Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-assisted C–V analysis. Under positive gate stress, small negative V th shifts (low stress) and a positive V th shifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-trapping energy ≈2.95 eV. UV-assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors.

V ertical GaN technology [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] is developing rapidly and, in particular, trench-MOSFETs [8][9][10][11][12][13] are attracting an ever increasing attention owing to their potential applications in the power conversion field. 16) For continued growth of this technology, the study and minimization of threshold instabilities is a fundamental step. Al 2 O 3 dielectrics have emerged as a dominant choice for developing vertical MOS technologies. 17,18) Recent works 19,20) indicate three prevalent trapping locations within the Al 2 O 3 /GaN MOS devices, responsible for V th shift: (i) states within the bulk dielectric, (ii) near-interface or border sites, and (iii) states along the oxide/ GaN interface. While the presence of the former two are oxidedependent, the interface state density (D it ) reflects the quality of the dielectric/semiconductor boundary, and of the process. Despite the importance of these trapping processes, these aspects have been studied only preliminarily by previous reports, 17,21,22) and a comprehensive description still needs to be published.
The aim of this paper is to contribute to an improved understanding of V th shift in semi-vertical GaN devices, and to provide in-depth perspectives on the physical origin of the trapping processes. To this aim, we integrated several analytical techniques to investigate the trapping processes and the associated recovery dynamics: pulsed measurements, transient investigation, light-assisted de-trapping, capacitance-voltage measurements.
The original results obtained within this paper demonstrate that positive gate voltage stress can trigger multiple trapping mechanisms contributing to strong positive and weak negative V th shifts due to trap states across the metal/Al 2 O 3 /GaN layers. Light energies above 2.9 eV (≈0.8 eV from E C ) are found to assist in faster recovery from semi-permanent trapping states in the bulk oxide and/or interface. Photo assisted CV measurements yield the interface trapped charge distribution (D it ) for the gate stress of 5 V which indicates prevalence of shallow traps, located mostly at ⩽0.3 eV from the conduction band (E C ).
The devices are normally-off GaN trench MOSFETs grown on a silicon substrate by MOCVD, 23) with a 35 nm Al 2 O 3 dielectric. The epitaxial GaN layers include a stress compensation layer, a thick and lightly doped drift layer and a doped p-body (see. Fig. 1).
The device has a semi-vertical configuration. This term refers to the fact that the flow of current in the experimental structure is not fully vertical, since the drain current is collected laterally through a n+ layer, and not vertically through the silicon substrate. The n+ top layer (250 nm) sources the electrons which then flow vertically through the channel in the p+ GaN layer (400 nm) along the gate trench sidewalls to reach the n− GaN drift layer (750 nm). A highly doped drain n+ region is integrated in the epitaxial stack such that the current flows laterally through this layer, before being routed back to the surface through the drain metallization.
To preliminarily evaluate device dynamic behavior and stability of V th under positive gate stress, we performed double pulsed measurements 24) that evaluate threshold instabilities within a short time scale (μs), thus capturing relatively fast trapping processes. The setup switches between quiescent (V G,Stress : 0-5 V for t Q = 100 μs and V D,Stress = 0 V) and measurement (V GS = −1 to 7 V at V DS = 8 V, t meas = 1 μs) conditions. Figure 2 displays the corresponding I D -V G behavior for the cumulative stress procedure on a typical device. The threshold voltage is defined as the voltage intercept at I D = 5 mA mm −1 which reflects a clear trend with change in V G,Q . The results emphasize a monotonic increase in V th with higher quiescent V G , with a maximum positive ΔV th >1.2 V for V G,Q = 5 V in Fig. 2(a). This high ΔV th arises from (i) the fast pulsed measurement configuration and (ii) the absence of recovery intervals between increments in quiescent stress V G,Q . The shifts are semi-permanent with only 10%-20% recovery after several minutes following V G,Q = 5 V. Typically, it could take from several hours to days to achieve 80%-90% recovery in V th .
When the experiment was repeated under exposure to high energy photons, as presented in Figs. 2(b) and 2(c), ΔV th is found to be smaller with a distinct wavelength dependence [see. To better investigate the semi-permanent nature of the positive V th shift under high fields, we employed a versatile setup capable of accurately evaluating threshold transients in the 10 μs-100 s range, 18,25,26) and re-evaluated V th transients under monochromatic light excitation. Here, a typical measurement is composed of a stress and a recovery phase of 100 s each, during which V th evolution is extracted from 22 fast I D -V G measurements (t meas = 10 μs). Figure 3(a) presents the stress phase V th transients obtained for V G,Stress ⩽ 5 V, where stress phases are separated by recovery intervals at (V G ,V D = 0 V, 0 V). To describe the energetic distribution of slow-emitting traps responsible for the positive ΔV th , Fig. 3(b) illustrates recovery phase V th transients at (V G ,V D = 0 V, 0 V) for measurements under light of λ = 365-760 nm, following equivalent stress phases (100 s at V G,Stress = 5 V). From Fig. 3(a), we discern a negative V th shift trend (≈0.07 V at 100 s) induced during the low gate stress of V G,Stress = 1 V, and also weakly observed for V G,Stress = 2 V. Similar small negative V th shifts were noticed for several devices, for stress times >10 s, under V G,Stress ⩽ 2 V conditions. This negative shift is not observable in the previous double pulsed measurements because other mechanisms (contributing to positive ΔV th ) probably dominate for the relatively fast stress/measurement intervals chosen [total t Stress at a given V G, Q builds up to only 40 × 100 μs = 4 ms for the 40 point I D V G curves in Fig. 2(a)]. The negative ΔV th trend at low stress biases can be ascribed to de-trapping of electrons from pre-existing states in the dielectric towards the metal. 17,27) V G,Stress = 3 V and higher induce positive V th shifts, proportional to the stress bias and time. In the full timerange between 10 μs and 100 s of a single V G,Stress = 5 V phase, a strong positive ΔV th ∼ 0.75 V [ Fig. 3(a)] is induced. Under dark conditions, this shift is only partially recoverable (calculated from negative shifts in V th during the recovery phase, absolute recovery ∼0.35 V) within the 100 s recovery window following the stress (not shown). A potential mechanism has been reported in other work, 28) where the recoverable degradation component has been attributed to electron injection from GaN into border traps close to the Al 2 O 3 /GaN interface, aligned near E C . On the removal of stress and restoration of the Fermi level, these traps would reemit to the GaN layer.
However, especially for high V G,Stress , recovery is dependent on a dominantly slow detrapping process. It can be hypothesized that under high stress fields, in addition to the contribution of border and interface traps, injected electrons from the GaN channel can travel further into the oxide or occupy energetically deeper trap states. Recovery from such traps could take days or weeks to complete, since electrons are semi-permanently stored in the insulator. To better capture this behavior, de-trapping during the recovery phase is accelerated through exposure to high energy photons, as presented in Fig. 3(b). The recovery phases for each wavelength in Fig. 3(b) are preceded by equivalent 100 s stress phases at V G,Stress = 5 V. Thus, the recovery behavior at each λ describes the device response after an induced positive ΔV th ≈0.75 V. The threshold energy for enhanced de-trapping, corresponding to the lowest energetic position of deep bulk states, appears to be 2.95 eV [420 nm, Fig. 3(c)]. A complete ΔV th recovery i.e. negative V th shift ≈0.75 V is achieved within 100 s with 395 nm [3.1 eV, Fig. 3(b)]. Thus, the presence of trap states between these energies: 2.9-3.1 eV (≈0.8-1.0 eV from E C , considering a Al 2 O 3 /GaN E C offset =2.16 eV 29) ) can be recognized (see Fig. 4).  Once dark conditions are restored, such states would gradually re-trap, corresponding to the stable device V th .
Thus, from the measurements in Figs. 2-3, the mechanisms contributing to V th shifts in these devices can be summarized as illustrated in Fig. 4.
(i) For low voltage (V G ⩽ 2 V), a small negative V th shift (<0.1 V) is attributed to the de-trapping of electrons from gate insulator towards the metal [Mechanism M1 in Fig. 4(a)]. (ii) For medium to high stress voltages (2 V < V G < 4 V), in addition to M1, positive ΔV th (≈0.2-0.3 V) due to electron trapping from the semiconductor towards border states in the dielectric [Mechanism M2_V LOW in Fig. 4(a)] becomes relevant. This process is reversible on removal of the stress. (iii) For high stress voltage (V G > 4 V), strong positive V th shifts (>0.5 V) are dominant, and recovery becomes significantly slow (several hours to days). This is attributed to the aggravation of M2 [M2_V HIGH in Fig. 4(b)] under high fields, involving electron transport from the GaN channel towards the metal, inducing trapping into deep states, along the interface or in the bulk of the dielectric. Even when stress is removed, deeper trap levels remain occupied. Exposure to light with energy higher than ≈2.9 eV is essential to enable accelerated recovery. Finally, we employ the photo-assisted capacitance-voltage or UV-CV 30) method that evaluates the distribution of interface states, D it , as illustrated in Fig. 5. Devices are exposed to UV light for 50 s in depletion in order to empty all electron traps, followed by 500 s in the dark to allow excess carriers to leave the system. Then, the de-trapped CV curve is measured [see. Fig. 5(b)] from 0 to 5 V. Bias at V G = 5 V is maintained for a moderate stress time of 80 s, so as to induce charge trapping at insulator and interface but without significant alteration of the capacitance level. Finally, the C-V curve of the trapped device is measured. The D it profile reported in Fig. 5(a) can be computed from the experimental data in Fig. 5(b) by using the procedure and the equations described in Ref. 30. The major parameters important for accurate calculation of D it are the displacement between the detrapped and trapped C-V curves, oxide area, and the effective doping of the semiconductor channel. The difference in slope allows the extraction of D it for trap energies across the entire GaN bandgap, whereas the rigid shift in the curves is proportional to the amount of charge trapped in the bulk of the oxide and/ or in border traps. This paper presents a detailed investigation into the threshold voltage instability of GaN-on-Si semivertical FETs. Based on combined electrical and optical measurements, we identify different mechanisms as responsible for V th shift: (i) at low stress voltages, a negative V th shift (M1 in Fig. 4) is observed, possibly related to detrapping of electrons from oxide states; (ii) at intermediate voltages, a moderate positive V th shift (M2_V LOW in Fig. 4), which is fully recoverable, has been associated to electron injection from the channel to near interface or border traps; (iii) at higher voltages, trapping might extend to deeper energy states or further into the dielectric bulk, which would yield greater V th shifts (M2_V HIGH in Fig. 4) with substantially longer de-trapping constants. Tests under different wavelengths were used to identify the threshold energy for de-trapping: the results identify the presence of deep-trap states within the insulator (threshold energy between 2.95 and 3.1 eV), that can be responsible for the semi-permanent trapping seen at high stress voltages. The results presented within this paper describe the dominant trapping processes for GaN-on-Si semi-vertical FETs, and general guidelines for the analysis of the related mechanisms, thus complementing the current knowledge on GaN vertical stability and reliability. 31)