Sub-50 mV power supply, recursive stacking body bias NAND gate for extremely low-voltage CMOS LSIs

This paper presents a recursive stacking body-bias NAND for extremely low voltage application. Our proposed NAND utilizes recursive-stacking and body-bias techniques to achieve extremely low-voltage operation. The former suppresses off-leakage current of MOSFETs and enhances the voltage gain of the NAND gate. The latter achieves on-current enhancement and the voltage gain improvement of the NAND gate. Performance improvements of our proposed NAND gate are theoretically analyzed and discussed. Simulation of our proposed NAND gates showed that voltage transfer curves, voltage gains, and voltage swings were improved significantly. A prototype chip was fabricated in a 180 nm CMOS process and demonstrated that the voltage swing of the proposed NAND was 44.1 mV at 50 mV power supply, which was 16.4 mV improvement compared to that of the standard NAND gate, at the cost of area, power, and delay time.


Introduction
A large number of internet-of-things devices have attracted significant attention because they are expected to be key devices for next generation smart and intelligent systems.To realize such devices, power/energy management is one of big challenges.Although these devices are mainly powered by batteries today, replacement and maintenance of batteries are important issues.][3][4][5] Systems using thermal energy, [6][7][8][9][10][11][12][13][14] solar energy, [15][16][17] and electromagnetic energy, 18) have been developed and reported.
Among several energy harvesting techniques, thermoelectric generators (TEGs) are promising candidates as power sources for wearable devices because they can generate electric energy from a small temperature difference between the human body and the atmosphere.However, the output voltage is quite low under a small temperature difference (i.e. less than 100 mV).Hence, we must develop highly efficient power management circuits capable of starting an operation at low input voltage.However, some works have no low-voltage start-up circuits, 6,7) and others start its operation with one-time pre-charge of the output. 8,9)][14] Therefore, we must explore and develop extremely low-voltage (ELV) circuit design techniques.
In this paper, we present a recursive stacking body-bias NAND (RSBB-NAND) that can operate at extremely low supply voltage V DD .In contrast to our previous work, 23) we discuss the problems of ELV circuit design and describe our proposed RSBB-NAND in detail.The key concept of our proposed RSBB-NAND is based on the RS-BBI, 22) and we expand it to the NAND gate design.The RSBB-NAND utilizes recursive stacking and body-bias techniques to achieve extremely low voltage operation.Measurement results of prototype test chips demonstrate that our proposed RSBB-NAND can operate at extremely low V DD .

Extremely low-voltage logic gates
Before discussing our proposed NAND gate, we briefly summarize the problems of ELV logic gate and discuss conventional low-voltage CMOS inverters.

Problems at extremely low-voltage
Figure 1 shows the simulated voltage transfer curves (VTCs) of a NAND gate at different V DD s and their voltage gains obtained from the VTCs.In this simulation, we set one of the two inputs of a NAND gate to V DD and then regarded the NAND gate as an inverter.As shown in the figure, the simulated voltage swings and gains decreased as the V DD decreased.The reason for the voltage gain reduction was that the transconductance g m of MOS transistors also degrades as the V DD decreased.The reason for the voltage swing reduction can be explained as follows.
The output voltage of a CMOS logic gate is determined by on and off currents, or I ON and I OFF .When the V DD is high enough, a current ratio of I ON over I OFF is quite large and the output voltage can be determined clearly.However, when the V DD becomes extremely low, the I ON decreases significantly and the current ratio also decreases.This causes the output voltage degradation.Figure 2 illustrates the high and low logic level degradation at extremely low V DD (e.g.V DD = 50 mV).The I ON decreases significantly and is close to the level of I OFF .As shown in Fig. 2, high logic level decreases from V DD , while low level logic increases from ground, because the output voltage of the logic gate is determined by the condition where I ON = I OFF .Therefore, the voltage swing decreased at extremely low V DD .
From these discussion, control techniques for the I ON -enhancement, I OFF -suppression, as well as the voltage gain enhancement technique, are strongly required for extremely low V DD logic gates.

Conventional low-voltage inverters
Figure 3 shows conventional low-voltage inverters.As discussed, the VTC of the normal inverter degrades as the V DD decreases.To improve the VTC of an inverter, Bose   . 22)The RS-BBI is based on the SBBI and stacks additional inverters top and bottom of the inverter recursively.
As seen above, low-voltage inverters have been studied and demonstrated.However, low-voltage combinational logic gates have not been explored well yet.In the following, we propose our low-voltage NAND gate.

Proposed NAND gates
Figure 4 shows our proposed recursive stacking body-bias NAND (RSBB-NAND).The concept of the RSBB-NAND is based on the RS-BBI. 24)By stacking additional NAND gates top and bottom of the NAND recursively (RS-NAND), the I OFF -suppression and the voltage gain improvement are achieved.In addition, by employing the body-bias technique for RS-NAND, we can realize recursive stacking body-bias NAND gates (RSBB-NAND), and both the I ON -enhancement and the voltage gain improvement are achieved.Details of these techniques are described as follows.
3.1.Recursive stacking technique 3.1.1.I OFF -suppression.The subthreshold MOS transistor current I D for a gate-source voltage V GS and drainsource voltage V DS is expressed as [25][26][27][28] ( ) 2 is the prefactor of the subthreshold current, μ is the mobility, C OX is the gate-oxide capacitance, W and L are the channel width and length, η is the subthreshold slope factor, V T (= k B T/q) is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and V TH is the threshold voltage of the MOS transistor.
As shown in Eq. ( 1), the I OFF can be suppressed by reducing V DS (note that I OFF is the current when V GS = 0).In the conventional NAND gate, source nodes of PMOS transistors are set to V DD , while that of bottom side NMOS transistor is set to ground.To suppress the I OFF , we consider controlling the source nodes of PMOS transistors and that of bottom side NMOS transistor in the NAND gate.
Figure 5 illustrates conceptual schematics of our proposed I OFF -suppression technique.Four input cases are depicted.When the output voltage is supposed to be "1" [see Figs.5(a), 5(b), and 5(c)], I OFF can be suppressed by setting the source node of the bottom-side NMOS transistor to "1".On the other hand, when the output voltage is supposed to be "0" [see Fig. 5(d)], I OFF can be suppressed by setting the source nodes of the PMOS transistors to "0".
Therefore, I OFF can be suppressed by setting the source nodes of each transistors to the same output logic of the NAND gate.In addition, I OFF can further be suppressed by stacking NAND gates recursively.3.1.2.Gain-enhancement.We proposed the recursive stacking technique as discussed above.The technique can not only suppress I OFF , but also improve the voltage gain. 19)igure 6(a) shows a schematic of the NAND gate.As discussed earlier, the NAND gate is regarded as an inverter when we set one of two inputs to "1".The voltage gain of the NAND gate, or inverter, is given by 03SP87-3 © 2024 The Japan Society of Applied Physics where g mp and g mn are the transconductance of M6 and M7, respectively, and r op and r on are the output impedance of M6 and M7, respectively.We ignore the effects of M5 and M8 for simplicity.
When we stack NAND gates as shown in Fig. 6(b), transconductance of the transistors increases by the voltage gain of the stacked NAND gates.Figure 6(b) shows a schematic of the stacked NAND gate when we set one of two inputs to "1".We also ignore the effects of transistors that "1" is applied to for simplicity.The input signal V in is amplified by the NAND gates, and node voltages at V a and V b becomes −A 1 V IN and −A 3 V IN , respectively, where A 1 and A 3 are the voltage gain of the NAND1 and NAND3.Therefore, gate-source voltages of PMOS and NMOS transistors in NAND2 can be expressed as (1 + A 1 )V in and (1 + A 3 )V in , respectively.As a result, the voltage gain of the stacked NAND is expressed as The voltage gain of the stacked NAND gate can be improved.As in the I OFF -suppression, the voltage gains of NAND1 and NAND3, or A 1 and A 3 , can also be enhanced by stacking NAND gates recursively.
3.2.Body-bias technique 3.2.1.I ON -and gain-enhancement.For ELV operation of the logic gates, the body-bias technique is effective to enhance I ON and the voltage gain.The technique has been employed in the BBI and body-bias NAND (BB-NAND) gate. 20,24)Figure 7 shows a gate-and transistor-level schematics of the BB-NAND.The BB-NAND consists of a main NAND and feedback inverter.The output of the feedback inverter is connected to the body of the main NAND and controls the threshold voltages of the main NAND's transistors.This enables us to enhance I ON of the transistors.
The body-bias technique can also improve the voltage gain.The voltage gain of the BB-NAND is modified from Eq. ( 2) and is rewritten as where A FB is the voltage gain of the feedback inverter, g mbp and g mbn are the body-source transconductance of PMOS and NMOS transistors.
The body-bias technique can also be applied to our proposed RS-NAND gate. Figure 4(b) shows the schematic of the RSBB-NAND.The body bias voltage can be controlled simply by the feedback inverter (the feedback inverter is not shown).As discussed above, the voltage gain of RSBB-NAND increases significantly.03SP87-4 © 2024 The Japan Society of Applied Physics 4. Results

Simulation results
We simulated our proposed RSBB-NANDs with a set of 0.18 μm standard CMOS process technology with a deep n-well option.To confirm the effectiveness of the stacking technique, recursive stacking NAND (RS-NAND) gates without the body-bias technique were also evaluated.In addition, a conventional NAND gate was also simulated for comparison.In this simulation, the rule of design is that when stacking, the NANDs connected to the PMOS source node double the number of PMOS transistors in parallel, and the NANDs connected to the NMOS source node double the number of NMOS transistors in parallel.This rule also applies to recursive stacking.This is to increase the effectiveness of the stacking.We set one of two inputs of NANDs to "1" and regarded them as inverters.
Figure 8 shows the simulated VTCs of the NANDs at V DD = 50 mV.The amplitudes of the proposed RSBB-NANDs were higher than that of conventional NAND and improved as the number of stacking devices increased.The voltage swings of 3RS-NAND and 3RSBB-NAND were improved by 36% and 44%, 1 respectively, compared with that of the conventional NAND.There was no significant difference between when 1 was input to A and when 1 was input to B. Note that the hysteresis characteristics were found in the VTCs.These were caused by the body bias technique. 24)igure 9 shows the simulated voltage gain of the NANDs.The voltage gain of 3RS-NAND was higher than that of conventional NAND.Furthermore, the voltage gain of RSBB-NANDs was clearly improved.There was no significant difference between when 1 was input to A and when 1 was input to B. The reason for the two peaks was the hysteresis characteristics due to the body-bias technique.
Figure 10 shows the simulated normalized amplitude of as a function of V DD .The amplitudes of RSBB-NANDs exceeded that of conventional NAND at each V DD .There was no significant difference between when 1 was input to A and when 1 was input to B.
Figure 11 shows the simulated current consumption of 3RSBB-NAND as a function of input voltage.The supply voltage was set to 50 mV.We set one of two inputs of NANDs to "1" and regarded them as inverters.The maximum and minimum short circuit currents were 17.8 and 13.2 nA, respectively (i.e.0.89 and 0.66 nW power consumption, respectively).As Figs. 8 and 9, we also found the hysteresis characteristics due to the body-bias technique.In addition, we also simulated the dynamic power of the 3RSBB-NAND when V DD and input clock frequency were set to 50 mV and 1 kHz, respectively.As a load, the same 3RSBB-NAND was connected to the output.The simulated dynamic power of the 3RSBB-NAND was 0.75 nW (the power when we changed the input roles was the same).
Note that the TEG device we use has maximum output voltage and current of 120 mV and 9 mA, respectively, with a temperature difference of 10 K. 29) With the device, we can use 250 000 gates with keeping the TEG voltage higher than 60 mV.However, our proposed NAND gate uses many (b) 03SP87-5 © 2024 The Japan Society of Applied Physics transistors, resulting in large silicon area.Thus, we need to consider the trade-off between low-voltage operation and area penalty.
Figure 12 shows the simulated VTCs at different process corners.We set V DD to 50 mV and considered typicaltypical, fast-fast, slow-slow, fast-slow, and slow-fast (TT, FF, SS, FS, and FS) corners.Our proposed NAND operated correctly at TT, FF, and SS corners, while not at SF and FS corners.As discussed in the literature, threshold voltage balance is quite important for low-voltage circuit design. 30,31)

Measurement results
We fabricated prototype test chips of our proposed 3RS-NAND and RSBB-NANDs using the same process technology as the simulation.A conventional NAND was also fabricated in the same chip for comparison.Figure 13 shows a chip micrograph.The areas of 3RS-, 1RSBB-, 2RSBB-, 3RSBB-, and NAND were 8991, 1937, 3669, 11 560, and 594 μm 2 , respectively.By adding stacking devices, the number of MOSFETs increased, resulting in larger chip area.As in the simulation, we set one of two inputs to "1" and regarded the NANDs as inverters.
Figure 14 shows the measured VTCs at V DD = 50 mV.As with the simulations, the amplitudes of the proposed RSBB-NANDs were higher than that of conventional NAND and were improved as the number of stacking devices increased.Note that we used source follower buffers to eliminate the effect of the parastics.Therefore, the output voltages were shifted by about 270 mV.The voltage swings of the 3RS-NAND and 3RSBB-NAND were improved by 31% and 59%, respectively, compared with that of the conventional NAND.The trip points moved slightly higher than those of simulated results.We think this was caused by the process variations and the threshold voltage balance moved toward SF corner.Figure 16 shows the measured input and output waveforms of the 3RSBB-NAND.We set one input to VDD = 50 mV and applied a buffered input pulse to the 3RSBB-NAND.The inverted output pulse was obtained with the delay of 174.5 μs, while it was 199 μs when we changed the input roles.
Table I summarizes the performance of NANDs.As can be seen, the voltage swings and the delay of the RSBB-NANDs improved and increased, respectively, as the number of stacking devices increased at the cost of the area penalty (the number of transistors) and delay.Compared 3RSBB-NAND with 3RS-NAND, the delay of the 3RSBB-NAND increased longer than 100 μs, due to the large capacitor for the body-bias technique.

Conclusion
In this work, we proposed RSBB-NAND gates as a fundamental logic gate capable of operating at extremely low supply voltage.The proposed RSBB-NAND employs recursive-stacking and body-bias techniques to improve output voltage swing and voltage gain.Simulation of our proposed NAND gates showed that voltage transfer curves, voltage gains, and voltage swings were improved significantly.A prototype chip was fabricated in a 180 nm CMOS process and demonstrated that the voltage swing of the proposed NAND was 44.1 mV at 50 mV power supply, which was 16.4 mV improvement compared to that of the standard NAND gate, at the cost of area, power, and delay time.03SP87-8 © 2024 The Japan Society of Applied Physics

Fig. 1 .
Fig. 1.(a) Voltage transfer curves (VTCs) of NAND gate at different V DD s and (b) voltage gains obtained from the VTCs.

Figure 15
Figure15shows the measured normalized amplitude of as a function of V DD .The amplitudes of RSBB-NANDs exceeded that of conventional NAND at each V DD .Figure16shows the measured input and output waveforms of the 3RSBB-NAND.We set one input to VDD = 50 mV and applied a buffered input pulse to the 3RSBB-NAND.The inverted output pulse was obtained with the delay of 174.5 μs, while it was 199 μs when we changed the input roles.TableIsummarizes the performance of NANDs.As can be seen, the voltage swings and the delay of the RSBB-NANDs improved and increased, respectively, as the number of stacking devices increased at the cost of the area penalty (the number of transistors) and delay.Compared 3RSBB-NAND with 3RS-NAND, the delay of the 3RSBB-NAND increased longer than 100 μs, due to the large capacitor for the body-bias technique.

Table I .
Performance summary.
a Voltage swings and delay times were obtained by setting one of two inputs to "1" alternately 03SP87-7 © 2024 The Japan Society of Applied Physics