Characterization of deep traps in the near-interface oxide of widegap metal–oxide–semiconductor interfaces revealed by light irradiation and temperature change

In photo-assisted C–V measurements, the occupancy ratio of the deep levels is forcibly changed by the light irradiation under a depletion bias. After stopping the irradiation, C–V measurement is conducted where the density of deep level traps can be quantified from the hysteresis width of the C–V curve because the trapped charges are once excited by the light irradiation in the depletion state, but re-captured when the accumulation bias is applied. ^21–23) In this study, we continuously change the wavelength of light to estimate the energy distribution of deep levels. The trap energy level that should be forced to become vacant by light can be tuned by changing the wavelength as schematically shown in Fig. 2 for the case of p-type substrates. For this case, the trapped charges will be excited when their energy levels referred to as the valence band edge (E_V) are less than the energy of light, while the energy levels should be referred to as the conduction band edge (E_C) for n-type. Note that this study uses only the light with photon energy well below the bandgap energy in contrast to the conventional photo-assisted C–V measurements where UV light with the energy above the bandgap is employed. Figure 3 shows typical photo-assisted C–V curves obtained at different wavelengths, L1 and L2. The small plateau observed in C–V curves around the region of maximum hysteresis will be approximately corresponding to the surface potential where the Fermi level comes closer to the energy level with the high density of the traps. But we do not focus on this energy level to avoid the ambiguous discussion to determine such levels under the possible influences of light-induced excitation of carriers. In this study, the amount of de-trapped charges will be detected as the maximum hysteresis width (ΔV_L1 and ΔV_L2, respectively) in the C–V curves of each wavelength.

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With this method, we newly define the effective interface trap state density (D_eff) by Eq. (1), using the difference of the number of traps (${C}_{{\rm{ox}}}{\rm{\Delta }}V/qE$) observed at different light energies, where C_ox is the oxide capacitance, q is an elemental charge, and E is the light energy

$$\begin{eqnarray}&&{D}_{{\rm{eff}}}=\displaystyle \frac{{C}_{{\rm{ox}}}\left({\rm{\Delta }}{V}_{L1}-\,{\rm{\Delta }}{V}_{L2}\right)}{q\left({E}_{L1}-{E}_{L2}\right)\,}.\end{eqnarray} \tag{ 1 }$$

Note that D_eff gives the total effective density of trapping states for a unit area, including not only the deep interface traps located on the surface of the semiconductor but the NITs located in oxide ∼Å or ∼nm away from the MOS interface. Note that the oxide traps located further than ∼nm are not taken into account as NIT in this study due to the very long time constant, which will be discussed later. Therefore, the traps with a wide variety of time constant are detectable by this measurement, except for very slow traps with a time constant longer than the sweeping time of C–V measurement (100 s, in our experiments).

Here it is worth mentioning how we can excite the trapped electrons in the region covered by gate electrode, even though we employ a nontransparent Au as the gate material. To consider the light delivery to the region covered by the gate, we should remind that the absorption coefficient of SiC for visible light is so small that the light can penetrate the whole substrate easily. If we have a back contact electrode, we expect a sufficient intensity of visible light reflection on the backside. This reflected light can reach even the area covered by a gate. Actually, we confirmed that the electrode size of 1.5 × 10⁻⁴ ${{\rm{cm}}}^{2}$ as small enough to excite the carriers under depletion bias by ∼1.8 eV UV light to observe the achievement of the inversion state using the same monochromator setup, while the electrode size beyond 3.0 × 10⁻⁴ ${{\rm{cm}}}^{2}$ results in smaller response. Thus, the electrode size ∼5 × 10⁻⁵ ${{\rm{cm}}}^{2}$ in this study is considered to be small enough to excite the trapped carriers in the oxide sufficiently under depletion bias. The validity of our experimental set up in terms of light intensity and irradiation time was also examined. From the light intensity dependence of hysteresis width with some of the wavelengths employed in the experiment, the hysteresis width was found to saturate when the light intensity was above 50% of the maximum intensity of the system. So, the maximum light intensity of the system in this experiment was confirmed to be sufficient to discuss the density of the trapped charges quantitatively. The appropriate light irradiation duration was also examined by observing the saturation behavior in the hysteresis width in the C–V curves. In our measurement, the irradiation time was set to 3 min because the hysteresis width was almost saturated by the irradiation for 3 min or more which was confirmed for some typical wavelengths.

In Fig. 4, D_eff determined from photo-assisted C–V measurements using Eq. (1) at 300 K are shown for both samples on p-type and n-type substrates, together with the energy distribution of D_it estimated by the high–low method using 1 MHz and 1 kHz. Without light irradiation, the hysteresis width of C–V curves was below 0.1 V. Both wet-POA and NO-POA improved the interface quality in terms of D_it, to achieve a similar D_it ∼ 10¹¹ cm⁻² eV⁻¹ at 0.2−0.5 eV from the conduction band edge (for n-type substrate samples) or the valence band edge (for p-type substrate samples). Even with a similar D_it, the difference in interface quality between those samples with different POA treatments was clearly revealed by photo-assisted C–V measurements at room temperature. From D_eff profiles, it can be seen that both samples showed effective trap state densities of 10¹²−10¹³ cm⁻² eV⁻¹ for energy levels from 0.8 to 2.2 eV referred to E_V, However, near midgap state from 1.5 to 2.2 eV referred to E_v, the sample with NO-POA showed a broad energy profile whereas those trap state densities are almost suppressed (less than the detection limit of D_eff) for the sample with wet-POA. Instead, in the region of 1.5 eV, a small peak of D_eff was detected. It can be the characteristic trap of the wet-POA.

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Next, we would like to discuss the possible origins of such deep traps revealed in this study by considering several candidate defect structures though we cannot determine which is the most probable one only from our experimental results. Simulation studies have been made on the expected energy levels of possible deep traps formed near the SiO₂/SiC interface with various origins. ^24–27) As for the origins of the deep traps on the valence band side (0.7−1.6 eV referred to E_v), Si–CO–CO₂ (0.7 eV), (C₂)_Si (0.9 eV and 1.5 eV), Si–(CO)–CO₂ (0.8 eV) and (C_i)_C (0.8 eV) may be the candidates considering its suggested energy levels. On the other hand, the possible candidates of the origin of the deep traps on the conduction band side (1.6−2.3 eV referred to E_v) would be Si₃–C (2.2 eV), C₆-ring (2.2 eV), Si–O–O–Si (2.3 eV) and (C_i)_C (1.7 eV). Since the enhancement of the removal of CO from the SiO₂/SiC interface by H₂O ²⁸⁾ is expected for wet-POA, the significant reduction of near midgap states by wet-POA may be related to such structures consisting of C and O atoms. Especially in the region of 1.5−2.2 eV, some of the deep states were reduced efficiently by wet-POA, though we cannot specify the most probable defect structure corresponding to that energy region only from our experimental data. Note that all of these candidate defect structures are carbon-related or carbonyl-induced defects and are characteristically present at the SiC MOS interfaces.

Hysteresis measurements, like photo-assisted C–V measurements, are the effective way to evaluate the NITs as we have discussed so far. However, a major restriction of the hysteresis measurement is the fact that the traps with a longer time constant than the voltage-sweeping time of C–V measurement cannot be detected. Note that the time constant of charge trapping $(\tau )$ in NITs is generally approximated to be proportional to Fermi–Dirac function, which is given by Eq. (2) as an exponential function of measurement temperature, when we assume that the tunneling process in oxide from the interface to the trap is the rate-determining step of the carrier trapping process. ^29,30)

$$\begin{eqnarray}&&\tau \,\left(\chi ,\,T\right)=F\left(E,\,T\right){\tau }_{0}\left(E\right)\exp \left(2\kappa \chi \right)\,,\end{eqnarray} \tag{ 2 }$$

where T is the measurement temperature and ${\tau }_{0}\,\,$is the time constant of the interface traps which weakly depends on T. $\chi$ is the tunneling distance of the traps. The notation $\kappa \,\,$is the tunneling attenuation factor for an electron wave function of energy E, which is a function of the tunneling mass of electrons (m^*). ³¹⁾ F defines the ratio of available sites working as a receptor of tunneling electrons. The factor $\exp \left(2\kappa \chi \right)$ expresses the attenuation of tunneling probability for a given tunneling distance. It should be noted that the $\tau$ of de-trapping is strongly dependent on T because of the temperature dependence of F. For example, the estimated $\tau$ at 173 K becomes a few orders larger than that of 300 K. Here we assume as the effective mass, 0.30 m₀ for electrons and 0.58 m₀ for holes, respectively, ^32,33) where m₀ is the mass of the free electron. As for the band offset, ${E}_{C}^{{\rm{ox}}}$−${E}_{C}^{{\rm{SiC}}}$ at the SiC/SiO₂ interface was set to 2.7 eV where ${E}_{C}^{{\rm{ox}}}\,\,$is the conduction band edge of oxide and ${E}_{C}^{{\rm{SiC}}}$ is that of SiC. ^34,35) Using the above assumptions and mathematical relationships given in the literature, ${\tau }_{0}\left(E\right)$ and $\kappa$ were approximately estimated. As a result, the temperature dependence of the approximate time constant of the traps with different distance from the interface were calculated ³⁴⁾ as shown in Fig. 5. Since our photo-assisted C–V measurements were conducted with the voltage sweep rate ∼100 mV s⁻¹, we can roughly estimate the detection range of the location of the oxide traps from the relationship in Fig. 5. Note that the measurements at lower temperature will detect only the spatially shallower (closer to semiconductor) oxide traps than those at room temperature, as illustrated in Fig. 6 for the case of hole-trapping. Thus, the photo-assisted C–V measurements at various temperatures can reveal the approximate depth profile of NITs.

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The D_eff profile observed at lower temperatures (223 K and 173 K) on both p-type and n-type substrate samples is shown in Fig. 7 for the cases of (a) NO-POA and (b) wet-POA, respectively. As mentioned above, those low-temperature data are indicating the oxide trap density located closer to MOS interfaces than the ones observed at room temperature. From the figure, it is found that the effective trap state density in the region closer to the interface (173 K) seems to be a few times smaller than the one detected in the wider region (300 K) for the samples with NO-POA for the whole energy levels. On the other hand, for the sample of wet-POA, those in the region closer to the interface (173 K) is much smaller than those for the sample with NO-POA. It may seem strange that D_eff observed at 300 K for the energy range from 0.5 to 2.5 eV is smaller than that at lower temperatures. This is considered to be originated from a significant estimation error in the low temperature data, because of the coarseness of D_eff determination due to the large wavelength interval for low temperature measurements, as mentioned in Sect. 2. This experimental condition difference between the room temperature (0.2 eV interval) and the low temperature (0.4 eV interval) measurements is caused by our experimental facility limitation.

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Considering the quantitative relationship between $\tau$ and the distance of the traps from the interface shown in Fig. 5, the detectable distance at 173 K by ∼100 mV s⁻¹ voltage sweep measurement was roughly estimated to be around half of that at 300 K as shown in Fig. 6. From D_eff profiles observed at lower temperatures, it can be seen that the sample with NO-POA showed higher effective trap state densities for whole energy levels than wet-POA sample. Our results would be reasonable if we assume an almost uniform spatial distribution of D_eff for NO-POA sample in the region within ∼1 nm distance from the MOS interface. On the other hand, D_eff detected at 173 K for the sample with wet-POA is as small as the level of D_it, which means that wet-POA suppresses the oxide traps in the region within several Å from the MOS interface quite more efficiently than NO-POA for the whole energy levels. This can be consistent with the fact that the field-effect mobility in both NMOSFET and PMOSFET fabricated with optimized wet-POA on (0001) substrates is a little better than that fabricated with NO-POA. ^17,19)