A simulation study on memory characteristics of InGaZnO-channel ferroelectric FETs with 2D planar and 3D structures

In a cyber-physical society, a tremendous amount of data is collected by edge devices, and stored and processed by cloud servers. It is important to make full use of such big data to create innovative social services. However, it is often reported that the amount of available data at edge devices largely exceeds the data traffic around data centers. This gap is increasing and thus the role of edge devices will become more important. We think that edge devices will be required to have high-capacity yet low-power memory not only for storage but also for enabling edge AI computing such as machine learning.

As for high-capacity storage memory, NAND flash memory is the most cost-effective and the mainstream in the market. However, its power consumption and operation speed can be obstacles for edge devices that operate under the constraints of power supply. A ferroelectric FET (FeFET) is a one-transistor memory device that has a ferroelectric gate insulator in a FET structure. ^1,2) A FeFET realizes high threshold voltage (V_th) and low V_th by the direction of the ferroelectric polarization which can be switched by the gate voltage (V_g). A FeFET operates at low power and high speed due to its field-driven write operation. Since the discovery of CMOS-compatible ferroelectric HfO₂ (FE-HfO₂), the FeFET has attracted much attention for high-capacity memory applications. ^3–6)

NAND flash memory has migrated to a 3D vertical stack structure due to scaling challenges and the increasing demand for higher density. ^7–10) The same architecture is applicable to FeFETs. In fact, a 3D vertical FeFET with FE-HfO₂ has been demonstrated with a poly-Si channel. ^11,12) However, several challenges with the poly-Si channel have been raised regarding performance, reliability and low-voltage operation. ¹³⁾ Poly-Si may suffer from low mobility especially at an ultrathin film less than 10 nm due to the grain boundary and defects inside the grain. ¹⁴⁾ A low-k interfacial layer is inevitably formed between the FE-HfO₂ layer and the poly-Si layer, which causes reliability degradation by charge trapping and prevents low-voltage operation due to the large voltage drop at the interfacial layer. ¹²⁾

Oxide semiconductors such as InGaZnO (IGZO) have been developed for flat-panel display applications, ^15–18) and have been proposed as an alternative channel material to poly-Si for FeFETs ^19,20) [Fig. 1(a)]. IGZO-channel FeFETs may solve these challenges by their high mobility and the lack of low-k interfacial layer formation between an FE-HfO₂ layer and an IGZO layer. ^21–24) One key challenge of IGZO-channel FeFETs is their weak erase operation, ¹⁹⁾ which is a similar situation to that of 3D NAND flash memory. IGZO is an n-type channel material and a FET with an IGZO channel is an n-type junctionless transistor. Since minority carrier holes are hardly generated in IGZO, the body potential is not fixed but floating, and the ferroelectric polarization charge is not balanced with the charge in the IGZO layer during the erase operation. ²⁴⁾ Thus, the erase operation is not efficiently done [Fig. 1(b)]. Although it is known that a 3D structure facilitates the write operation in 3D NAND flash memory, ^25,26) the impact of a 3D structure on 3D FeFETs has not been fully discussed yet.

Zoom In Zoom Out Reset image size

To address the issue of the erase operation in IGZO-channel FeFETs and improve the memory window (MW), in this work, we study the memory characteristics of IGZO-channel FeFETs with 2D planar and 3D structures by TCAD simulation. We simulate single-IGZO FeFETs instead of actual series-connected transistors with the source and drain terminated at the end of the NAND string. In the 3D vertical architecture, each IGZO FeFET is an n-type junctionless transistor and connects to the source and drain in the string by applying pass voltage on the gates of the other series-connected transistors. Therefore, the study of single-IGZO FeFETs is relevant and applicable to the study of 3D vertical architecture. This paper is an extended version of short conference proceedings ²⁷⁾ including a detailed analysis and an entirely new section on a parametric simulation study on 3D structure FeFETs to provide device design guidelines for high-density memory applications.

We previously built a TCAD model for 2D planar FeFETs ^28–30) with IGZO channels ^19,24,27) which captured the essential physics and qualitatively reproduced the measurement results with the basic material parameters of FE-HfO₂ (HfZrO₂, HZO) and IGZO. In this work, we extend our TCAD model from a 2D planar to a 3D structure. As shown in Fig. 2, we simulated (a) single-gate (SG) planar FeFETs with a floating body, (b) double-gate (DG) planar FeFETs corresponding to FinFETs or nanosheet FETs, (c) macaroni (MAC) structure FeFETs similar to 3D NAND flash memory, and (d) nanowire (NW) structure FeFETs. For the MAC FETs, the inner core was filled with SiO₂. All devices were junctionless transistors with ohmic contact at the source and drain. The source and drain contacts were put on the side surface of the IGZO region and were aligned to the edge of the gate. The remanent polarization charge density (P_r) and the coercive field (E_c) of HZO were 23 μC cm⁻² and 1.16 MV cm⁻¹, respectively. To focus on the static characteristics, dynamic model parameters were not taken into account. The bandgap and the carrier concentration of IGZO were 3.2 eV and 10¹⁹ cm⁻³, respectively. Note that the ferroelectric thin film was modeled as a continuous medium and shows non-uniform ferroelectric polarization ³⁰⁾ in this work. The HZO thickness (t_HZO) was 10 nm, which is a practical value ensuring high ferroelectricity and low leakage current. The IGZO thickness (t_IGZO) and the NW diameter (d_IGZO) were fixed at 8 nm for the channel length (L) dependence in section 3.1. These parameters were varied for the study on the device design of MAC and NW FeFETs for different outer diameters (D) of the IGZO channel in the MAC and NW structures in section 3.2. These device parameters are depicted in Fig. 2. For the write operation, a bidirectional DC V_g sweep (±5 V) was applied, where 5 V is the program voltage and −5 V is the erase voltage. The MW was defined by taking the difference between the high V_th after erase and the low V_th after the program.

Zoom In Zoom Out Reset image size

3.1. Channel length (L) dependence of 2D planar and 3D structure FeFETs

First, we simulated SG planar FeFETs varying L. The simulated drain current (I_d) versus V_g curves are shown in Fig. 3. As L decreases, the MW rapidly increases in the sub-100 nm L region, while the short channel effect (SCE) is degraded with a large subthreshold swing. To discuss this L dependence of the MW, Fig. 4 shows the electrostatic potential and the polarization charge density for L = 100 nm and L = 30 nm in the erase state. In the case of long L, the electric field from the gate is concentrated near the source and drain. However, the center region of the IGZO layer is floating and the electric field from the gate is sparse. Thus, it is difficult to apply high voltage on the HZO layer and induce polarization switching around the center region of the HZO layer. In the case of short L, on the other hand, the regions where the electric field concentrates near the source and drain merge around the center of the IGZO layer. In other words, the source and drain electrostatically couples to the center region of the IGZO layer. Thus, the large electric field is applied on the HZO layer and polarization switching occurs even around the center region of the HZO layer. Such electrostatic coupling from the source and drain also gives rise to the SCE. Please note that some hump behavior is seen in the reverse sweep in Fig. 3. The IGZO FeFET is a junctionless transistor, which has body conduction near the flat-band region and surface conduction in the accumulation region. In our simulation conditions, after the surface channel is turned off, the body conduction near the top surface is not pinched off until sufficiently high negative V_g is applied. This leads to hump behavior.

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

Next, we simulated DG planar FeFETs varying L. The simulated I_d–V_g curves are shown in Fig. 5. The MWs of the SG FeFETs and the DG FeFETs are plotted against L in Fig. 6. The DG planar FeFETs show larger MWs with less SCE than the SG planar FeFETs. The DG structure can control the IGZO-body potential from both sides of the gate. Even though polarization switching only occurs near the source and drain in the erase operation as in the SG planar FeFETs, the DG FeFETs can efficiently cut off the channel as shown in the electrostatic potential in Fig. 7, and thus realize high V_th in the erase operation and the large MW.

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

Then, we simulated MAC FeFETs and NW FeFETs varying L. The simulated I_d–V_g curves are shown in Figs. 8(a) and 8(b) for the MAC FeFETs and the NW FeFETs, respectively. The MWs of the MAC and NW FeFETs are plotted against L in Fig. 9, where both FeFETs show large MWs compared to the SG FeFETs and the DG FeFETs. In particular, the NW FeFETs show the largest MWs for the entire L regions. There is much less L dependence in the NW FeFETs than in the other FeFETs. To understand such memory characteristics of the NW FeFETs, the NW diameter dependence of the I_d–V_g curves is studied. As shown in Fig. 10, the MW increases as the NW diameter decreases. This is mainly attributed to the electric field concentration in the 3D cylinder structure. In the NW structure, given V_g, the electric field is concentrated toward the inside of the HZO layer by Gauss's law. The larger MW in the NW FeFETs than in the MAC FeFETs is due to the smaller D in the NW FeFETs while t_HZO is the same for both FeFETs. The ratio of the inner surface area to the outer surface area of the HZO layer is lower in the NW FeFETs and thus the electric field is more concentrated in the NW FeFETs. The simulated polarization charge density along the channel direction in an NW FeFET is shown in Fig. 11(a), in which polarization switching occurs in the entire HZO layer in the erase operation. Figure 11(b) shows the electric field in the diameter direction, which clearly illustrates the electric field concentration.

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

3.2. Diameter (D) and IGZO thickness (t_IGZO) dependence of MAC and NW FeFETs

The actual design of 3D vertical FeFETs depends on available process technologies and layout constraints to achieve a high-aspect-ratio trench and high-density integration. In this section, we systematically investigate the diameter and IGZO thickness dependence of MAC and NW FeFETs to explore device design guidelines. R_IGZO is defined by t_IGZO/D to express the volume ratio of the IGZO layer to the total diameter. MAC FeFETs have R_IGZO < 0.5 and NW FeFETs have R_IGZO = 0.5. The t_HZO is fixed at 10 nm, which is a practical value ensuring high ferroelectricity and low leakage current. L is 50 nm, which is also a relevant value to 3D NAND flash memory and avoids severe SCE as seen in the previous section. Note that L is defined by the deposition thickness of the gate in a 3D vertical stack structure and thus determined by the process integration. Figures 12(a)–12(c) show the simulated I_d–V_g curves with D = 24 nm, 16 nm, and 8 nm, with varying R_IGZO, respectively. The narrower FeFETs show lower on-current due to the smaller effective channel width. Figures 13(a) and 13(b) summarize the extracted MWs versus R_IGZO and t_IGZO, with varying D, respectively. At R_IGZO = 0.5, which is the case of the NW FeFETs, the MW largely increases as D decreases. This is the same result in Fig. 10 attributed to the 3D electric field concentration. In addition, as R_IGZO decreases, the MW monotonically increases. This is mainly due to the voltage divider between the HZO layer and the IGZO-channel layer. As t_IGZO decreases, more voltage drops on the HZO layer. For D = 8 nm, the R_IGZO dependence is relatively weak because the 3D electric field concentration with small D is more dominant than the voltage divider with a thin IGZO layer. These trends are more clearly seen in Fig. 13(b). In the MAC FeFETs, the MWs follow almost the same trend as a function of t_IGZO even with different D values because of the voltage divider between the HZO layer and the IGZO channel. The NW FeFETs deviate from this universal trend because of the 3D electric field concentration effect, which depends on D.

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

From the device design point of view, once the diameter of the deep trench in a 3D FeFET is decided from the density and layout requirement, then D, which is the total diameter including the IGZO channel and the filler, is determined at the given HZO thickness. Next, the IGZO thickness is chosen for the target MW. An extremely thin IGZO thickness may be required in the regime of MAC FeFETs. If the IGZO thickness is too thin to conformally deposit inside a deep trench of a high aspect ratio and filler deposition is technically difficult, making NW FeFETs by entirely filling the trench with IGZO is a feasible approach. NW FeFETs can facilitate the process integration and boost the MW by the 3D electric field concentration.

We simulated the memory characteristics of IGZO-channel FeFETs with 2D planar and 3D structures by TCAD simulation to study MW improvement with a floating-body channel for high-density memory applications. From the study on 2D planar devices with SG and DG structures, the MW depends on L and is enhanced with shorter L, which is due to strong electrostatic coupling from the source and drain to the center region of the IGZO layer. From the study on the 3D structure FeFETs with MAC and NW structures, a large MW can be obtained especially in the NW structure due to the electric field concentration by the 3D electrostatics. MAC FeFETs and NW FeFETs were simulated by systematically varying the parameters of D, R_IGZO and t_IGZO. The MW can be improved by the 3D electric field concentration in a narrow outer diameter of the IGZO layer and a voltage divider with a thin IGZO-channel layer. These findings are useful for designing 3D vertical FeFETs for high-density memory applications.

This work was supported by JST CREST (16815651), JSPS KAKENHI Grant No. JP18H01489, and Tokyo Electron Ltd. and TSMC Advanced Semiconductor Research Project.