Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration

We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

I n 2011, the single-layer MoS 2 FET with exfoliation method was first reported with excellent channel charge modulation, high on/off-ratio and mobility of approximately 200 cm 2 V −1 s −1 , despite an extremely small thickness of 0.65 nm. 1) The high mobility of MoS 2 film is attributed to its layered structure and no dangling bond in the out-of-plane direction. The MoS 2 film has flexibility and transparency as well. 2,3) Therefore, transition-metal di-chalcogenides such as MoS 2 have been attracting attention as channel materials for advanced field-effect transistor (FET), internet-of-things (IoT) and wearable devices. 4) Considering on applications, the MoS 2 films have been widely formed by thermal chemical vapor deposition (CVD) and metal-organic CVD (MOCVD). 5,6) However, to synthesize large MoS 2 film, a special treatment with alkali metal such as perylene-3,4,9,10 tetracarboxylic acid tetrapotassium salt is necessary, and it influences in the Fermi level. [7][8][9][10][11] In contrast in the MOCVD, contamination derived from organic precursors is a concern. 4,12) Therefore, we selected radio-frequency (RF) magnetron sputtering to synthesize a large and uniform MoS 2 thin film, reducing contaminations because of the high vacuum process. [13][14][15] Previously, we demonstrated chiplevel integrated MoS 2 nMISFETs using H 2 S annealing and the double layer aluminum oxide (Al 2 O 3 ) passivating procedure for sulfur compensation and prolong process endurance of sputtered-MoS 2 film. However, the normally-on operation remains to be solved. 15) This is due to the fixed charge (Q f ), interface trap densities (Q it ) of double layer Al 2 O 3 and high carrier densities in MoS 2 film annealed in H 2 S ambient at 400°C. 15) In this study, to reduce Q f and Q it , a single-Al 2 O 3 dielectric layer and forming gas (F.G.) annealing were introduced. Moreover, the sulfur powder annealing (SPA) at 700°C. 16) was newly applied to reduce carrier density. We integrated the sputtered-MoS 2 nMISFET with all these techniques to achieve normally-off operation in accumulation mode.
In the experiments, Fig. 1(a) shows the process flow of chip-level integrated nMISFETs. 17) As the S/D regions for ntype operation, the n-doped poly-Si contact was patterned via optical lithography and chemical dry etching in CF 4 ambient. To remove the photo resist, piranha cleaning at 120°C for 10 min was performed. A Mo film was deposited by sputtering at room temperature and a MoSi 2 film was formed at 700°C in argon (Ar) gas. [17][18][19][20] Just after the piranha cleaning to remove the residual Mo film, 21) a 2.7 nm thick MoS 2 film was directly deposited on the SiO 2 substrate via RF magnetron sputtering at 400°C with RF power of 50 W, distance of 230 mm between the target and substrate, Ar flow of 7.0 sccm, and partial pressure of 0.75 Pa. 13,22) The MoS 2 film was annealed via SPA at 700°C under 100 Pa for 1 h to compensate for the sulfur vacancies and suppress the carrier density. 15) As a dielectric layer, a single Al 2 O 3 film was deposited on the MoS 2 film by atomic layer deposition (ALD) method at 300°C. After the isolation of the MoS 2 channel region via optical lithography and reactive ion etching (RIE) using Cl 2 ambient, a 50 nm thick SiN film was deposited on the patterned photo resist via sputtering. After lift-off process, a residual SiN sidewall encapsulated the MoS 2 channel with Al 2 O 3 film to prolong its endurance. A 150 nm thick titanium nitride (TiN) top-gate electrode was deposited through sputtering, and etched via optical lithography and RIE using Cl 2 ambient. Therefore, the single Al 2 O 3 gate-dielectric with SiN sidewall is realized to reduce Q f values. S/D contact holes through the Al 2 O 3 film were opened using diluted hydrogen fluoride, and contact metals with Ti of 20 nm and TiN of 30 nm were formed by sputtering and the lift-off process. Finally, the F.G. annealing was performed on the sputtered MoS 2 channel at 300°C for 30 min to reduce the Q f and Q it values, as shown in Fig. 1 (b). 23,24) As results and discussion, a test elementary group (TEG) on a chip of 2.5 × 2.5 cm 2 area was successfully fabricated, as depicted in plane scanning electron microscope (SEM) images in Fig. 1(c). 17) The cross-sectional transmission electron microscope (TEM) images in Fig. 2 exhibits the final gate-stack structure with the sulfurized MoS 2 channel, single ALD-Al 2 O 3 gate-dielectric, and TiN top-gate electrode. From Fig. 2(a), it is confirmed that the MoS 2 film with uniform thickness through 200 nm wide was preserved, and also that the single Al 2 O 3 film with approximately 16.4 nm thick was uniformly formed. A four-layer MoS 2 film with approximately 2.7 nm thick is successfully observed in Fig. 2 (b). 17) Therefore, the thickness per layer is approximately 0.7 nm, which matches the reported thickness. 1) In Fig. 3(a), the log(I d , I s , I g )-V gs characteristics at V ds = 1-5 V are depicted with only SPA, only F.G. anneal, and SPA & F.G. anneals having a drawn channel length (L ch ) and width (W mask ) of 10 and 160 μm, respectively. 17) When only F.G. annealing is performed, the field effect is not observed because the sputtered MoS 2 film has sulfur vacancies, seriously. In contrast, when only SPA to compensate the sulfur vacancies is performed, the field effect is observed, however the off voltage (V off ) seems to be negative. Here, V off is the voltage at the minimum current defined by off current (I off ). When both SPA and F.G. annealing processes were performed, a normally-off n-type operation in accumulation mode was successfully realized. This is considered to be because of the simultaneous suppression of Q f and Q it values with sulfur compensation. 15) The minimum subthreshold slope (SS), the maximum on/off ratio and drain-induced barrier lowering (DIBL) are approximately 800 mV dec -1 ., 100 and 190 mV V −1 respectively, which mean that the performance of our FETs is required to be improved. The I d -V ds characteristics at V gs = 0-4 V with SPA & F.G. anneals are shown in Fig. 3(b). 17) The field effect and following pinch-off are remarkably observed, however the Schottky-type junction is still observed at small values of V ds . In addition, a negative differential conductance in Fig. 3(b) is observed due to the presence of parallel transistors which have different parasitic resistance. Furthermore, the on/off ratio in Fig. 3(a) is as small as approximately 10 2 , which is still due to remaining parasitic resistance.
To extract the external parasitic resistance (R ext ) and the effective channel length (L eff ), the resistance dependence on the L ch value is depicted in Fig. 4. 17) From the bunch of nMISFETs in the TEG, 2ΔL and R ext values were respectively extracted as -1.20 μm and 2.95 × 10 10 Ω μm, and also L eff is calculated as follows: 2ΔL is attributed to the difference between the drawn and electrical channel lengths. The R ext value is higher than that of the CVD-MoS 2 FET with back-gate electrode. 25) Therefore, it is necessary to further suppress the parasitic resistance such as the contact resistance between the MoS 2 and MoSi 2 films.
To confirm whether L eff precisely expresses the electrical channel length, normalized g m characteristics by the L eff , W mask of 160 μm, and overlap of 10 μm are shown in Fig. 5. From this figure, variation in g m values among the three L eff values are small, suggesting that the fabrication and measurements were successfully accomplished in a stable manner.   However, the g m value itself is small, and also the peak value of the field effect mobility with SPA & F.G. anneals is evaluated as 0.12 cm 2 V −1 s −1 through deducting R ext , L eff and V th values calculated as approximately 1.0 V using the g m _ max method. 26) The equivalent SiO 2 thickness of the Al 2 O 3 film was calculated as 10 nm with the relative dielectric constant of Al 2 O 3 film on the MoS 2 channel as 5.8. 27) Therefore, to enhance g m and mobility values with normallyoff operation, the grain size of the sputtered MoS 2 film needs to be enlarged to suppress the carrier scattering in such atomically thin channel by controlling the number of nucleation sites, 28,29) as compared to the CVD method. 4,7) In addition, the enlargement of grain size is expected to improve SS, on/off ratio and DIBL, because a small grain size having each small channel length and many grain boundaries deteriorates the quality of channel and interface between Al 2 O 3 and MoS 2 films. 28,29) Figure 6 is the benchmarks of I off and V off with MoS 2 FETs. 8,9,[30][31][32][33][34][35][36][37][38][39][40][41] As shown in this figure, this study shows the     largest V off of approximately 1.0 V and comparably low I off value of 10 −6 -10 −7 μA μm −1 . Here, I off is the current when the channel resistance is relatively higher than the parasitic resistance. Therefore, it is indicated that our nMISFETs have the low standby power similar to other MoS 2 FETs.
In conclusion, we successfully realized top-gate sputtered MoS 2 nMISFETs integrated on a chip, which exhibited normally-off operation and the highest V off value in accumulation mode. This is attributed to the reduction of Q f , Q it , and carrier density values by a bunch of process-integration improvements. Although the mobility of 0.12 cm 2 V −1 s −1 was still low, our I off value was comparable with previous reports elsewhere. Therefore, this chip-scale 2D device integration scheme helps for future applications such as the IoT and wearable electronics with low energy consumption.