Improvement of Hf-based metal/oxide/nitride/oxide/Si nonvolatile memory characteristics by Si surface atomically flattening

Metal–oxide–nitride–oxide–silicon (MONOS) type nonvolatile memory (NVM) is a promising candidate to replace the conventional floating-gate type NVM in terms of the scaling and high-density integration.¹⁾ One of the issues of conventional MONOS type NVM is the high operation voltage such as 20 V because the thinning of ONO layers has been limited for the ONO layers which consist from SiO₂ blocking layer (BL)/SiN charge trapping layer (CTL)/SiO₂ tunneling layer (TL). Therefore, the replacement of each layer to high-k thin film has been investigated to decrease the equivalent oxide thickness of ONO layers for the operation voltage reduction especially for the BL and CTL.^2–6) Generally, each layer is deposited by a different method such as thermal oxidation for SiO₂ TL, chemical vapor deposition for SiN CTL, and sputtering for high-k BL. This process would degrade the interface properties during the transfer of the sample to another chamber.

The HfO₂ thin film with the relative dielectric constant (ε_r) of 20 has been introduced to the metal–oxide-field-effect transistor (MOSFET) as a high-k gate insulator since the 45 nm technology node.⁷⁾ The HfN_x (x > 1) thin film has also been investigated for high-k gate insulator application, and the ε_r of 26 has been achieved for the HfN_1.3/HfN_1.1/Si(100) bilayer structures.^8–11) We have reported the excellent electrical characteristics of fully in situ formed Hf-based MONOS NVM, which consists from HfN_0.5 gate electrode/HfO₂ BL/HfN_1.1 CTL/HfO₂ TL/Si(100).^12–14) The Hf-based MONOS layers were deposited by the electron cyclotron resonance (ECR) plasma sputtering in a chamber with changing the process gas for the deposition of each layer. The relative dielectric constants of HfO₂ and HfN are several times higher than those of SiO₂ and SiN such as 3.9 and 7, respectively, which would realize the high speed and low voltage operation. The HfO₂ TL is effective in improving the efficiency of electron injection and emission compared to the SiO₂ TL because of its small barrier height to Si. However, the HfO₂ TL becomes as thin as a few nanometers, further improvement of MONOS memory characteristics has been getting difficult.

In order to improve the Hf-based MONOS memory characteristics, Si surface flattening is important as well as the gate insulator of MOSFET^15–23) because of the thinning of HfO₂ TL and HfN_1.1 CTL. We have reported the Si surface atomically flattening (SAF) process for the Si(100) surface by annealing in Ar/H₂ ambient.^24–32) It has been revealed that the electrical characteristics of Hf-based MONOS diodes was improved by Si SAF as well as the MOSFETs with Hf-based high-k gate insulator.^28–32)

In this study, the effect of Si SAF on the Hf-based MONOS NVM was investigated.³³⁾ Furthermore, the charge centroid in the HfN_1.1 CTL was extracted.³³⁾ The precise device analysis was carried out for the Hf-based MONOS NVM.

Figure 1 shows the experimental procedure for the fabrication of Hf-based MONOS NVM and diode. The in situ formed Hf-based MONOS NVM was fabricated on p-Si(100) substrate using the typical gate-last process.¹⁴⁾ After the channel stop ion implantation and local oxidation of silicon (LOCOS) isolation, Si(100) SAF process by annealing at 1050 °C/60 min in Ar/4%H₂ ambient was carried out. Then, the HfN_0.5/HfO₂/HfN_1.1/HfO₂ (MONO) structure was in situ deposited on p-Si(100) by the ECR plasma sputtering (AFTEX 3400) at room temperature (RT). The designed thickness of HfO₂ TL was 3.2 nm. A 2.1 nm TL was also investigated for the comparison. The HfN_1.1 CTL thickness was 2.3 nm. The thickness of HfO₂ BL and HfN_0.5 gate electrode was 8 nm each. The Ar/O₂ flow rate for HfO₂ TL and BL was 23/4.6 sccm, while the Ar/N₂ flow rates for HfN_1.1 CTL and HfN_0.5 gate electrode were 8/6 sccm and 10/0.2 sccm, respectively. Then, the post-deposition annealing (PDA) was carried out at 600 °C/1 min in N₂. After the contact hole formation and metallization, the post-metallization annealing (PMA) was carried out at 300 °C/10 min in N₂/4.9%H₂. The gate length (L) and width (W) of the fabricated device was L/W = 10/90 μm. The inset of Fig. 1 shows the plane-view of the fabricated Hf-based MONOS diode and NVM.

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The fabricated Hf-based MONOS diodes and NVMs were evaluated by C–V, density of interface states (D_it), I_D–V_D, and I_D–V_G at RT using LCR meter (HEWLETT PACKARD 4284A) and semiconductor parameter analyzer (Agilent 4156C). The operation conditions were set as the program voltage/time (V_PGM/t_PGM) of 10 V/1 s, the erase voltage/time (V_ERS/t_ERS) of −10 V/1 s, and V_DS of 1.5 V. The charge centroid (Z_eff) was extracted utilizing the following equation

$$\begin{eqnarray}&&{Z}_{{\rm{e}}{\rm{f}}{\rm{f}}}=\displaystyle \frac{{\varepsilon }_{{\rm{O}}{\rm{X}}}{\rm{\Delta }}{V}_{{\rm{F}}{\rm{B}}}}{\displaystyle {\int }_{-{V}_{{\rm{F}}{\rm{B}}}}^{0}C\left(V\right)dV+{Q}_{m}},\end{eqnarray} \tag{ 1 }$$

where Q_m is the measured charge, ε_ox is the dielectric constant of HfO₂ BL, and V_FB is the flat-band voltage.³⁴⁾ Figure 2 shows the schematic measurement system for Z_eff evaluation. The input pulse was applied by pulse generator (HEWLETT PACKARD 8110A), and the pulse was observed by the oscilloscope (LeCroy LC534AM). The charge was measured by the electrometer (KEITHLEY 6517A). The pulse input, charge and C–V measurements were controlled by the switch (KEYSIGHT DAQ970A). All measurements were carried out at RT.

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3.1. Effect of Si SAF on the Hf-based MONOS diode characteristics

Figure 3 shows the effect of Si SAF on the C–V measured at 1 MHz and memory window (MW) for Hf-based MONOS diodes extracted from the difference of flat-band voltage (V_FB) after the program and erase (P/E) operation at +10 V/1 s and −10 V/1 s, respectively. From Fig. 3(a), it was found that the charge-injection type hysteresis width was decreased from 40 to 10 mV by the Si SAF for the Hf-based MONOS diodes with the 3.2 nm thick HfO₂ TL. This improvement of interface property was also confirmed by the reduction of D_it from 5.7 × 10¹⁰ to 3.5 × 10¹⁰ cm⁻² eV⁻¹ by the Si SAF as we have reported.¹³⁾ The ideal V_FB for HfN_0.5 gate electrode and p-Si(100) was −0.2 V so that the V_FB shit was decreased from −1.1 to −0.9 V by the Si SAF. This is probably due to the reduction of fixed-oxide charge in the HfO₂ TL with improving the film quality by the Si SAF. The positive fixed charge is induced by the SiO_x (x < 2.0) formation at the interface of HfO₂ and Si substrate. The rough Si surface would form the thicker SiO_x layer, and it would be suppressed by the Si SAF. Figure 3(b) shows the effect of Si SAF on the MW for the Hf-based MONOS diode as a function of the thickness of HfO₂ TL. As shown in Fig. 3(b), the MW obtained by the P/E operation was increased from 4.5 to 4.8 V by the Si SAF when the HfO₂ TL thickness was 3.2 nm. It was getting more effective for the thinner HfO₂ TL such as 2.1 nm. The MW was increased from 1.5 to 2.5 V in case of the Hf-based MONOS diodes with 2.1 nm thick HfO₂ TL. This is because the interface roughness induced the degradation of the retention for the trapped charge with decreasing the HfO₂ TL thickness.

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Figure 4 shows the extracted Z_eff for the Hf-based MONOS diodes with 2.3 nm thick HfN_1.1 CTL and 3.2 nm HfO₂ TL utilizing Eq. (1).³⁴⁾ The ε_r of HfO₂, ε_HfO2, was assumed as 20. The distance of Z_eff from HfO₂ BL/HfN_1.1 CTL interface was extracted as 1.3 nm, which is approximately at the center of HfN_1.1 CTL, for the Hf-based MONOS diode without Si SAF. Interestingly, it was found that the Z_eff was located at the interface region of HfO₂ BL/HfN_1.1 CTL for the Hf-based MONOS diode with Si SAF. The Si SAF would improve the uniformity of HfO₂ TL and HfN_1.1 CTL which led to improve the stability of trapped charge in the HfN_1.1 CTL and decrease the probability of detrapping of the electrons in the HfN_1.1 CTL through the HfO₂ TL.

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3.2. Improvement of Hf-based MONOS NVM characteristics by Si SAF

Next, we have investigated the effect of Si SAF on the device characteristics of Hf-based MONOS NVM with 2.3 nm thick HfN_1.1 CTL and 3.2 nm HfO₂ TL. Figure 5 shows the I_D–V_D characteristics for the fabricated Hf-based MONOS NVM at fresh state. The threshold voltage (V_TH) was extracted from the I_D–V_G characteristics as shown in Fig. 6, and the MW was defined as the V_TH difference of program and erase states. As shown in Fig. 5, the good saturation characteristics were observed for the I_D–V_D characteristics under the V_G–V_TH of 2 V operation for Hf-based MONOS NVM both with and without (w/o) Si SAF. This result suggested that the device fabrication process was successfully carried out especially for the S/D contact hole formation and gate patterning for the Hf-based MONOS stacked structures. The current drivability was found to be improved by Si SAF with the linear mobility of 150 cm² V⁻¹ s⁻¹.

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Figure 6 shows the effect of Si SAF on the I_D–V_G characteristics of Hf-based MONOS NVM utilizing P/E pulses of ±10 V/1 s. The read operation condition was set as V_D = 1.5 V and V_S = 0 V, respectively. The V_TH was defined as the voltage when the I_D became 10⁻² A μm⁻¹ in this research. The extracted V_TH results were indicated by an arrow in each graph. The obtained I_D–V_G characteristics showed negligible hysteresis both for the devices with and w/o Si SAF. As shown in Fig. 6(a), the initial V_TH was −0.9 V, while it shifted to 1.7 V after the program operation. The V_TH of 0.6 V was obtained after the erase operation. Although the erase operation was not completed by this condition, the MW of 1.1 V was obtained for the Hf-based MONOS NVM w/o Si SAF.

The device characteristics were markedly improved by the Si SAF as shown in Fig. 6(b). The initial V_TH was −0.4 V, while it shifted to 3.3 V after the program operation. Interestingly, the erase operation was significantly improved by the Si SAF, and the V_TH shifted to 0.1 V which was close to the initial state. The MW of 3.2 V was obtained for the Hf-based MONOS NVM with Si SAF. Furthermore, the extracted ON/OFF ratio form the fresh characteristics was increased from 6.5 × 10⁷ to 2.9 × 10⁸, and subthreshold swing was reduced from 106 to 101 mV dec⁻¹ with decreasing the off current by the Si SAF. The Si SAF improves the uniformity of HfO₂ TL and HfN_1.1 CTL which led to the decrease of off leakage current. Furthermore, we speculated that the deep trap level was formed in the HfN_1.1 CTL in case of the Hf-based MONOS NVM w/o Si SAF which caused the incomplete erase operation. The deep trap formation would be suppressed by the Si SAF with improving the film quality of HfN_1.1 CTL so that the erase operation was successfully carried out. Therefore, the Si SAF improved not only the quality of each layer but the property of each interface, and it is promising for precise control of the V_TH to realize the multi-bit NVM with reducing the operation voltage. We have reported that the improvement of memory characteristics such as retention and endurance by the Si SAF for the Hf-based MONOS diodes.¹³⁾ The retention and endurance characteristics for the Hf-based MONOS transistors would be discussed in another paper.

The effect of Si SAF on the Hf-based MONOS characteristics was investigated. The MW of 4.8 V was obtained, and Z_eff was found to be located at BL/CTL interface for the Hf-based MONOS diode with the Si SAF. Furthermore, the MW of 3.2 V was realized for the Hf-based MONOS NVM with improvement of the device characteristics by the Si SAF. In conclusion, the Si SAF is effective to improve the Hf-based MONOS NVM characteristics for high speed and low voltage operation.

The authors would like to thank Mr. M. Suzuki of Tokyo Institute of Technology, the late Prof. Emeritus T. Ohmi, Prof. T. Goto, and Prof. T. Suwa of Tohoku University, Dr. M. Shimada and Mr. M. Hirohara of JSW-AFTY for their support and useful discussions for this research. This research was partially supported by JSPS KAKENHI Grant Nos. 19H00758, JP17J10752 and Toshiba Electronic Devices & Storage Corporation.