X-band MMICs for a Low-Cost Radar Transmit/Receive Module in 250 nm GaN HEMT Technology

This paper describes Monolithic Microwave Integrated Circuits (MMICs) for an X-band radar transceiver front-end implemented in 0.25 μm GaN High Electron Mobility Transistor (HEMT) technology. Two versions of single pole double throw (SPDT) T/R switches are introduced to realize a fully GaN-based transmit/receive module (TRM), each of which achieves an insertion loss of 1.21 dB and 0.66 dB at 9 GHz, IP1dB higher than 46.3 dBm and 44.7 dBm, respectively. Therefore, it can substitute a lossy circulator and limiter used for a conventional GaAs receiver. A driving amplifier (DA), a high-power amplifier (HPA), and a robust low-noise amplifier (LNA) are also designed and verified for a low-cost X-band transmit-receive module (TRM). For the transmitting path, the implemented DA achieves a saturated output power (Psat) of 38.0 dBm and output 1-dB compression (OP1dB) of 25.84 dBm. The HPA reaches a Psat of 43.0 dBm and power-added efficiency (PAE) of 35.6%. For the receiving path, the fabricated LNA measures a small-signal gain of 34.9 dB and a noise figure of 2.56 dB, and it can endure higher than 38 dBm input power in the measurement. The presented GaN MMICs can be useful in implementing a cost-effective TRM for Active Electronically Scanned Array (AESA) radar systems at X-band.


Introduction
The recent remarkable development of solid-state semiconductors has enabled a highresolution remote sensor to be implemented. In particular, the transition from classical magnetron radar to solid-state semiconductor radar made the coherence characteristics available and various signal processing techniques possible. This method can realize technologies such as Doppler processing, pulse compression, and beamforming used in modern radars. Particularly, an Active Electronically Scanned Array (AESA) radar utilizing beamforming technology enables accurate ranging and detection by adjusting the direction of the shared antenna beam through electrical control of phase and size. AESA radars have recently been widely used in various sectors of military aviation, surveillance, and civil applications. AESA radar systems rely heavily on the performance of the Transmit (Tx)/Receive (Rx) module (TRM) for each antenna element since it is a crucial module in determining the SNR of reflected signals and its cost. Thousands of TRMs are integrated depending on the applications [1]. Hence, it is essential to implement a compact and cost-effective TRM for a competitive AESA radar system for various applications.  Traditionally, TRM front-end blocks have been implemented with GaAs technologies considering the superb device performance at microwave and millimeter-wave regimes. Recently, research on GaN technologies has been widely conducted across the semiconductor sectors, including research on efficient full-spectrum WLEDs utilizing bandgap engineering [2] and GaN radiation hardness for space-applied electronics [3]. In particular, research on GaN-based RF front-end mainly relies on the large bandgap characteristics. By replacing TRM front-end blocks with GaN technology, it is possible to implement a low-cost and compact TRM by eliminating a bulky ferrite circulator and external limiters in front of the GaAs LNA. The high breakdown voltage of the GaN High Electron Mobility Transistor (HEMT) enables a high voltage swing of the HPA with a higher supply voltage, resulting in a higher power density than GaAs HEMTs [4]. This enables the use of smaller device sizes and less complex output matching networks, which may result in more compact and more power-efficient blocks in the GaN technology than GaAs counterparts.
The design of RF circuits utilizing GaN HEMT devices with excellent characteristics requires accurate GaN HEMT device modeling studies. Early empirical models were proposed by Angelov et al. [5] and Sadi et al. [6]. Later, based on the device physics of the model, the ASM-HEMT model [7], MVSG HEMT model [8], and EPFL HEMT model were proposed for improved GaN HEMT modeling [9]. During the last decade, GaN HEMT device modeling studies have enabled foundries to provide commercially viable GaN HEMT design services, such as modeling the NQS effect [10], improving HEMT models at cryogenic temperatures [11], and modeling the charge trapping effect [12] to improve the modeling of nonlinear characteristics of HEMT devices.
For the LNA in the Rx path of a conventional TRM, GaAs HEMT has been widely employed due to its high transconductance and superior noise performance. However, considering feasible high input power interferences, external limiters are necessary to protect the GaAs HEMT at the first stage of the LNA, which compromises the noise performance and increases the manufacturing cost. Moreover, a conventional Rx implemented with GaAs MMICs requires the use of bulky ferrite circulators to isolate the Tx and Rx paths.
The high-power handling capability of the GaN HEMT allows a SPDT switch to operate as a compact Tx/Rx duplexer. Since the SPDT switch is located at the input port of the antenna element, its performance significantly affects on the overall TRM block. In order to achieve the required SNR of the entire Rx path, it is essential to minimize the insertion loss (ILSPDT) of the SPDT switch as it degrades the SNR by twice the ILSPDT. By substituting a bulky ferrite circulator and the input limiter blocks with a compact GaN Traditionally, TRM front-end blocks have been implemented with GaAs technologies considering the superb device performance at microwave and millimeter-wave regimes. Recently, research on GaN technologies has been widely conducted across the semiconductor sectors, including research on efficient full-spectrum WLEDs utilizing bandgap engineering [2] and GaN radiation hardness for space-applied electronics [3]. In particular, research on GaN-based RF front-end mainly relies on the large bandgap characteristics. By replacing TRM front-end blocks with GaN technology, it is possible to implement a low-cost and compact TRM by eliminating a bulky ferrite circulator and external limiters in front of the GaAs LNA. The high breakdown voltage of the GaN High Electron Mobility Transistor (HEMT) enables a high voltage swing of the HPA with a higher supply voltage, resulting in a higher power density than GaAs HEMTs [4]. This enables the use of smaller device sizes and less complex output matching networks, which may result in more compact and more power-efficient blocks in the GaN technology than GaAs counterparts.
The design of RF circuits utilizing GaN HEMT devices with excellent characteristics requires accurate GaN HEMT device modeling studies. Early empirical models were proposed by Angelov et al. [5] and Sadi et al. [6]. Later, based on the device physics of the model, the ASM-HEMT model [7], MVSG HEMT model [8], and EPFL HEMT model were proposed for improved GaN HEMT modeling [9]. During the last decade, GaN HEMT device modeling studies have enabled foundries to provide commercially viable GaN HEMT design services, such as modeling the NQS effect [10], improving HEMT models at cryogenic temperatures [11], and modeling the charge trapping effect [12] to improve the modeling of nonlinear characteristics of HEMT devices.
For the LNA in the Rx path of a conventional TRM, GaAs HEMT has been widely employed due to its high transconductance and superior noise performance. However, considering feasible high input power interferences, external limiters are necessary to protect the GaAs HEMT at the first stage of the LNA, which compromises the noise performance and increases the manufacturing cost. Moreover, a conventional Rx implemented with GaAs MMICs requires the use of bulky ferrite circulators to isolate the Tx and Rx paths.
The high-power handling capability of the GaN HEMT allows a SPDT switch to operate as a compact Tx/Rx duplexer. Since the SPDT switch is located at the input port of the antenna element, its performance significantly affects on the overall TRM block. In order to achieve the required SNR of the entire Rx path, it is essential to minimize the insertion loss (IL SPDT ) of the SPDT switch as it degrades the SNR by twice the IL SPDT . By substituting a bulky ferrite circulator and the input limiter blocks with a compact GaN T/R switch, the performance of the GaN Rx chain can be comparable with the GaAs Rx chain with a lower manufacturing cost and more compact module size.
In this paper, core MMIC blocks for a cost-effective TRM aiming at the X-band AESA radar system are presented. All the core blocks such as the low insertion loss SPDT switch, and low-noise LNA for Rx chain, DA, and HPA were implemented in 250 nm GaN on the SiC HEMT process. For SPDTs, the impact of the presence or absence of a compensation inductor on the overall value of insertion loss and bandwidth is discussed. The HPA design introduces a pulse-induced test to avoid stability issues. In the design of LNA, it is demonstrated that utilizing a high gate resistor and a drain current limiter ensures high  A comparison table is provided to compare the performance of each block with  other recently reported GaN-based works in the X-band, which demonstrate the feasibility of the fully GaN-based TRM.

X-band Transceiver Front-End Design
In this work, all the GaN MMICs were realized in 0.25 µm GaN/SiC HEMT power device technology. The GaN heterostructure is grown on a 100 µm SiC substrate by plasmaenhanced chemical vapor deposition (PECVD). In this process, two metal layers can be routed: MET1 of 1.1 µm thickness, and MET2 of 4 µm thickness, which can be connected using a via-layer of 0.27 µm thickness. The cut-off frequency f T and the maximum frequency of oscillation f max are 25 GHz and 82 GHz, respectively.

SPDT Switch as Duplexer
Working as a duplexer, the GaN SPDT switch is placed right after each antenna element and connects both the receive and transmit paths. Thus, it requires an extremely low insertion loss and high isolation between Tx and Rx ports. Exhibiting a low insertion loss may improve the overall SNR of the implemented TRM, and the high isolation minimizes high power signal leakage from the Tx to Rx path in transmit mode that can permanently damage the gate diode of a LNA. Figure 2 presents two types of FET switches, which are series switches and parallel switches, and both are used to construct a conventional single pole double throw (SPDT). Each switch in the SPDT turns on and off inversely depending on the gate control voltage (V H = 0 V, V L = −26 V). Notably, the on-state power is limited by the maximum channel current (I MAX ) of the series switch of which the typical value at V GS = 0 V is about 1 A/mm. Thus, the maximum available power through the series HEMT is approximately 25 W for a HEMT with a gate width of 1 mm. Thus, it can be a threat of using a SPDT switch as a duplexer for high-power applications (typically 25 W for recent designs). Moreover, the series HEMT switch induces a relatively large insertion loss since it is in the main path of signal conduction. It is noted that the maximum power of the off-state switch should consider the breakdown voltage (V BD ), the gate control voltage (V ctrl ), and the pinch-off voltage (V p ). To maximize the voltage swing, V ctrl is selected to be centered between V BD and V p [13]. Owing to the high band gap property of GaN, the breakdown voltage (V BD ) is 120 V under a drain current density of 1 mA/mm in this GaN process. With a −2.6 V pinchoff voltage, an off-state power can be handled up to a hundred watts. Since the reliability of the parallel switch is mainly dependent on the off-state power handling rather than on-state power handling, the SPDT can achieve a low insertion loss with high output handling capability when only parallel HEMT switches are used with λ/4 transmission-lines (T-lines) for the isolation.  In this work, we implemented two types of SPDT T/R switches. The first T/R (SW-A) employs shunt inductors to compensate parasitic capacitance of shunt tran  In this work, we implemented two types of SPDT T/R switches. The first T/R switch (SW-A) employs shunt inductors to compensate parasitic capacitance of shunt transistors to improve isolation and bandwidth. The second T/R switch (SW-B) is more focused on the low insertion-loss, which excludes the shunt inductors. SW-A is advantageous in achieving a wider bandwidth with improved isolation owing to the resonant inductors. However, the additional lossy inductors degrade the overall insertion loss of the switch. Figure 3 depicts the layout and the schematic of SPDT T/R switch version-A (SW-A). The designed T/R switch occupies a chip size of 5.7 mm × 1.5 mm. The proposed T/R switch has a symmetric structure, and each arm consists of four parallel HEMTs with transmission lines without any series HEMT switches. The simulations have been conducted in Keysight ADS, and all the routing lines in the design were optimized with the Momentum EM simulator in ADS. The size of all shunt transistors is optimized to achieve the minimum insertion loss while providing good isolation and linearity. When the Tx path is turned on, that means M 1-4 should be turned on to make a short circuit, which is consequently seen as open by the λ/4 transmission line, TL 1 . Thus, M 1-8 need to be large enough to minimize the on-state resistance. Considering these aspects, the width of M 1-8 is 9 × 100 µm. In this work, we implemented two types of SPDT T/R switches. The first T/R switch (SW-A) employs shunt inductors to compensate parasitic capacitance of shunt transistors to improve isolation and bandwidth. The second T/R switch (SW-B) is more focused on the low insertion-loss, which excludes the shunt inductors. SW-A is advantageous in achieving a wider bandwidth with improved isolation owing to the resonant inductors. However, the additional lossy inductors degrade the overall insertion loss of the switch. Figure 3 depicts the layout and the schematic of SPDT T/R switch version-A (SW-A). The designed T/R switch occupies a chip size of 5.7 mm × 1.5 mm. The proposed T/R switch has a symmetric structure, and each arm consists of four parallel HEMTs with transmission lines without any series HEMT switches. The simulations have been conducted in Keysight ADS, and all the routing lines in the design were optimized with the Momentum EM simulator in ADS. The size of all shunt transistors is optimized to achieve the minimum insertion loss while providing good isolation and linearity. When the Tx path is turned on, that means M1-4 should be turned on to make a short circuit, which is consequently seen as open by the /4 transmission line, TL1. Thus, M1-8 need to be large enough to minimize the on-state resistance. Considering these aspects, the width of M1-8 is 9 × 100 μm.  Since all the active devices are depletion HEMT, applying 0 V control voltage is enough to keep the transistor at the on-state and can also provide low resistance for short circuits. When the Tx path is turned off, an inserted shunt inductors resonate with the parasitic capacitance of the off-state transistors, which decreases the loading of the shunt transistor remarkably. Since this design should be integrated with other blocks (e.g., LNA, PA) to construct a TRM utilizing 26 V for the HPA and DA, Vctrl = −26 V is chosen. It is noteworthy that the used T-lines need to be wide enough to carry the input power level as expected from the output of HPA. The characteristic impedance is calculated and tuned deliberately with the Momentum EM simulation in ADS. In previous works, several k- Since all the active devices are depletion HEMT, applying 0 V control voltage is enough to keep the transistor at the on-state and can also provide low resistance for short circuits. When the Tx path is turned off, an inserted shunt inductors resonate with the parasitic capacitance of the off-state transistors, which decreases the loading of the shunt transistor remarkably. Since this design should be integrated with other blocks (e.g., LNA, PA) to construct a TRM utilizing 26 V for the HPA and DA, V ctrl = −26 V is chosen. It is noteworthy that the used T-lines need to be wide enough to carry the input power level as expected from the output of HPA. The characteristic impedance is calculated and tuned deliberately with the Momentum EM simulation in ADS. In previous works, several k-Ohm resistors were used to decouple the switch circuit from the common gate ground [13][14][15][16][17][18][19]. However, the gate leakage current combined with a high-value resistor induces a distinctive change to the effective control voltage, which can result in a huge degradation in the overall performance of the switch, specifically for the on-state HEMT as it can change state from onto off-state. Hence, in our work, a λ/4 T-line with a high characteristic impedance (narrow width) is used at the gate control line for the improved isolation purpose. In addition, a 30 Ω resistor is inserted between the gate and the control line to enhance stability.

23
The chip photo and the schematic of SW-B are presented in Figure 4. Different from SW-A, SW-B removes the parallel inductors to improve the overall insertion loss. The designed SW-B occupies a chip size of 5.3 mm × 2.6 mm. To reduce the parasitic capacitance, the widths of M 1,8 and M 2,3,6,7 are changed to 5 × 100 µm and 7 × 100 µm, respectively. Meanwhile, the width of M 4,5 remained at 9 × 100 µm to guarantee the small channel resistance with a T/R switch off-state. Different from SW-A, a gate resistor R g = 500 Ω was adopted for the isolation purpose, and the degradation due to the voltage drop was not measured as described the Section 3.1. SW-A, SW-B removes the parallel inductors to improve the overall insertion loss. The designed SW-B occupies a chip size of 5.3 mm × 2.6 mm. To reduce the parasitic capacitance, the widths of M1,8 and M2,3,6,7 are changed to 5 × 100 μm and 7 × 100 μm, respectively. Meanwhile, the width of M4,5 remained at 9 × 100 μm to guarantee the small channel resistance with a T/R switch off-state. Different from SW-A, a gate resistor Rg = 500 Ω was adopted for the isolation purpose, and the degradation due to the voltage drop was not measured as described the Section 3.1.

High Power Amplifier
The designed High Power Amplifier (HPA) architecture utilizes a four-way power combining structure at the power stage with a cascaded two-stage configuration. Figure  5a shows the photo of the implemented HPA, which occupies 4.6 mm × 3.7 mm. Figure 5b presents the schematic of the HPA. In this HPA design, individual source via (ISV)-type HEMTs are utilized to minimize the source degeneration from the via to the ground.

High Power Amplifier
The designed High Power Amplifier (HPA) architecture utilizes a four-way power combining structure at the power stage with a cascaded two-stage configuration. Figure 5a shows the photo of the implemented HPA, which occupies 4.6 mm × 3.7 mm. Figure 5b presents the schematic of the HPA. In this HPA design, individual source via (ISV)-type HEMTs are utilized to minimize the source degeneration from the via to the ground.
The HEMT at the first stage (M 1-2 ) and the final stage (M 3-6 ) has a gate periphery ratio of 1:3.2 with a width of 8 × 150 µm and 6 × 125 µm, respectively. A parallel RC network and a gate bias resistor are implemented in each gate of the transistor to enhance stability. Moreover, in-phase RF signals pass through each four path at the final stage. In this condition, an odd-mode oscillation may occur due to the electric asymmetry from the different DC supply paths of each transistor. To suppress feasible odd-mode oscillation, a resistor between transistors, R o = 17 Ω is placed at the final stage. To avoid undesired oscillation from the power supply perturbation, the quality-factor (Q-factor) of the bypass capacitor network was degraded by adding a 10 Ω resistor in series with the bypass capacitor.  Rodd   TL1   TL2   TL3   TL4   TL5   TL6  TL7   TL8   TL9   TL10   TL11   TL12   TL13   TL14   6×125 μm   M1-2  M3-6   TL1  TL2  TL3  TL4  TL5   TL7  TL8  The HEMT at the first stage (M1-2) and the final stage (M3-6) has a gate periphery ratio of 1:3.2 with a width of 8 × 150 μm and 6 × 125 μm, respectively. A parallel RC network and a gate bias resistor are implemented in each gate of the transistor to enhance stability. Moreover, in-phase RF signals pass through each four path at the final stage. In this condition, an odd-mode oscillation may occur due to the electric asymmetry from the different DC supply paths of each transistor. To suppress feasible odd-mode oscillation, a resistor between transistors, Ro = 17 Ω is placed at the final stage. To avoid undesired oscillation from the power supply perturbation, the quality-factor (Q-factor) of the bypass capacitor network was degraded by adding a 10 Ω resistor in series with the bypass capacitor.
Theoretically, Rollet's k-stability analysis can be usefully applied to check the unconditional stability of the two-port network at the small-signal regime. Unfortunately, a realized HPA cannot be properly modeled as a two-port network since it includes multiple biasing ports. Hence, oscillations may not be properly detected only with the k- Theoretically, Rollet's k-stability analysis can be usefully applied to check the unconditional stability of the two-port network at the small-signal regime. Unfortunately, a realized HPA cannot be properly modeled as a two-port network since it includes multiple biasing ports. Hence, oscillations may not be properly detected only with the k-stability test from the small-signal two-port S-parameters. To guarantee the stability of the designed HPA, we applied a pulse-induced stability test in the time domain to check undesirable oscillations from the power supply interferences. As presented in Figure 6, a periodic pulse perturbation was excited from the power supply, and the output voltage was investigated in the time domain. In the designed HPA architecture, the fluctuations were forced to be underdamped with various stabilization networks such as the odd-mode resistors, bypass capacitor networks with a low Q-factor, and parallel RC networks at the gate of each HEMT. The simulation shows that the output voltage was settled quickly under the strong perturbations from the supply. stability test from the small-signal two-port S-parameters. To guarantee the stability of the designed HPA, we applied a pulse-induced stability test in the time domain to check undesirable oscillations from the power supply interferences. As presented in Figure 6, a periodic pulse perturbation was excited from the power supply, and the output voltage was investigated in the time domain. In the designed HPA architecture, the fluctuations were forced to be underdamped with various stabilization networks such as the oddmode resistors, bypass capacitor networks with a low Q-factor, and parallel RC networks at the gate of each HEMT. The simulation shows that the output voltage was settled quickly under the strong perturbations from the supply.  Figure 7a presents the load-pull simulation result plotted in the Smith chart, and the insertion loss of the output combiner is shown in Figure 7b. To suppress undesired outof-band signals, the output-matching network was designed to achieve a bandpass filter property. The input impedance of the output combiner at 9 GHz is 10.8 + j19.43 Ω. The  Figure 7b. To suppress undesired out-of-band signals, the output-matching network was designed to achieve a bandpass filter property. The input impedance of the output combiner at 9 GHz is 10.8 + j19.43 Ω. The combiner loss at 9 GHz is 0.96 dB, which is an acceptable value for the four-way combiner, while the out-of-band suppression of the combiner is distinctive with a sharp skirt characteristic.

Driving Amplifier
A two-stage driving amplifier (DA) with high power gain is used to drive the HPA at the saturation point with optimal peak power added efficiency (PAE). Figure 8 illustrates the chip photo and the schematic of the proposed amplifier. The size of the implemented DA is 4.4 mm × 2.8 mm. Since the designed power amplifier in Section 2.2 necessitates an input power of 32 dBm to achieve the saturation point, the DA should acquire an output power larger than 32 dBm.

Driving Amplifier
A two-stage driving amplifier (DA) with high power gain is used to drive the HPA at the saturation point with optimal peak power added efficiency (PAE). Figure 8 illustrates the chip photo and the schematic of the proposed amplifier. The size of the implemented DA is 4.4 mm × 2.8 mm. Since the designed power amplifier in Section 2.2 necessitates an input power of 32 dBm to achieve the saturation point, the DA should acquire an output power larger than 32 dBm.  The implemented DA was designed with ISV-type HEMTs to minimize the parasitic degeneration inductance from the via to the ground. To achieve a wide range of linear regions, the size of the device at the final stage (M2) was chosen to be 8 × 150 μm, which makes Psat surpass 32 dBm. To keep the liner region from large input power and reduce the gain distortion within the operating power range, the size of the device at the final stage (M1) was selected to be 8 × 75 μm, resulting in the gate periphery ratio of 1:2. The input and output impedance was matched to 50 Ω considering the standalone measurement of each block and feasibility of the different compositions of MMIC blocks. The matching networks were comprised of capacitors and T-lines instead of inductors considering the reduction of the loss and modeling accuracy at the X-band.

OUT
To increase the stability of the DA within the operating band, a parallel RC network The implemented DA was designed with ISV-type HEMTs to minimize the parasitic degeneration inductance from the via to the ground. To achieve a wide range of linear regions, the size of the device at the final stage (M 2 ) was chosen to be 8 × 150 µm, which makes P sat surpass 32 dBm. To keep the liner region from large input power and reduce the gain distortion within the operating power range, the size of the device at the final stage (M 1 ) was selected to be 8 × 75 µm, resulting in the gate periphery ratio of 1:2. The input and output impedance was matched to 50 Ω considering the standalone measurement of each block and feasibility of the different compositions of MMIC blocks. The matching networks were comprised of capacitors and T-lines instead of inductors considering the reduction of the loss and modeling accuracy at the X-band.
To increase the stability of the DA within the operating band, a parallel RC network was placed at the gate of each device. While the RC network enhances stability through overall frequency, the gain suppression was not enough to guarantee unconditional stability at a low-frequency regime. Thus, a series resistor was also placed in the path of the gate bias line of each device for improved stability at a low frequency. The values of resistance and capacitance of the parallel RC network were carefully chosen according to the size of each device while keeping unconditional stability with minimal gain degradation. Figure 9 shows a design example of a stabilization cell with an 8 × 150 µm ISV HEMT. By adding the parallel RC network with 50 Ω and 1.2 pF at the gate and a 50 Ω resistor in the gate bias line, the HEMT cell achieves unconditional stability from 100 MHz to 20 GHz range.

Low Noise Amplifier
The first stage was configured with an inductive source degeneration structure to achieve impedance and noise matching simultaneously. For the second stage, the RCfeedback is removed to improve the gain of the LNA, and the RC-feedback network was used for wideband operation with enhanced stability of the LNA in the last two stages. The optimal device size with a degeneration inductance was chosen to minimize the gain degradation for an improved noise performance of the overall receiver system with enhanced robustness from the high-power interference at the input of the LNA. While the smaller device has a low minimum noise figure (NFmin), the larger device is advantageous for wideband matching. Figure 10 depicts the chip photo and the configuration of the proposed four-stage LNA with common source (CS) devices. In this simulation, a measurement-based noise model from the Foundry was used for the noise matching of the first stage of the LNA. (a)

Low Noise Amplifier
The first stage was configured with an inductive source degeneration structure to achieve impedance and noise matching simultaneously. For the second stage, the RCfeedback is removed to improve the gain of the LNA, and the RC-feedback network was used for wideband operation with enhanced stability of the LNA in the last two stages. The optimal device size with a degeneration inductance was chosen to minimize the gain degradation for an improved noise performance of the overall receiver system with enhanced robustness from the high-power interference at the input of the LNA. While the smaller device has a low minimum noise figure (NF min ), the larger device is advantageous for wideband matching. Figure 10 depicts the chip photo and the configuration of the proposed four-stage LNA with common source (CS) devices. In this simulation, a measurementbased noise model from the Foundry was used for the noise matching of the first stage of the LNA.  The optimum noise impedance (Znopt) of the selected device with 6 × 50 μm gate width is simulated as shown in Figure 11a. As illustrated in Figure 11b through Figure 11d, the degeneration inductance should be carefully selected to guarantee the unconditional stability that was achieved with Ldeg = 175 pH. The optimum noise impedance (Z nopt ) of the selected device with 6 × 50 µm gate width is simulated as shown in Figure 11a. As illustrated in Figure 11b through Figure 11d, the degeneration inductance should be carefully selected to guarantee the unconditional stability that was achieved with L deg = 175 pH.  The optimum noise impedance (Znopt) of the selected device with 6 × 50 µm gate width is simulated as shown in Figure 11a. As illustrated in Figure 11b through Figure 11d, the degeneration inductance should be carefully selected to guarantee the unconditional stability that was achieved with Ldeg = 175 pH.   For a GaAs LNA, the first stage of the LNA can be easily damaged from excessive RF input power, which necessitates a limiter for a robust Rx chain. To implement a GaN LNA without any input protection circuit, the designed LNA introduced a high gate resistor in the path of the gate bias line to reduce the gate leakage current from the high voltage swing at the gate by effectively lowering the gate bias voltage from the voltage drop of the gate resistor from the leakage current [20]. Figure 12 presents the drain-gate voltage of the first stage HEMT with Pin = 38 dBm (100 μs of pulse width and 10% of duty-cycle). The breakdown voltage of the gate-drain junction (VBDG) is 120 V in the PDK. Different from the GaN LNA, a succeeding CMOS multi-function chip (MFC) can be seriously damaged even with 1 W power, which necessitates limiting the output power For a GaAs LNA, the first stage of the LNA can be easily damaged from excessive RF input power, which necessitates a limiter for a robust Rx chain. To implement a GaN LNA without any input protection circuit, the designed LNA introduced a high gate resistor in the path of the gate bias line to reduce the gate leakage current from the high voltage swing at the gate by effectively lowering the gate bias voltage from the voltage drop of the gate resistor from the leakage current [20]. Figure 12 presents the drain-gate voltage of the first stage HEMT with P in = 38 dBm (100 µs of pulse width and 10% of duty-cycle). The breakdown voltage of the gate-drain junction (V BDG ) is 120 V in the PDK.  For a GaAs LNA, the first stage of the LNA can be easily damaged from excessive RF input power, which necessitates a limiter for a robust Rx chain. To implement a GaN LNA without any input protection circuit, the designed LNA introduced a high gate resistor in the path of the gate bias line to reduce the gate leakage current from the high voltage swing at the gate by effectively lowering the gate bias voltage from the voltage drop of the gate resistor from the leakage current [20]. Figure 12 presents the drain-gate voltage of the first stage HEMT with Pin = 38 dBm (100 μs of pulse width and 10% of duty-cycle). The breakdown voltage of the gate-drain junction (VBDG) is 120 V in the PDK. Different from the GaN LNA, a succeeding CMOS multi-function chip (MFC) can be seriously damaged even with 1 W power, which necessitates limiting the output power Different from the GaN LNA, a succeeding CMOS multi-function chip (MFC) can be seriously damaged even with 1 W power, which necessitates limiting the output power level of the LNA. By reducing the size of the final stage transistor, the control output power seems to be easy; however, a decrease in the size is limited to the specific design rule and aggravates the output impedance matching transformation ratio, which leads to the reduction of the bandwidth. To control the output power of the LNA and protect a succeeding silicon-based block, a diode-connected load was used at the final stage as shown in Figure 10b. The size of the limiter was carefully chosen considering the trade-off between the small signal gain reduction and the output power level control of the final stage. The output power of the LNA with the drain limiter was alleviated to 24 dBm.

SPDT T/R Switches
The S-parameters of the fabricated SPDT T/R switches were measured with the network analyzer Rohde & Schwarz ZNB40. As shown in Figure 13a, the measured insertion loss of the T/R switch achieved 1.21 dB at 9 GHz and less than 1.36 dB in the whole X-band. The measured return loss of the proposed T/R switch was better than 10 dB in the whole X band, which corresponded well with the simulation results. The isolation of the switch was better than 34 dB within the whole X-band. Moreover, SPDT switch version-A demonstrates exceptionally high linearity up to 46 dBm, which indicates it can be employed in the Tx path with a high output power as shown in Figure 13b. level of the LNA. By reducing the size of the final stage transistor, the control output power seems to be easy; however, a decrease in the size is limited to the specific design rule and aggravates the output impedance matching transformation ratio, which leads to the reduction of the bandwidth. To control the output power of the LNA and protect a succeeding silicon-based block, a diode-connected load was used at the final stage as shown in Figure 10b. The size of the limiter was carefully chosen considering the tradeoff between the small signal gain reduction and the output power level control of the final stage. The output power of the LNA with the drain limiter was alleviated to 24 dBm.

SPDT T/R Switches
The S-parameters of the fabricated SPDT T/R switches were measured with the network analyzer Rohde & Schwarz ZNB40. As shown in Figure 13a, the measured insertion loss of the T/R switch achieved 1.21 dB at 9 GHz and less than 1.36 dB in the whole X-band. The measured return loss of the proposed T/R switch was better than 10 dB in the whole X band, which corresponded well with the simulation results. The isolation of the switch was better than 34 dB within the whole X-band. Moreover, SPDT switch version-A demonstrates exceptionally high linearity up to 46 dBm, which indicates it can be employed in the Tx path with a high output power as shown in Figure 13b. As shown in Figure 14a, the measured insertion loss of SW-B achieved 0.66 dB at 9 GHz and less than 1.5 dB in the whole X-band. Even though the trend of S-parameters was slightly shifted to the low frequency due to the capacitive loading effect of the shunt transistors, the insertion loss of SW-B was better than SW-A as additional lossy inductors were eliminated. The measured SW-B achieved the insertion loss below 1 dB (0.66 dB at 9 GHz) within 3.7 GHz (7.8-11.2 GHz). The improvement of the insertion loss demonstrates that the 500 Ω resistor at the gate control path does not affect the performance of the switch from the gate voltage drop. The measured return loss of the proposed SW-B was better than 10 dB in the whole X band, which corresponded well with the simulation results. The isolation of the switch was better than 35 dB within the whole X-band. SPDT T/R switch version-B demonstrates comparably high linearity with the IP1dB larger than 44.7 dBm at 9 GHz as shown in Figure 14b. As shown in Figure 14a, the measured insertion loss of SW-B achieved 0.66 dB at 9 GHz and less than 1.5 dB in the whole X-band. Even though the trend of S-parameters was slightly shifted to the low frequency due to the capacitive loading effect of the shunt transistors, the insertion loss of SW-B was better than SW-A as additional lossy inductors were eliminated. The measured SW-B achieved the insertion loss below 1 dB (0.66 dB at 9 GHz) within 3.7 GHz (7.8-11.2 GHz). The improvement of the insertion loss demonstrates that the 500 Ω resistor at the gate control path does not affect the performance of the switch from the gate voltage drop. The measured return loss of the proposed SW-B was better than 10 dB in the whole X band, which corresponded well with the simulation results. The isolation of the switch was better than 35 dB within the whole X-band. SPDT T/R switch version-B demonstrates comparably high linearity with the IP 1dB larger than 44.7 dBm at 9 GHz as shown in Figure 14b.  Table 1 shows the performance comparison of X-band GaN SPDT switches recently reported in the literature. Both proposed SPDT T/R switches (SW-A and SW-B) have achieved outstanding performances with the lowest insertion loss and exhibited superior linearity in the X-band. Particularly, the insertion loss of both SPDT SW-A and SW-B was degraded by less than 0.1 dB up to 46 dBm and 44.7 dBm for SW-A and SW-B, respectively.  Figure 15a presents the measured small-signal S-parameters and pulsed large-signal performance of the proposed DA. The implemented driving amplifier was biased at VGG = −2.2 V with VDD = 26 V with the quiescent drain current of 130 mA. In this condition, each HEMT operates with a current density of 72 mA/mm. The measured 3 dB bandwidth was 3.5 GHz over 7.7-11.2 GHz with a peak gain of 19.3 dB at 8.2 GHz. The input and output return loss was also better than 10 dB over the 3 dB bandwidth. The measured large-signal performance result is given in Figure 15b. The measured saturated output power (Psat) achieved 38.0 dBm, and OP1dB was 25.8 dBm at 9 GHz. The implemented DA can drive the HPA with the output power of 32 dBm with a large signal gain of 14 dB, which is sufficient to drive the designed HPA to the optimal saturation point.  Table 1 shows the performance comparison of X-band GaN SPDT switches recently reported in the literature. Both proposed SPDT T/R switches (SW-A and SW-B) have achieved outstanding performances with the lowest insertion loss and exhibited superior linearity in the X-band. Particularly, the insertion loss of both SPDT SW-A and SW-B was degraded by less than 0.1 dB up to 46 dBm and 44.7 dBm for SW-A and SW-B, respectively.  Figure 15a presents the measured small-signal S-parameters and pulsed large-signal performance of the proposed DA. The implemented driving amplifier was biased at V GG = −2.2 V with V DD = 26 V with the quiescent drain current of 130 mA. In this condition, each HEMT operates with a current density of 72 mA/mm. The measured 3 dB bandwidth was 3.5 GHz over 7.7-11.2 GHz with a peak gain of 19.3 dB at 8.2 GHz. The input and output return loss was also better than 10 dB over the 3 dB bandwidth. The measured large-signal performance result is given in Figure 15b. The measured saturated output power (P sat ) achieved 38.0 dBm, and OP 1dB was 25.8 dBm at 9 GHz. The implemented DA can drive the HPA with the output power of 32 dBm with a large signal gain of 14 dB, which is sufficient to drive the designed HPA to the optimal saturation point.

High Power Amplifier
The implemented GaN HPA was measured for the small signal S-parameters and large-signal performance. The HPA was biased at VGG = −2.3 V with VDD = 26 V with the current density of each HEMT equal to 44 mA/mm. With this bias condition, the total quiescent drain current was 280 mA. Figure 16a shows the measured S-parameters, and the peak gain was 17.7 dB at 9.2 GHz, and the 3-dB bandwidth was 2.5 GHz from 8.5 to 11 GHz. Figure 16b illustrates the large-signal performance of the HPA at 9 GHz. For the large-signal measurement, the pulse-modulated RF signal was modulated with a 10% duty cycle and 100 μs pulse. The saturated output power was measured to be Psat = 20 Watt with a large signal power gain of 10.9 dB which corresponded well with the simulation.
At the saturation point of the output power, the peak drain current was 1.9 A, corresponding to the peak PAE of 35.6%. The drain current versus input power is compared in Figure 17.

High Power Amplifier
The implemented GaN HPA was measured for the small signal S-parameters and large-signal performance. The HPA was biased at V GG = −2.3 V with V DD = 26 V with the current density of each HEMT equal to 44 mA/mm. With this bias condition, the total quiescent drain current was 280 mA. Figure 16a shows the measured S-parameters, and the peak gain was 17.7 dB at 9.2 GHz, and the 3-dB bandwidth was 2.5 GHz from 8.5 to 11 GHz. Figure 16b illustrates the large-signal performance of the HPA at 9 GHz. For the large-signal measurement, the pulse-modulated RF signal was modulated with a 10% duty cycle and 100 µs pulse. The saturated output power was measured to be P sat = 20 Watt with a large signal power gain of 10.9 dB which corresponded well with the simulation.

High Power Amplifier
The implemented GaN HPA was measured for the small signal S-parameters and large-signal performance. The HPA was biased at VGG = −2.3 V with VDD = 26 V with the current density of each HEMT equal to 44 mA/mm. With this bias condition, the total quiescent drain current was 280 mA. Figure 16a shows the measured S-parameters, and the peak gain was 17.7 dB at 9.2 GHz, and the 3-dB bandwidth was 2.5 GHz from 8.5 to 11 GHz. Figure 16b illustrates the large-signal performance of the HPA at 9 GHz. For the large-signal measurement, the pulse-modulated RF signal was modulated with a 10% duty cycle and 100 μs pulse. The saturated output power was measured to be Psat = 20 Watt with a large signal power gain of 10.9 dB which corresponded well with the simulation.
At the saturation point of the output power, the peak drain current was 1.9 A, corresponding to the peak PAE of 35.6%. The drain current versus input power is compared in Figure 17. At the saturation point of the output power, the peak drain current was 1.9 A, corresponding to the peak PAE of 35.6%. The drain current versus input power is compared in Figure 17. The measured drain current was not saturated, while the simulated drain current was saturated at the output power saturation point. The discrepancy of the drain current between the simulation and measurement mainly resulted in the degradation of the peak PAE compared with that in the simulation.  Table 2 compares the implemented GaN HPA with the recently reported works in 0.25 μm at the X-band. The saturated power of the designed HPA was 43 dBm with a supply voltage of 26 V. It is noteworthy that HPA and DA were designed separately considering the design flexibility and the cost-effectiveness of the implemented transceiver front-end.

Low Noise Amplifier
The implemented LNA was measured to evaluate the noise figure (NF) and Sparameters. The gate bias voltage was VGG = −2.1 V, and the drain supply voltage was VDD = 10 V. With this condition, the four-stage LNA consumes 1.0 watts. Figure 18a shows the comparison between the simulated and measured results of the S-parameters of the LNA. The 3 dB bandwidth was 4.4 GHz (7.6-12 GHz) with a peak gain is 34.9 dB at 9 GHz. The The measured drain current was not saturated, while the simulated drain current was saturated at the output power saturation point. The discrepancy of the drain current between the simulation and measurement mainly resulted in the degradation of the peak PAE compared with that in the simulation. Table 2 compares the implemented GaN HPA with the recently reported works in 0.25 µm at the X-band. The saturated power of the designed HPA was 43 dBm with a supply voltage of 26 V. It is noteworthy that HPA and DA were designed separately considering the design flexibility and the cost-effectiveness of the implemented transceiver front-end.

Low Noise Amplifier
The implemented LNA was measured to evaluate the noise figure (NF) and S-parameters. The gate bias voltage was V GG = −2.1 V, and the drain supply voltage was V DD = 10 V. With this condition, the four-stage LNA consumes 1.0 watts. Figure 18a shows the comparison between the simulated and measured results of the S-parameters of the LNA. The 3 dB bandwidth was 4.4 GHz (7.6-12 GHz) with a peak gain is 34.9 dB at 9 GHz. The input and output return loss was better than 10 dB. The NF of the LNA was measured with the Y-factor method. Figure 18b presents the simulated and measured NF, which shows a large discrepancy between them. The measured NF at 9 GHz was 2.56 dB, and the maximum NF over the 3 dB bandwidth was 3 dB. It is noted that there is a large NF discrepancy between the simulation and measurement. The root cause of this discrepancy is an inaccurate device noise model provided by the PDK. A large signal measurement was also conducted to check the output power of the LNA. Figure 19a shows the output power of the LNA at 9 GHz, the saturated output power is 24.5 dBm and a 1-dB compressed input power (IP 1dB ) is −18 dBm. Due to the drain limiter at the final stage of the LNA, output power does not exceed 25 dBm, as it is expected in the simulation. To verify the robustness of the implemented LNA to the large input power, S-parameters of the LNA were measured before and after applying the input power of 6.3 watts (100 µs of the pulse width and 10% of the duty-cycle) to the implemented LNA several times at X-band as shown in Figure 19b. There was no noticeable degradation observed after applying the high input power to the LNA. The proposed LNA is compared with other reported X-band GaN LNAs as shown in Table 3. Since the proposed LNA is required to achieve a more than 30 dB gain, four cascaded stages consume a relatively large power consumption (1.0 watts). Considering its high gain performance, the power dissipation is acceptable.

Conclusions
This paper reported the X-band GaN front-end core MMIC blocks for a low-cost transmit-receive module (TRM) for an X-band AESA radar system. All the core MMICs were implemented in 0.25 µm GaN technology including SPDT T/R switch, low noise amplifier (LNA), driving amplifier (DA), and high power amplifier (HPA). The designed SPDT T/R switches utilized shunt switches and λ/4 transmission lines (T-lines) without any series switches to substitute a bulky circulator and external limiters in a conventional TRM. The implemented SPDT T/R switch version-A (SW-A) exhibited a low insertion loss between 1.06 and 1.36 dB in the whole X-band, and IP 1dB higher than 46 dBm, better than 34 dB of isolation was observed. The SPDT T/R switch version-B (SW-B) achieved a lower insertion loss below 1 dB (0.66 dB at 9 GHz), better than 35 dB of isolation in 7.8-11.5 GHz, and IP 1dB higher than 44.7 dBm. With the proposed low-loss T/R switches, the signal-to-noise ratio (SNR) of the GaN-based TRM can be comparable to the TRM with a GaAs Rx chain with a bulky circulator and limiter. For the Tx chain, DA and HPA were co-designed to achieve the output power of 43.0 dBm. The designed HPA achieved a peak small-signal gain of 17.7 dB at 9.2 GHz and a 3 dB bandwidth of 8.5-11 GHz. The P sat was 43 dBm at 9 GHz with a peak PAE of 35.6% and a large signal power gain of 10.9 dB. For the Rx chain, the LNA has a small-signal gain of 34.9 dB and a noise figure of 2.56 dB at 9 GHz with a wide 3 dB bandwidth covering 7.6-12 GHz. With the high feedback resistor at the gate and careful selection of the HEMT size, the implemented LNA successfully demonstrated its robustness from a high input power larger than 38 dBm at X-band.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.