A Fast Loss Model for Cascode GaN-FETs and Real-Time Degradation-Sensitive Control of Solid-State Transformers

This paper proposes a novel, degradation-sensitive, adaptive SST controller for cascode GaN-FETs. Unlike in traditional transformers, a semiconductor switch’s degradation and failure can compromise its robustness and integrity. It is vital to continuously monitor a switch’s health condition to adapt it to mission-critical applications. The current state-of-the-art degradation monitoring methods for power electronics systems are computationally intensive, have limited capacity to accurately identify the severity of degradation, and can be challenging to implement in real time. These methods primarily focus on conducting accelerated life testing (ALT) of individual switches and are not typically implemented for online monitoring. The proposed controller uses accelerated life testing (ALT)-based switch degradation mapping for degradation severity assessment. This controller intelligently derates the SST to (1) ensure robust operation over the SST’s lifetime and (2) achieve the optimal degradation-sensitive function. Additionally, a fast behavioral switch loss model for cascode GaN-FETs is used. This proposed fast model estimates the loss accurately without proprietary switch parasitic information. Finally, the proposed method is experimentally validated using a 5 kW cascode GaN-FET-based SST platform.


Introduction
In recent years, a number of studies have been conducted to find reliable power electronics alternatives to traditional transformers. Two of the most promising alternatives are solid-state transformers (SSTs) and high-temperature superconducting (HTS) transformers [1][2][3]. While both technologies offer significant advantages over traditional transformers, they differ in their design, capabilities, and potential applications. One of the key advantages of SSTs is their ability to control power flow, which makes them ideal for power electronics applications. SSTs will replace traditional transformers in modern industry, including use in electric vehicle charging and smart-grid applications, due to their low cost, high efficiency (>95%), and compact features [1]. Power semiconductor switches are among the most vulnerable components in a power electronic system (PES) [4]. These switches commonly experience high-frequency (HF) electro-thermal stresses in their SSTs during dynamic operation. Thus, monitoring switch aging and degradation and implementing a proactive degradation-sensitive control strategy are vital for real-world applications [5].
Switches mainly experience HF stresses during the HF dual active bridge (DAB) stage, as shown in Figure 1 [1]. A DAB control strategy minimizes the inductor current to achieve

Principles of the Proposed Controller
The Coffin-Manson method estimates an application's remaining useful life based on its operating conditions [16]. This model solely addresses the effect of instantaneous operating conditions on the life of the switch [9][10][11]14], monitoring the number of cycles elapsed to identify the level of degradation. As degradation is random, the switch might degrade at an accelerated rate, so this model includes high variance. Thus, it is important to complement this model with fault-precursor-based identification of degradation severity. Accelerated life testing (ALT)-based degradation mapping provides a switch degradation trajectory, which allows accurate switch-degradation severity assessment and offline planning of degradation-sensitive control [17]. Another essential feature of a degradation-sensitive controller is the ability to identify abrupt changes. The proposed controller intelligently integrates online lifetime-mapping features, degradation mapping based on accelerated life testing, and identification of unexpected degradation to derate the SST for life extension. The principles of the proposed degradation-sensitive controller are shown in Figure 2. The proposed controller uses information from the following three blocks: i.
Online switch lifetime mapping; ii.
Accelerated life testing (ALT)-based degradation mapping; The integration of renewable energy sources and new technologies into power systems has led to the development of a new reliability framework for modern power electronic systems [7]. Another study introduced a comprehensive approach that uses a photovoltaic inverter as an example to predict power electronic converter reliability, address wear-out failures, and optimize power system design, operation, and maintenance [8]. With the increasing demand for more electrical systems, reliability assessment and standardization have become increasingly important [7,8]. The development of guidelines is vital to achieving this objective, and current efforts are focused on creating them. Furthermore, this approach is applicable not only to the entire power electronic system but also to individual components. State-of-the-art DAB-control-based protection systems focus on post-fault scenarios [9][10][11][12][13], mainly by carrying out fault tolerance operations after a switch failure. Therefore, they require costly hardware redundancies and high system complexity, which commonly increase the system's size and weight [9,10]. Redundancy-based network-level power routing is not feasible in standalone SST-based EV charging applications [12]. In these applications, topology transformation methods can bypass fatal switch failure effects for a limited time. However, these methods double the current through the switch, resulting in higher switch stress and accelerated aging, which causes premature SST failure. They also require computationally exhaustive fault detection and isolation procedures. A powersharing control strategy is proposed to improve the reliability of power converters in DC microgrids by adjusting their loadings based on prior thermal damages, aiming to extend their lifespan and enhance the overall system reliability [14]. Previous studies [12][13][14][15] have relied solely on thermal loading information to determine the stage of degradation. In contrast, accelerated life testing (ALT) can provide additional insights into the degradation pattern, which have not been utilized in this study. In [11] and [13], an adaptive but complicated and costly cooling method for junction temperature control was proposed to extend switch life.
So far, SST control and protection strategies based on monitoring switch degradation have rarely been studied. If successful, these could offer a new, effective solution without costly redundancies. An SST could integrate switch health status into a controller to intelligently identify its health-optimal operating point. Techniques based on thermal cycle counting have a limited capacity to identify switch degradation; instead, they derate the PES based on the number of thermal cycles elapsed [9][10][11]15]. Thus, these methods fail to derate the PES if the switch is degraded early. Switch degradation mapping is critical to utilize the benefits of PES derating.
In this paper, a new degradation-sensitive controller is proposed for a cascode GaN-FET-based SST. The proposed controller uses intelligent thermal-cycle-counting methods and ALT-based switch degradation mapping to ensure safe and robust operation over the SST's life as well as to enable operation at optimal operating conditions for switch health. A degraded switch deteriorates quickly if the SST continues operating at rated conditions and causes early failure. To address this issue, the proposed controller estimates the optimal switch health condition at which to derate. This intelligent derating allows the SST to reach its target life and avoid unexpected shutdown. A linear quadratic regulator (LQR) determines these rating and derating conditions, estimating the optimal phase shift to ensure the SST's stability and robustness to system disturbance. A fast-behavioral switch loss model is used to identify switch degradation instantaneously with low complexity, enabling adaptive, real-time operation. This model does not require parasitic parameter estimation and exhaustive computational effort calculation, in contrast to existing analytical loss models. Although our approach is specifically developed for SST, it should be applicable to other power electronics systems as well.
The rest of the paper is organized as follows. In Section 2, the proposed controller's fundamentals are explained. Online switch lifetime mapping is discussed in Section 3, followed by accelerated-aging-based degradation mapping in Section 4. The design of the proposed controller is presented in Section 5, the design and performance of the LQR in Section 6, and experimental testing and validation in Section 7. The contributions of this paper and future research directions are explored in the conclusion in Section 8.

Principles of the Proposed Controller
The Coffin-Manson method estimates an application's remaining useful life based on its operating conditions [16]. This model solely addresses the effect of instantaneous operating conditions on the life of the switch [9][10][11]15], monitoring the number of cycles elapsed to identify the level of degradation. As degradation is random, the switch might degrade at an accelerated rate, so this model includes high variance. Thus, it is important to complement this model with fault-precursor-based identification of degradation severity. Accelerated life testing (ALT)-based degradation mapping provides a switch degradation trajectory, which allows accurate switch-degradation severity assessment and offline planning of degradation-sensitive control [17]. Another essential feature of a degradation-sensitive controller is the ability to identify abrupt changes. The proposed controller intelligently integrates online lifetime-mapping features, degradation mapping based on accelerated life testing, and identification of unexpected degradation to derate the SST for life extension. The principles of the proposed degradation-sensitive controller are shown in Figure 2. loss models. Although our approach is specifically developed for SST, it should be applicable to other power electronics systems as well.
The rest of the paper is organized as follows. In Section 2, the proposed controller's fundamentals are explained. Online switch lifetime mapping is discussed in Section 3, followed by accelerated-aging-based degradation mapping in Section 4. The design of the proposed controller is presented in Section 5, the design and performance of the LQR in Section 6, and experimental testing and validation in Section 7. The contributions of this paper and future research directions are explored in the conclusion in Section 8.

Principles of the Proposed Controller
The Coffin-Manson method estimates an application's remaining useful life based on its operating conditions [16]. This model solely addresses the effect of instantaneous operating conditions on the life of the switch [9][10][11]14], monitoring the number of cycles elapsed to identify the level of degradation. As degradation is random, the switch might degrade at an accelerated rate, so this model includes high variance. Thus, it is important to complement this model with fault-precursor-based identification of degradation severity. Accelerated life testing (ALT)-based degradation mapping provides a switch degradation trajectory, which allows accurate switch-degradation severity assessment and offline planning of degradation-sensitive control [17]. Another essential feature of a degradation-sensitive controller is the ability to identify abrupt changes. The proposed controller intelligently integrates online lifetime-mapping features, degradation mapping based on accelerated life testing, and identification of unexpected degradation to derate the SST for life extension. The principles of the proposed degradation-sensitive controller are shown in Figure 2. The proposed controller uses information from the following three blocks: i.
Online switch lifetime mapping; ii.
Accelerated life testing (ALT)-based degradation mapping; The proposed controller uses information from the following three blocks: i. Online switch lifetime mapping; ii. Accelerated life testing (ALT)-based degradation mapping; iii. Identification of unexpected degradation.
In block i, the number of cycles to failure (N f ) is estimated online based on the proposed behavioral switch loss model. In block ii, switch degradation is mapped based on the switch's fault precursor trajectory under ALT. On-state resistance (R DS,ON ) shows the highest sensitivity to switch degradation in cascode GaN-FETs [17,18]. This R DS,ON trajectory is statistically analyzed, and a degradation probability is mapped based on ALT. In block iii, R DS,ON is measured online and regularly evaluated to identify any sudden changes in switch health. The proposed controller has two functions-(i) a supervisory function and (ii) an operational function, as shown in Figure 2. In the supervisory function, dynamic programming is used to identify the switch's health status and estimate the optimal degradation-sensitive operating conditions based on the three blocks of inputs. In the operational function, an LQR regulates the optimal phase-shift angle based on the set degradation-sensitive operating point.
The following sections briefly describe the functions of the three blocks of the proposed controller.

Online Switch Lifetime Mapping
Block i estimates N f based on the junction temperature, which is estimated using a switch loss model. The procedure is shown in Figure 3. This block's three main components are the switch loss model, R-C Foster-network-based junction temperature estimation, and lifetime estimation. The switch loss causes are the mean junction temperature (T J,m ) and junction temperature variation (∆T J ). Wire-bond lift-off and solder fatigue are the two dominant open-circuit failure mechanisms triggered by HF thermo-mechanical stress. A mismatched coefficient of thermal expansion (CTE) between different layers increases the severity of this stress [17,19]. These dominant mechanisms result in wire-bond cracks and solder degradation or eventual lift-off. In the following subsections, these three components are discussed.
In block i, the number of cycles to failure (Nf) is estimated online based on the proposed behavioral switch loss model. In block ii, switch degradation is mapped based on the switch's fault precursor trajectory under ALT. On-state resistance (RDS,ON) shows the highest sensitivity to switch degradation in cascode GaN-FETs [17,18]. This RDS,ON trajectory is statistically analyzed, and a degradation probability is mapped based on ALT. In block iii, RDS,ON is measured online and regularly evaluated to identify any sudden changes in switch health.
The proposed controller has two functions-(i) a supervisory function and (ii) an operational function, as shown in Figure 2. In the supervisory function, dynamic programming is used to identify the switch's health status and estimate the optimal degradationsensitive operating conditions based on the three blocks of inputs. In the operational function, an LQR regulates the optimal phase-shift angle based on the set degradation-sensitive operating point.
The following sections briefly describe the functions of the three blocks of the proposed controller.

Online Switch Lifetime Mapping
Block i estimates Nf based on the junction temperature, which is estimated using a switch loss model. The procedure is shown in Figure 3. This block's three main components are the switch loss model, R-C Foster-network-based junction temperature estimation, and lifetime estimation. The switch loss causes are the mean junction temperature (TJ,m) and junction temperature variation (ΔTJ). Wire-bond lift-off and solder fatigue are the two dominant open-circuit failure mechanisms triggered by HF thermo-mechanical stress. A mismatched coefficient of thermal expansion (CTE) between different layers increases the severity of this stress [17,19]. These dominant mechanisms result in wire-bond cracks and solder degradation or eventual lift-off. In the following subsections, these three components are discussed.

Switch Loss Model for Cascode GaN-FETs
A fast and accurate behavioral loss model is proposed. In the cascode structure, a low-voltage (LV) Si-MOSFET is cascoded with a normally-on GaN-HEMT. The turn-off loss is different, especially from IGBT, due to the absence of a tailing current. An analytical loss model for cascode GaN-FETs was developed in [20][21][22][23][24] based on complex cascodestructure-induced parasitic capacitances and inductances. This analytical model thus requires a computationally exhaustive process and proprietary information. Additionally, this model requires expensive testing for parameter extraction. Piecewise linear models are faster but less accurate, and the effect of the PCB parasitic is not considered [25]. The proposed model was developed by analyzing and modeling the switching transition behavior of drain-source voltage (VDS) and drain current (Id) in the half-bridge configuration to overcome these challenges.

Switch Loss Model for Cascode GaN-FETs
A fast and accurate behavioral loss model is proposed. In the cascode structure, a low-voltage (LV) Si-MOSFET is cascoded with a normally-on GaN-HEMT. The turn-off loss is different, especially from IGBT, due to the absence of a tailing current. An analytical loss model for cascode GaN-FETs was developed in [20][21][22][23][24] based on complex cascode-structureinduced parasitic capacitances and inductances. This analytical model thus requires a computationally exhaustive process and proprietary information. Additionally, this model requires expensive testing for parameter extraction. Piecewise linear models are faster but less accurate, and the effect of the PCB parasitic is not considered [25]. The proposed model was developed by analyzing and modeling the switching transition behavior of drainsource voltage (V DS ) and drain current (I d ) in the half-bridge configuration to overcome these challenges.
Moreover, this behavioral model uses parameters easily extractable from the datasheet and double pulse test (DPT). This behavioral model reflects the effects of parasitic capacitances and commutation inductors. Thus, the proposed model is adaptable to highfrequency applications.
The switch loss has two components: switching loss (P sw ) and conduction loss (P cond ), calculated as follows: Conduction loss can be estimated as follows: Sensors 2023, 23, 4395

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where I L is the RMS load current and R DS,ON is the function of temperature and switch health status. P sw is the summation of turn-on and turn-off power losses.

Turn-on Loss Calculation
Commonly, a cascode GaN-FET's turn-on is modeled by LV Si-MOSFET, normally on GaN-HEMT's complex physics-based interactions. The proposed behavior-based model inherently addresses the effects of parasitic capacitors and commutation inductors and is thus accurate. The proposed model does not require the solving of complex high-degree polynomials and differential equations. The switching transition of V DS and I d during turn-on is shown in Figure 4a, and is divided into four regions, as follows: high-frequency applications.
The switch loss has two components: switching loss (Psw) and conduction loss (Pcond), calculated as follows: Conduction loss can be estimated as follows: where IL is the RMS load current and RDS,ON is the function of temperature and switch health status. Psw is the summation of turn-on and turn-off power losses.

Turn-on Loss Calculation
Commonly, a cascode GaN-FET's turn-on is modeled by LV Si-MOSFET, normally on GaN-HEMT's complex physics-based interactions. The proposed behavior-based model inherently addresses the effects of parasitic capacitors and commutation inductors and is thus accurate. The proposed model does not require the solving of complex highdegree polynomials and differential equations. The switching transition of VDS and Id during turn-on is shown in Figure 4a, and is divided into four regions, as follows:

Region I: LV Si Gate Charging
The LV Si-MOSFET controls the switching transitions of the cascode GaN-FET. The turn-on process starts when the LV Si-MOSFET's gate voltage reaches the threshold and a conducting channel is established in LV Si-MOSFET. The gate-drive loss (Pdri) can be expressed as follows: where QG is the gate charge, VG is the gate voltage, and fs is the switching frequency. Id starts rising when the gate-source voltage (VGS) of GaN-HEMT reaches its threshold and causes turn-on loss in cascode GaN-FET due to V-I overlapping. This V-I overlapping starts at t1, as shown in Figure 4a. 

Region II: Increasing Drain Current
In this region, the GaN-HEMT is fully turned on. Id increases linearly and reaches load current (IL). Thus, Id can be modeled in the proposed model as follows:  The LV Si-MOSFET controls the switching transitions of the cascode GaN-FET. The turn-on process starts when the LV Si-MOSFET's gate voltage reaches the threshold and a conducting channel is established in LV Si-MOSFET. The gate-drive loss (P dri ) can be expressed as follows: where Q G is the gate charge, V G is the gate voltage, and f s is the switching frequency. I d starts rising when the gate-source voltage (V GS ) of GaN-HEMT reaches its threshold and causes turn-on loss in cascode GaN-FET due to V-I overlapping. This V-I overlapping starts at t 1 , as shown in Figure 4a.

• Region II: Increasing Drain Current
In this region, the GaN-HEMT is fully turned on. I d increases linearly and reaches load current (I L ). Thus, I d can be modeled in the proposed model as follows: where 0 ≤ I d < I L and t 1 ≤ t < t 2 , and dI rise /d t is the rising rate of I d , which is a constant. The value of dIrise/dt depends on the commutation inductances. The value is estimated from the DPT. During this period, V DS is assumed to be constant at V DS,OFF . The energy loss during this period is expressed as follows: • Region III: Decreasing drain-source voltage In the half-bridge, two switches in one leg switch complementarily. In region III, I L supplies I d to the top switch and reverse-conducting current (I RR ) to the bottom switch. I d rises at dI rise /d t until it reaches I L + I RR . There are two sub-regions in region III. In sub-region a, I d increases due to commutation inductances and internal parasitics. The behavior of I d is modeled as follows: where I L ≤ I d < I L + I RR and t 2 ≤ t < t 22 . In this sub-region, dIrise/dt remains the same as in region II. V DS linearly drops to an off-state V DS (V DS,OFF ) during this time. This drop is due to the increase in I d over I L . The behavioral model of V DS can be expressed as follows: where dV DS,1 /d t is the falling rate of V DS . The energy loss in this sub-region is as follows: In subregion b, the reverse recovery charge needs to be removed from the bottom switch. The rate of change in I d is defined by the reverse recovery current of the bottom switch. In this sub-region, I d falls from I L + I RR to I L when V DS falls from V DS,OFF ,1 to V DS,ON . The internal parasitics of the cascode structure cause these transitions. The analytical model requires internal parasitic information, which is not available. In the proposed model, the behaviors of I d and V DS can be modeled as follows: This model inherently addresses the effects of parasitics, which affect the rates of change in V DS and I d . Thus, the modeling approach ensures speed and accuracy. The energy loss is calculated as follows: • Region IV: Ringing Region In this region, I d and V DS behave like a damping system and reach their steady states at I L and V DS,ON , respectively. These tendencies can be modeled as follows: where A 1 and A 2 are the amplitudes of I d and V DS , respectively; α 1 is the decay rate of I d and V DS ; and ω 01 is the frequency of I d and V DS , respectively. At the start of this region, I d is I L , V DS is V DS,ON , and θ and ψ are zero. The loss in this region is as follows: where E turn-on-IV is a function of ω 01 , α 01 , A 1 , and A 2 . These parameters are estimated from the double-pulse test. The total turn-on loss is the summation of the losses in regions I, II, and III:

Turn-off Loss Calculation
Like turn-on loss, turn-off loss is modeled by analyzing the switching transition behavior. This model is fast and easily implementable without any proprietary information and costly testing. The turn-off transition of V DS and I d during the turn-off process is shown in Figure 4b, where the turn-off region is divided into three regions. •

Region-I: Gate Capacitor Discharge
The turn-off process starts when V g is zero and initiates the discharge process of the gate-source capacitor of the LV Si-MOSFET. In this region, there are insignificant changes in V DS and I d . Thus, there is only an insignificant gate-drive loss, similar to that in Equation (3).

• Region II: Decreasing Drain Current
In region II, GaN-HEMT is shut down due to the interaction between the gate capacitance of the LV MOSFET and GaN-HEMT. I d decreases from I L to zero. V DS increases from V DS,ON to V ds2,off , which is greater than the input voltage (V in ). These behaviors of I d and V DS can be modeled as follows: where I d (t 1 ) = I L at t = t 1 and I d (t 2 ) = 0 at t = t 2 .
where V DS (t 1 ) = V DS,ON at t = t 1 and VDS(t 2 ) = V DS,off at t = t 2 . These behavioral models address the effects of the parasitic components on the switching transition while avoiding complex modeling and exhaustive calculations. The energy loss in this region is as follows: •

Region III: Ringing Region
In region III, I d and V DS reach steady-state conditions at zero and V DS,OFF , respectively. During this period, I d and V DS behave like an underdamped system. This behavior is modeled as follows: V DS (t) = ∆V DS exp(−α 2 t) cos(ω o2 t) (20) where, at t = t 3 , I d = 0 and V DS = V DS,OFF , A 3 is the amplitude of the overdamped system, α 2 is the decaying rate, and ω o2 is the decaying frequency. The turn-off loss is as follows: where E turn-on-III is a function of ω 02 , α 02 , A 3 , and ∆V DS . These parameters are estimated from the DPT. The total turn-off loss is the summation of the losses as follows: This behavioral model is a fast and efficient alternative to complex analytical loss models. Addressing parasitic capacitances and commutation inductances using the time series behavioral model results in fast and accurate switch loss estimation.

R-C Foster-Model-Based Junction Temperature Estimation
The R-C Foster model is the second component in block I, as shown in Figure 3. Switch loss is translated into T J using the R-C Foster model as follows: where T J is the switch's junction temperature, Z th is the thermal impedance, and T C is the case temperature. Z th is estimated as follows: where r i is the thermal resistance of the switch and τi is the thermal time constant. Thermal time constraints are expressed as τ i = r i C th,i , where C th,i is the thermal capacitance. These thermal parameters are estimated from the switch's transient thermal impedance curve provided in the datasheet.

Lifetime Estimation
The Coffin-Manson life estimation model relates Nf to T J,m and ∆T J . This model estimates the instantaneous variation in N f due to a change in operating conditions. The model can be expressed as follows: where T J,m is the minimum junction temperature and A, b 1 , b 2 , and b 3 are the empirical coefficients. These empirical coefficients and the estimated value, T J , include estimation error uncertainties. Switch lifetime consumption accelerates due to changes in ∆T J and T J,m , as follows: where D.A.F is the degradation acceleration factor when the operation point changes from (∆T J1 , T J1,m ) to (∆T J2 , T J2,m ) due to switch degradation. The damage to the switch is estimated based on Miner's linear damage rule as follows: where C is the switch's consumed lifetime and n i is the number of cycles consumed by the switch. The information on consumed lifetime is used with ALT-based switch degradation mapping to address deviations in the operating conditions and switch lifetime acceleration.

Degradation Mapping Based on Accelerated Life Testing
The typical lifetime of a power semiconductor switch is 10-12 years [5]. ALT maps this trajectory to a logical timeframe. ALT of a cascode GaN-FET provides critical insight into the relationship between R DS,ON trajectory dynamics and consumed life. The R DS,ON trajectory shows sensitivity to packaging-related failures in the cascode GaN-FET, such as wire-bond lift-off (WBLO) and solder crack [18,26]. Switch degradation is mapped by analyzing the R DS,ON trajectories.
In this paper, a power-cycling ALT is used for mapping the R DS,ON trajectory. The ALT conditions and switch degradation mappings are provided in Section 7.2. The R DS,ON trajectories show that there are three distinct regions in the life of the cascode GaN-FET-(i) the healthy region, (ii) the slow degradation (SD) or constant degradation (CD) region, and (iii) the exponential degradation (ED) region. These tendencies in the R DS,ON trajectory are shown in Figure 5a. There are also R DS,ON trajectories that are outliers to the typical trajectories, as shown in Figure 5b. These outlier trajectories bias the mean R DS,ON trajectory. It is logical to model the degradation trajectory using the median R DS,ON trajectory, which is not significantly affected by outliers. This median trajectory is modeled as follows: where R DS,ON, med is the median of the R DS,ON trajectories. This mapping of degradation using Equation (28) is shown in Figure 5b.
mapping to address deviations in the operating conditions and switch lifetime acceleration.

Degradation Mapping Based on Accelerated Life Testing
The typical lifetime of a power semiconductor switch is 10-12 years [5]. ALT maps this trajectory to a logical timeframe. ALT of a cascode GaN-FET provides critical insight into the relationship between RDS,ON trajectory dynamics and consumed life. The RDS,ON trajectory shows sensitivity to packaging-related failures in the cascode GaN-FET, such as wire-bond lift-off (WBLO) and solder crack [18,26]. Switch degradation is mapped by analyzing the RDS,ON trajectories.
In this paper, a power-cycling ALT is used for mapping the RDS,ON trajectory. The ALT conditions and switch degradation mappings are provided in Section 7.2. The RDS,ON trajectories show that there are three distinct regions in the life of the cascode GaN-FET-(i) the healthy region, (ii) the slow degradation (SD) or constant degradation (CD) region, and (iii) the exponential degradation (ED) region. These tendencies in the RDS,ON trajectory are shown in Figure 5a. There are also RDS,ON trajectories that are outliers to the typical trajectories, as shown in Figure 5b. These outlier trajectories bias the mean RDS,ON trajectory. It is logical to model the degradation trajectory using the median RDS,ON trajectory, which is not significantly affected by outliers. This median trajectory is modeled as follows: where RDS,ON, med is the median of the RDS,ON trajectories. This mapping of degradation using Equation (28) is shown in Figure 5b.

A Degradation-Sensitive Controller for SSTS
The proposed controller operates using two functions: a supervisory function and an operational function, as shown in Figure 2. The dynamically programmed supervisory function determines a switch-health-sensitive operating point. Based on this operating point, the LQR process estimates the optimal phase shift for the SST.

Dynamic Programmed Supervisory Function
Dynamic programming uses switch degradation mapping to estimate the necessary operating conditions to achieve a target lifetime for the SST. To achieve the target lifetime under the proposed method, the SST operates using the optimal derating trajectory based on the cost function, as follows: where C rated is the rated lifetime under constant junction temperature variation and C degraded,i is the consumed lifetime. The cost function is minimal when the rated value is equal to a switch's lifetime. The objective of the dynamically programmed supervisory function is to maximize J by adaptively selecting operating conditions based on switch health status. This strategy is shown graphically in Figure 6. This strategy ensures constant junction temperature variation and uniform lifetime consumption. The controller is designed as follows: Minimize: Arg max C degraded = (C 1 + C 2 + C 3 ) Subject to: Constraint 1: C 1 > 0, C 2 > 0, C 3 > 0 Constraint 2: 0.8P rated ≤ P ≤ P rated Constraint 3: C degradate ≤ C rated Constraint 4: P II > P III where C 1 , C 2 , and C 3 are consumed life in regions I, II, and III, respectively. The derating algorithm is shown in Figure 6. As the switch will be more degraded in the exponential degradation (ED) region than in the slow degradation (SD) region, it is logical to impose higher derating in the ED region. Based on the constraints, the allowed operating conditions are shown in Figure 7. When the switch is healthy, the SST operates as rated. However, the SD and ED regions' operating conditions are programmed based on constraints 1-4. If the SST operates at P min , it will have a maximum lifetime, but it will violate constraint 3. If the SST operates at P rated , J will be maximized, but the SST will fail before its target lifetime. Different combinations of operating conditions in these two regions lead to different lifetimes for the SST. To integrate these dynamic operating conditions, Equation (26) is used to estimate lifetime consumption under each condition. E on and E off are integrated into the proposed controller as a look-up table to reduce the computational burden.
where Crated is the rated lifetime under constant junction temperature variation and Cdegraded,i is the consumed lifetime. The cost function is minimal when the rated value is equal to a switch's lifetime. The objective of the dynamically programmed supervisory function is to maximize J by adaptively selecting operating conditions based on switch health status. This strategy is shown graphically in Figure 6. This strategy ensures constant junction temperature variation and uniform lifetime consumption. The controller is designed as follows: Minimize: Arg C C C C Subject to: Constraint 1: C 0, C 0, C 0 Constraint 2: 0.8 P P P

Constraint 3: C C
Constraint 4: P P where C1, C2, and C3 are consumed life in regions I, II, and III, respectively. The derating algorithm is shown in Figure 6. As the switch will be more degraded in the exponential degradation (ED) region than in the slow degradation (SD) region, it is logical to impose higher derating in the ED region. Based on the constraints, the allowed operating conditions are shown in Figure 7. When the switch is healthy, the SST operates as rated. However, the SD and ED regions' operating conditions are programmed based on constraints 1-4. If the SST operates at Pmin, it will have a maximum lifetime, but it will violate constraint 3. If the SST operates at Prated, J will be maximized, but the SST will fail before its target lifetime. Different combinations of operating conditions in these two regions lead to different lifetimes for the SST. To integrate these dynamic operating conditions, Equation (26) is used to estimate lifetime consumption under each condition. Eon and Eoff are integrated into the proposed controller as a look-up table to reduce the computational burden.

LQR-Based Operational Function
A regulator is required to control the DAB stage in SST to deliver the reference voltage. In the proposed controller, the operational function uses an LQR as this regulator. In this sub-section, this LQR is described; the LQR ensures the optimal phase-shift angle for

LQR-Based Operational Function
A regulator is required to control the DAB stage in SST to deliver the reference voltage. In the proposed controller, the operational function uses an LQR as this regulator. In this sub-section, this LQR is described; the LQR ensures the optimal phase-shift angle for the rated or derated operating condition set by the supervisory function. The LQR shows robust performance under system disturbance and estimates the optimal phase-shift angle to ensure efficiency. The LQR design requires a state-space model of the DAB stage. The equivalent circuit in the DAB is shown in Figure 8, where L is the HF transformer's leakage inductance, VAB is the inverter output, and VCD is the rectifier input voltage.

LQR-Based Operational Function
A regulator is required to control the DAB stage in SST to deliver the reference voltage. In the proposed controller, the operational function uses an LQR as this regulator. In this sub-section, this LQR is described; the LQR ensures the optimal phase-shift angle for the rated or derated operating condition set by the supervisory function. The LQR shows robust performance under system disturbance and estimates the optimal phase-shift angle to ensure efficiency. The LQR design requires a state-space model of the DAB stage. The equivalent circuit in the DAB is shown in Figure 8, where L is the HF transformer's leakage inductance, VAB is the inverter output, and VCD is the rectifier input voltage. The average model of the output stage of the DAB is shown in Figure 8. Using Kirchhoff's current law, where Vi is the input voltage, Vo is the output voltage, RL is the load, Co is the output capacitor, and fs is the switching frequency. The small-signal model of this output average model for small variations in vo and d is as follows: The state-space model of the DAB is as follows: The average model of the output stage of the DAB is shown in Figure 8. Using Kirchhoff's current law, where V i is the input voltage, V o is the output voltage, RL is the load, C o is the output capacitor, and f s is the switching frequency. The small-signal model of this output average model for small variations in v o and d is as follows: The state-space model of the DAB is as follows: In this state-space model, a new variable, v o dt, is introduced, which results in zero steady-state error. The quadratic cost function of the system is as follows: where J LQR is the quadratic cost function, Q is a 2-by-2 positive semi-definite matrix, and R is a scalar that should be positive. The closed-loop poles' locations depend on the choices of Q and R. In this paper, R = 1 and Q = [q 1 0; 0 q 2 ]. Thus, q 1 and q 2 determine the speed and damping of the system. For the state feedback, it is assumed that where k = k 1 k 2 represents the feedback gain.

Putting Equation (34) into Equation (35), it is found that
The optimal solution for k is found as follows: where P is the solution of the algebraic Recatti equation, as follows:

LQR Design and Its Performance Analysis
The LQR design requires the operating point information as shown in Equation (30). The operating frequency of the SST is 50 kHz; the rated voltage and power are 400 V and 5 kW, respectively; the leakage inductance is 53 µH; and the output capacitance is 120 µF. Based on this operating condition and the system information, the LQR is designed to have sufficient controller speed and zero steady-state error. The root locus and the step response of the modeled LQR controller are shown in Figure 9a where JLQR is the quadratic cost function, Q is a 2-by-2 positive semi-definite matrix, and R is a scalar that should be positive. The closed-loop poles' locations depend on the choices of Q and R.
In this paper, R = 1 and Q = [q1 0; 0 q2]. Thus, q1 and q2 determine the speed and damping of the system. For the state feedback, it is assumed that where k k k represents the feedback gain.
Putting Equation (34) into Equation (35), it is found that The optimal solution for k is found as follows: where P is the solution of the algebraic Recatti equation, as follows: PA A P PBR B Q 0 (37)

LQR Design and its Performance Analysis
The LQR design requires the operating point information as shown in Equation (30). The operating frequency of the SST is 50 kHz; the rated voltage and power are 400 V and 5 kW, respectively; the leakage inductance is 53 µH; and the output capacitance is 120 µF. Based on this operating condition and the system information, the LQR is designed to have sufficient controller speed and zero steady-state error. The root locus and the step response of the modeled LQR controller are shown in Figure 9a

Validation of the Behavioural Switch Loss Model
Commutation inductance due to the PCB layout plays a vital role in switching loss estimation. These inductances change with the PCB layout, which is application dependent. Thus, it is essential to conduct a DPT on the same PCB layout as the SST to address these inductances' effect on switching loss. V DS and Id measurements require high-bandwidth probes. A differential voltage probe (TMDP0200) and coaxial shunt 0.1 Ω SSDN-10 current sensor are used for fast, high-precision measurements. V DS and I d are shown in Figure 10 during the turn-on and turn-off transitions. Turn-on and turn-off losses are estimated by calculating energy losses due to the crossover of V DS and I d . Moreover, these signals are properly aligned to improve the integrity of the testing. ent. Thus, it is essential to conduct a DPT on the same PCB layout as the SST to address these inductances' effect on switching loss. VDS and Id measurements require high-bandwidth probes. A differential voltage probe (TMDP0200) and coaxial shunt 0.1 Ω SSDN-10 current sensor are used for fast, high-precision measurements. VDS and Id are shown in Figure 10 during the turn-on and turn-off transitions. Turn-on and turn-off losses are estimated by calculating energy losses due to the crossover of VDS and Id. Moreover, these signals are properly aligned to improve the integrity of the testing. The rates of change in VDS and Id during turn-on and turn-off are estimated from the DPT test and the datasheet, along with ringing region parameters. These parameters are used in Equations (3)-(25) for switching loss estimation and are integrated into the controller. The estimated switching loss is compared with the measured loss from the DPT at different operating conditions to validate the proposed switching loss model, as shown in Figure 11. This behavioral switching-loss model closely follows the experimental switching loss tendency and has a 2.3% average mean squared error. The model is fast, parameter extraction is easy, and the model follows the experimental model's loss tendency closely. The rates of change in V DS and I d during turn-on and turn-off are estimated from the DPT test and the datasheet, along with ringing region parameters. These parameters are used in Equations (3)-(25) for switching loss estimation and are integrated into the controller. The estimated switching loss is compared with the measured loss from the DPT at different operating conditions to validate the proposed switching loss model, as shown in Figure 11. This behavioral switching-loss model closely follows the experimental switching loss tendency and has a 2.3% average mean squared error. The model is fast, parameter extraction is easy, and the model follows the experimental model's loss tendency closely. these inductances' effect on switching loss. VDS and Id measurements require high-bandwidth probes. A differential voltage probe (TMDP0200) and coaxial shunt 0.1 Ω SSDN-10 current sensor are used for fast, high-precision measurements. VDS and Id are shown in Figure 10 during the turn-on and turn-off transitions. Turn-on and turn-off losses are estimated by calculating energy losses due to the crossover of VDS and Id. Moreover, these signals are properly aligned to improve the integrity of the testing. The rates of change in VDS and Id during turn-on and turn-off are estimated from the DPT test and the datasheet, along with ringing region parameters. These parameters are used in Equations (3)-(25) for switching loss estimation and are integrated into the controller. The estimated switching loss is compared with the measured loss from the DPT at different operating conditions to validate the proposed switching loss model, as shown in Figure 11. This behavioral switching-loss model closely follows the experimental switching loss tendency and has a 2.3% average mean squared error. The model is fast, parameter extraction is easy, and the model follows the experimental model's loss tendency closely.

Validation of the Degradation-Sensitive Controller
An experimental setup for the degradation-sensitive controller is shown in Figure 12. The operating frequency is 50 kHz, the rated input and output voltage is 400 V, the rated power is 5 kW, and the leakage inductance is 53 µH.

Validation of the Degradation-Sensitive Controller
An experimental setup for the degradation-sensitive controller is shown in Figure 12. The operating frequency is 50 kHz, the rated input and output voltage is 400 V, the rated power is 5 kW, and the leakage inductance is 53 µH.  Figure 13. In the power cycling ALT test, the switch's case temperature was varied between 25 °C and 100 °C using active-switch heating. To measure VDS,ON and monitor RDS,ON in real time, a signal-conditioning circuit was utilized. For a detailed description of this circuit, please refer to our previous publication [19], and the shunt resistor in the phase leg was used to measure Id. The RDS,ON measurement was sampled at a steady state to avoid the effect of switching transients. To reduce the effect of noise, 50 RDS,ON samples were averaged. These RDS,ON samples were also temperature scaled.  The R DS,ON trajectories of the cascode GaN-FET under ALT are shown in Figure 13. In the power cycling ALT test, the switch's case temperature was varied between 25 • C and 100 • C using active-switch heating. To measure V DS,ON and monitor R DS,ON in real time, a signal-conditioning circuit was utilized. For a detailed description of this circuit, please refer to our previous publication [19], and the shunt resistor in the phase leg was used to measure I d . The R DS,ON measurement was sampled at a steady state to avoid the effect of switching transients. To reduce the effect of noise, 50 R DS,ON samples were averaged. These R DS,ON samples were also temperature scaled.

Validation of the Degradation-Sensitive Controller
An experimental setup for the degradation-sensitive controller is shown in Figure 12. The operating frequency is 50 kHz, the rated input and output voltage is 400 V, the rated power is 5 kW, and the leakage inductance is 53 µH.  Figure 13. In the power cycling ALT test, the switch's case temperature was varied between 25 °C and 100 °C using active-switch heating. To measure VDS,ON and monitor RDS,ON in real time, a signal-conditioning circuit was utilized. For a detailed description of this circuit, please refer to our previous publication [19], and the shunt resistor in the phase leg was used to measure Id. The RDS,ON measurement was sampled at a steady state to avoid the effect of switching transients. To reduce the effect of noise, 50 RDS,ON samples were averaged. These RDS,ON samples were also temperature scaled.  It was observed that, until 60% of the way through their life, the switches were in the healthy region. In this region, ∆R DS,ON is between 0% and 2%. From 60% to 80% of the switches' lifetime, the switches were in the SD region, where ∆R DS,ON is between 2% and 7%. When ∆R DS,ON is greater than 7%, the switch is in the ED region. The statistically modeled median R DS,ON and the dynamically programmed estimated optimal operating trajectory are shown in Figure 14.
healthy region. In this region, ΔRDS,ON is between 0% and 2%. From 60% to 80% of the switches' lifetime, the switches were in the SD region, where ΔRDS,ON is between 2% and 7%. When ΔRDS,ON is greater than 7%, the switch is in the ED region. The statistically modeled median RDS,ON and the dynamically programmed estimated optimal operating trajectory are shown in Figure 14. The SST was operated with a new switch, a 40% degraded switch, and an 80% degraded switch to validate the proposed control system's applicability. The ΔRDS,ON values were 1.6% and 7% for the 40% and 80% degraded switches, respectively. The switches were degraded using ALT. The SST operates at a rated inductor current of Vo = 400 V when the switch is healthy, as shown in Figure 15. As a 40% degraded switch is also in the healthy region, the SST keeps operating in the rated condition. The inductor current is decreased when the degradation-sensitive degradation controller identifies the switch as being in the ED region, as shown in Figure 15. The optimal operating condition was identified as Vo = 360 V.  Figure 17. When TJ,m and ΔTJ are reduced by 1 °C, the CDF becomes less steep. If the switch keeps operating in the rated condition, it will fail at 96% of the rated lifetime. The proposed derating condition considers switch degradation and achieves the rated lifetime, extending the switch's life by 4%. This extended life is crucial for scheduling maintenance before the switch fails. The SST was operated with a new switch, a 40% degraded switch, and an 80% degraded switch to validate the proposed control system's applicability. The ∆R DS,ON values were 1.6% and 7% for the 40% and 80% degraded switches, respectively. The switches were degraded using ALT. The SST operates at a rated inductor current of V o = 400 V when the switch is healthy, as shown in Figure 15. As a 40% degraded switch is also in the healthy region, the SST keeps operating in the rated condition. The inductor current is decreased when the degradation-sensitive degradation controller identifies the switch as being in the ED region, as shown in Figure 15. The optimal operating condition was identified as V o = 360 V. healthy region. In this region, ΔRDS,ON is between 0% and 2%. From 60% to 80% of the switches' lifetime, the switches were in the SD region, where ΔRDS,ON is between 2% and 7%. When ΔRDS,ON is greater than 7%, the switch is in the ED region. The statistically modeled median RDS,ON and the dynamically programmed estimated optimal operating trajectory are shown in Figure 14. The SST was operated with a new switch, a 40% degraded switch, and an 80% degraded switch to validate the proposed control system's applicability. The ΔRDS,ON values were 1.6% and 7% for the 40% and 80% degraded switches, respectively. The switches were degraded using ALT. The SST operates at a rated inductor current of Vo = 400 V when the switch is healthy, as shown in Figure 15. As a 40% degraded switch is also in the healthy region, the SST keeps operating in the rated condition. The inductor current is decreased when the degradation-sensitive degradation controller identifies the switch as being in the ED region, as shown in Figure 15. The optimal operating condition was identified as Vo = 360 V.  Figure 17. When TJ,m and ΔTJ are reduced by 1 °C, the CDF becomes less steep. If the switch keeps operating in the rated condition, it will fail at 96% of the rated lifetime. The proposed derating condition considers switch degradation and achieves the rated lifetime, extending the switch's life by 4%. This extended life is crucial for scheduling maintenance before the switch fails.  Figure 17. When T J,m and ∆T J are reduced by 1 • C, the CDF becomes less steep. If the switch keeps operating in the rated condition, it will fail at 96% of the rated lifetime. The proposed derating condition considers switch degradation and achieves the rated lifetime, extending the switch's life by 4%. This extended life is crucial for scheduling maintenance before the switch fails.

Conclusions
This paper proposes a degradation-sensitive controller for an SST that intelligently derates the system's power based on the switch's health in order to prevent system failure before the end of the switch's expected lifetime. The proposed controller increases the SST's lifetime by 4% over a traditional controller by derating the SST to 80% of its rated power. The proposed approach involves mapping switch degradation to derating levels, with the system operating at its rated conditions until 60% of its consumed life, followed by a gradual reduction of power levels based on switch degradation, and a forced shutdown if degradation exceeds 90%, effectively extending the lifetime of the system. This lifetime extension is achieved by reducing TJ,m and ΔTJ limits by 1 °C. The objective of this strategy is to maintain a consistent temperature variation while ensuring that TJ,m does not increase. This is particularly important because an increase in its value can significantly reduce the device's lifetime. Although the proposed controller derates the SST with switch degradation, this extended lifetime is significant for maintenance scheduling and avoidance of unexpected failure.
The proposed fast behavioral cascode GaN-FET switch loss model shows an average mean squared error of 2.3% and does not require proprietary switch information. The model parameters are easily extractable from the datasheet and DPT, and the loss model

Conclusions
This paper proposes a degradation-sensitive controller for an SST that intelligently derates the system's power based on the switch's health in order to prevent system failure before the end of the switch's expected lifetime. The proposed controller increases the SST's lifetime by 4% over a traditional controller by derating the SST to 80% of its rated power. The proposed approach involves mapping switch degradation to derating levels, with the system operating at its rated conditions until 60% of its consumed life, followed by a gradual reduction of power levels based on switch degradation, and a forced shutdown if degradation exceeds 90%, effectively extending the lifetime of the system. This lifetime extension is achieved by reducing TJ,m and ΔTJ limits by 1 °C. The objective of this strategy is to maintain a consistent temperature variation while ensuring that TJ,m does not increase. This is particularly important because an increase in its value can significantly reduce the device's lifetime. Although the proposed controller derates the SST with switch degradation, this extended lifetime is significant for maintenance scheduling and avoidance of unexpected failure.
The proposed fast behavioral cascode GaN-FET switch loss model shows an average mean squared error of 2.3% and does not require proprietary switch information. The model parameters are easily extractable from the datasheet and DPT, and the loss model

Conclusions
This paper proposes a degradation-sensitive controller for an SST that intelligently derates the system's power based on the switch's health in order to prevent system failure before the end of the switch's expected lifetime. The proposed controller increases the SST's lifetime by 4% over a traditional controller by derating the SST to 80% of its rated power. The proposed approach involves mapping switch degradation to derating levels, with the system operating at its rated conditions until 60% of its consumed life, followed by a gradual reduction of power levels based on switch degradation, and a forced shutdown if degradation exceeds 90%, effectively extending the lifetime of the system. This lifetime extension is achieved by reducing T J,m and ∆T J limits by 1 • C. The objective of this strategy is to maintain a consistent temperature variation while ensuring that T J,m does not increase. This is particularly important because an increase in its value can significantly reduce the device's lifetime. Although the proposed controller derates the SST with switch degradation, this extended lifetime is significant for maintenance scheduling and avoidance of unexpected failure.
The proposed fast behavioral cascode GaN-FET switch loss model shows an average mean squared error of 2.3% and does not require proprietary switch information. The model parameters are easily extractable from the datasheet and DPT, and the loss model does not require exhaustive computation. Though it is developed for SST, it should be applicable to other power electronics systems as well. The integration of health-monitoring systems and degradation-sensitive controllers into digital twin and cloud computing platforms could be useful for industrial and electric transport maintenance and asset management.