Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy †

This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS). The TDC in the EIS system must handle a wide input-time range for analysis in the low-frequency range and have a high resolution for analysis in the high-frequency range. The proposed TDC adopts a coarse counter to support a wide input-time range and cascaded time interpolators to improve the time resolution in the high-frequency analysis without increasing the counting clock speed. When the same large interpolation factor is adopted, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. A reconfigurable time interpolation factor is adopted to maintain the phase resolution with reasonable measurement time. The fabricated TDC has a peak-to-peak phase error of less than 0.72° over the input frequency range from 1 kHz to 512 kHz and the phase error of less than 2.70° when the range is extended to 2.048 MHz, which demonstrates a competitive performance when compared with previously reported designs.


Introduction
Electrical impedance spectroscopy (EIS), which measures the impedance over a range of frequencies, has been widely used in today's biomedical applications such as body composition analysis [1][2][3], cancer diagnosis [4][5][6], and detection of allergic contact reaction [7], and so on. The frequency range from 1 kHz to several MHz, which is associated with the polarization of macromolecules [8], is required for these applications. With growing demands on portable EIS systems, today's research is focused on designing fully integrated EIS systems that support a wide frequency range.

Background and Design Specifications
This section describes the impedance measurement principle and phase measurement scheme in EIS systems. From this background, design specifications are derived at the end of the section.

Impedance Measurement Principle
When a sinusoidal current signal iin(t) is injected into the target material, a resulting sinusoidal voltage signal vb(t) is generated, and its magnitude and time delay with respect to iin(t) depend on the impedance of the material, as shown in Figure 1. Zb is the impedance of the target material, and |Zb| and θ are the magnitude and phase of Zb, respectively. Polar demodulators measure the magnitude and time delay of vb(t) for a particular frequency. |Zb| and θ can be calculated as follows: where |vb(t)| and Tb are the magnitude and time delay of vb(t), respectively. |IIN| is the magnitude of iin(t), and Tin is the period of iin(t) and vb(t). Impedance spectrum is obtained by using the FRA method, which analyzes one frequency at a time, repeatedly with sweeping the frequency [9]. Figure 2 shows the phase measurement scheme adopted in polar demodulators [10,11,[15][16][17]. When iin(t) is injected into the target material and reference resistor, vr(t) with the same phase as iin(t) is generated from the resistor in addition to vb(t). Comparators convert vr(t) and vb(t) to clock signals, ϕr and ϕb, from which an XOR gate and an SR latch create clock signals, ϕXOR and ϕSR, respectively. These clock signals have the pulse width of Tb, which corresponds to θ, as shown in Figure 2. From Equation (2), when the frequency of the injected current, fin = 1/Tin is known, θ can be determined by measuring Tb. Polar demodulators measure the magnitude and time delay of v b (t) for a particular frequency. |Z b | and θ can be calculated as follows:

Phase Measurement Scheme in Polar Demodulators
where |v b (t)| and T b are the magnitude and time delay of v b (t), respectively. |I IN | is the magnitude of i in (t), and T in is the period of i in (t) and v b (t). Impedance spectrum is obtained by using the FRA method, which analyzes one frequency at a time, repeatedly with sweeping the frequency [9]. Figure 2 shows the phase measurement scheme adopted in polar demodulators [10,11,[15][16][17]. When i in (t) is injected into the target material and reference resistor, v r (t) with the same phase as i in (t) is generated from the resistor in addition to v b (t). Comparators convert v r (t) and v b (t) to clock signals, φ r and φ b , from which an XOR gate and an SR latch create clock signals, φ XOR and φ SR , respectively. These clock signals have the pulse width of T b , which corresponds to θ, as shown in Figure 2. From Equation (2), when the frequency of the injected current, f in = 1/T in is known, θ can be determined by measuring T b .  [19] with permission from the IEEE).

Design Specifications
Design specifications of TDC proposed in this paper are presented in Table 1. fin is set from 1 kHz to 2.048 MHz because the proposed TDC is implemented in the form of a fully integrated chip for EIS systems in biomedical applications. Considering that the impedance measured in such applications [15] usually has capacitive reactance, θ ranges from 0° to 90°, and the corresponding input-time range is 0 to 122 ns at the shortest when fin is 2.048 MHz and 0 to 250 s at the widest when fin is 1 kHz. Referring to performances of the previous works reported in [15,17], this TDC aims to have maximum phase error under 1° and phase resolution over 10 bits for the suggested range of fin. This amount of phase error corresponds to 1.35 ns in the worst case when fin is 2.048 MHz. Lastly, the frequency of the reference clock (fclk) is set to 32.768 MHz, which is only 16 times the maximum fin. Compared to the TDC in [17], where fclk is 330 times higher than the maximum fin, the proposed TDC aims to achieve competitive phase error performance with much lower fclk.

Architecture of the Proposed TDC
As shown in Table 1, the requirements of both the input-time range and time resolution vary with fin. The proposed TDC operates across three different modes to meet the design specifications with maintaining reasonable measurement time. This section describes overall architecture and operation in each mode.

Overall Architecture and Operation
The block diagram of the proposed TDC is presented in Figure 3. The input pulse signal whose pulse width carries θ is denoted as in. clk is the reference clock, and the outputs of the system are the digital bits, Dc, Df1, and Df2. This TDC is composed of three stages, namely a coarse stage, the first fine stage, and the second fine stage. The coarse stage consists of a 12-bit coarse counter with digital logics. Each fine stage consists of a time splitter, a reconfigurable time interpolator, and a 4-bit counter. The coarse counter is used to implement a wide input-time range, and two fine stages are employed to  [19] with permission from the IEEE).

Design Specifications
Design specifications of TDC proposed in this paper are presented in Table 1. f in is set from 1 kHz to 2.048 MHz because the proposed TDC is implemented in the form of a fully integrated chip for EIS systems in biomedical applications. Considering that the impedance measured in such applications [15] usually has capacitive reactance, θ ranges from 0 • to 90 • , and the corresponding input-time range is 0 to 122 ns at the shortest when f in is 2.048 MHz and 0 to 250 µs at the widest when f in is 1 kHz. Referring to performances of the previous works reported in [15,17], this TDC aims to have maximum phase error under 1 • and phase resolution over 10 bits for the suggested range of f in . This amount of phase error corresponds to 1.35 ns in the worst case when f in is 2.048 MHz. Lastly, the frequency of the reference clock (f clk ) is set to 32.768 MHz, which is only 16 times the maximum f in . Compared to the TDC in [17], where f clk is 330 times higher than the maximum f in , the proposed TDC aims to achieve competitive phase error performance with much lower f clk .

Architecture of the Proposed TDC
As shown in Table 1, the requirements of both the input-time range and time resolution vary with f in . The proposed TDC operates across three different modes to meet the design specifications with maintaining reasonable measurement time. This section describes overall architecture and operation in each mode.

Overall Architecture and Operation
The block diagram of the proposed TDC is presented in Figure 3. The input pulse signal whose pulse width carries θ is denoted as φ in . φ clk is the reference clock, and the outputs of the system are the digital bits, D c , D f1 , and D f2 . This TDC is composed of three stages, namely a coarse stage, the first fine stage, and the second fine stage. The coarse stage consists of a 12-bit coarse counter with digital logics. Each fine stage consists of a time splitter, a reconfigurable time interpolator, and a 4-bit counter. The coarse counter is used to implement a wide input-time range, and two fine stages are employed to improve resolution without increasing f clk . In each fine stage, the time splitter extracts quantization error of the preceding stage and the time interpolator stretches the quantization error. The resolution can be improved by quantizing the stretched quantization error through the fine counters and φ clk .  Figure 3. Block diagram of the proposed TDC (reproduced from [18] with permission from the IEEE).
The proposed TDC operates in one of the three modes to achieve the phase resolution over 10 bits. In mode A, only the coarse stage is used, and the time resolution is Tclk. For low fin of 1 kHz and 2 kHz, fclk is high enough to achieve target phase resolution. For 4-kHz fin upwards, the fine stages are used with the coarse stage to further improve the time resolution without increasing fclk. In mode B, the coarse stage and the first fine stage are used for fin from 4 kHz to 32 kHz. The first fine stage further quantizes the quantization error of the coarse stage with a time interpolation factor of AT1. The time resolution in mode B is Tclk/AT1, which is AT1 times higher than the highest resolution in mode A while keeping fclk = 32.768 MHz. In mode C, for 32-kHz fin upwards, the coarse stage and the first fine stage operate in the same manner. In addition, the second fine stage further quantizes the quantization error of the first fine stage. The time resolution in mode C is Tclk/(AT1AT2), which is AT1AT2 times higher than the highest one in mode A, still keeping fclk = 32.768 MHz. When fin = 2.048 MHz, the coarse stage only achieves a 2-bit resolution for θ range from 0° to 90° with fclk = 32.768 MHz. Therefore, the total interpolation factor (AT) of up to 256 is required to achieve a 10-bit resolution for the whole fin range. AT1 and AT2 are set, as shown in Table 2, across three different modes, A, B, and C, for varying values of fin.  The proposed TDC operates in one of the three modes to achieve the phase resolution over 10 bits. In mode A, only the coarse stage is used, and the time resolution is T clk . For low f in of 1 kHz and 2 kHz, f clk is high enough to achieve target phase resolution. For 4-kHz f in upwards, the fine stages are used with the coarse stage to further improve the time resolution without increasing f clk . In mode B, the coarse stage and the first fine stage are used for f in from 4 kHz to 32 kHz. The first fine stage further quantizes the quantization error of the coarse stage with a time interpolation factor of A T1 . The time resolution in mode B is T clk /A T1 , which is A T1 times higher than the highest resolution in mode A while keeping f clk = 32.768 MHz. In mode C, for 32-kHz f in upwards, the coarse stage and the first fine stage operate in the same manner. In addition, the second fine stage further quantizes the quantization error of the first fine stage. The time resolution in mode C is T clk /(A T1 A T2 ), which is A T1 A T2 times higher than the highest one in mode A, still keeping f clk = 32.768 MHz. When f in = 2.048 MHz, the coarse stage only achieves a 2-bit resolution for θ range from 0 • to 90 • with f clk = 32.768 MHz. Therefore, the total interpolation factor (A T ) of up to 256 is required to achieve a 10-bit resolution for the whole f in range. A T1 and A T2 are set, as shown in Table 2, across three different modes, A, B, and C, for varying values of f in . When utilizing the time interpolator, A T is determined by the ratio of discharging capacitance and discharging current [20]. If the current increases for implementing a large A T , the power consumption of TDC increases accordingly. Moreover, since the pulse width of the interpolated signal increases, the conversion time increases significantly, which leads to the degraded conversion rate. Thus, the large A T is realized in two steps by dividing A T into A T1 and A T2 to offer much more relaxed design conditions. A T1 and A T2 can be adjusted between 2, 4, 8, and 16 to provide 1, 2, 3, and 4 additional bits, respectively. Reconfigurable A T1 and A T2 maintain the phase resolution over 10 bits with reasonably short measurement time.

Operation in Mode A
This mode offers only counter-based time quantization, and the timing diagram of its operation is depicted in Figure 4. When utilizing the time interpolator, AT is determined by the ratio of discharging capacitance and discharging current [20]. If the current increases for implementing a large AT, the power consumption of TDC increases accordingly. Moreover, since the pulse width of the interpolated signal increases, the conversion time increases significantly, which leads to the degraded conversion rate. Thus, the large AT is realized in two steps by dividing AT into AT1 and AT2 to offer much more relaxed design conditions. AT1 and AT2 can be adjusted between 2, 4, 8, and 16 to provide 1, 2, 3, and 4 additional bits, respectively. Reconfigurable AT1 and AT2 maintain the phase resolution over 10 bits with reasonably short measurement time.

Operation in Mode A
This mode offers only counter-based time quantization, and the timing diagram of its operation is depicted in Figure 4.  The proposed TDC in mode A outputs digital bits Dc with the relation as follows: where q,c is the quantization error of the coarse stage and smaller than clk. The time resolution in mode A becomes one period of the clock signal, Tclk. To achieve a 12-bit phase resolution for θ range from 0° to 90° at low fin, this mode is used for fin of up to 2 kHz.

Operation in Mode B
Mode B uses the coarse stage and the first fine stage, each generating output digital bits, Dc and Df1, respectively. The timing diagram of its operation is presented in Figure 5.
The pulse width of Tf1 is generated by the time splitter in the first fine stage and expressed as follows: The time interpolator in the first stage stretches Tf1 to Tint1, which is described by:  The proposed TDC in mode A outputs digital bits D c with the relation as follows: where T q,c is the quantization error of the coarse stage and smaller than T clk . The time resolution in mode A becomes one period of the clock signal, T clk . To achieve a 12-bit phase resolution for θ range from 0 • to 90 • at low f in , this mode is used for f in of up to 2 kHz.

Operation in Mode B
Mode B uses the coarse stage and the first fine stage, each generating output digital bits, D c and D f1 , respectively. The timing diagram of its operation is presented in Figure 5.
When utilizing the time interpolator, AT is determined by the ratio of discharging capacitance and discharging current [20]. If the current increases for implementing a large AT, the power consumption of TDC increases accordingly. Moreover, since the pulse width of the interpolated signal increases, the conversion time increases significantly, which leads to the degraded conversion rate. Thus, the large AT is realized in two steps by dividing AT into AT1 and AT2 to offer much more relaxed design conditions. AT1 and AT2 can be adjusted between 2, 4, 8, and 16 to provide 1, 2, 3, and 4 additional bits, respectively. Reconfigurable AT1 and AT2 maintain the phase resolution over 10 bits with reasonably short measurement time.

Operation in Mode A
This mode offers only counter-based time quantization, and the timing diagram of its operation is depicted in Figure 4. The proposed TDC in mode A outputs digital bits Dc with the relation as follows: where q,c is the quantization error of the coarse stage and smaller than clk. The time resolution in mode A becomes one period of the clock signal, Tclk. To achieve a 12-bit phase resolution for θ range from 0° to 90° at low fin, this mode is used for fin of up to 2 kHz.

Operation in Mode B
Mode B uses the coarse stage and the first fine stage, each generating output digital bits, Dc and Df1, respectively. The timing diagram of its operation is presented in Figure 5.
The pulse width of Tf1 is generated by the time splitter in the first fine stage and expressed as follows: The time interpolator in the first stage stretches Tf1 to Tint1, which is described by:  The pulse width of T f1 is generated by the time splitter in the first fine stage and expressed as follows: Sensors 2020, 20, 1889 The time interpolator in the first stage stretches T f1 to T int1 , which is described by: The fine counter quantizes T int1 with the reference clock, to output up to four fine digital bits, D f1 . The relation among T b , D c , and D f1 is given by: where T q,f1 /A T1 is always smaller than T clk . The time resolution in mode B is improved from T clk to T clk /A T1 , which is A T1 times higher than the highest resolution in mode A while keeping f clk = 32.768 MHz.
To achieve a 12-bit phase resolution for θ range from 0 • to 90 • , f in must satisfy the following condition: With the maximum A T1 of 16, this mode is used until f in increases up to 32 kHz.

Operation in Mode C
The mode C uses the coarse stage, the first fine stage, and the second fine stage, each generating output digital bits, D c , D f1 , and D f2 , respectively. The timing diagram of its operation is presented in Figure 6. The fine counter quantizes Tint1 with the reference clock, to output up to four fine digital bits, Df1. The relation among Tb, Dc, and Df1 is given by: c  clk  clk  c  clk  clk  TT   D T  T  T  T T  T  T  D T  T  D T  T  AA   -    = --=    --=    --        (6) where q,f1/AT1 is always smaller than clk. The time resolution in mode B is improved from Tclk to Tclk/AT1, which is AT1 times higher than the highest resolution in mode A while keeping fclk = 32.768 MHz.
To achieve a 12-bit phase resolution for θ range from 0° to 90°, fin must satisfy the following condition: With the maximum AT1 of 16, this mode is used until fin increases up to 32 kHz.

Operation in Mode C
The mode C uses the coarse stage, the first fine stage, and the second fine stage, each generating output digital bits, Dc, Df1, and Df2, respectively. The timing diagram of its operation is presented in Figure 6.
The coarse stage and the first fine stage operate in the same manner as in mode B. The time splitter in the second stage generates Tf2, which is expressed as: The time interpolator in the second stage stretches Tf2 to Tint2, which is described by: The fine counter in the second fine stage quantizes Tint2 with the reference clock, to output up to four fine digital bits, D2. The relation among Tb, Dc, Df1, and Df2 is given by: The coarse stage and the first fine stage operate in the same manner as in mode B. The time splitter in the second stage generates T f2 , which is expressed as: The time interpolator in the second stage stretches T f2 to T int2 , which is described by: Sensors 2020, 20, 1889 The fine counter in the second fine stage quantizes T int2 with the reference clock, to output up to four fine digital bits, D 2 . The relation among T b , D c , D f1 , and D f2 is given by: where T q,f2 /(A T1 A T2 ) is always smaller than T clk . The time resolution in mode C is improved from T clk to T clk /(A T1 A T2 ), which is A T1 A T2 times higher than the highest resolution in mode A, even though f clk = 32.768 MHz is kept. To achieve a 10-bit phase resolution for θ range from 0 • to 90 • , f in must satisfy the following condition: with the maximum A T1 and A T2 of 16, this mode is used for f in of up to 2.048 MHz.

Circuit Design
This section describes how the first fine stage is designed to realize time interpolation with reconfigurable A T1 . The second fine stage is designed to be identical to the first one. Figure 7 shows the structure of the time splitter, which consists of three D flip-flops and one NOR gate. As shown in Figures 5 and 6, the time splitter extracts the quantization error of the coarse stage with an offset of T clk . This offset is employed to avoid the metastability issue of the D flip-flops [20]. Therefore, T f1 takes the value from T clk to 2T clk , corresponding to 30.52 ns to 61.04 ns. As shown in Equations (6) and (10), in mode B and C, the offset is compensated when T b is calculated from the digital outputs.

Time Splitter
Sensors 2020, 20, x FOR PEER REVIEW 8 of 18 where q,f2/(AT1AT2) is always smaller than clk. The time resolution in mode C is improved from Tclk to Tclk/(AT1AT2), which is AT1AT2 times higher than the highest resolution in mode A, even though fclk = 32.768 MHz is kept. To achieve a 10-bit phase resolution for θ range from 0° to 90°, fin must satisfy the following condition: 10 12 1 90 1 .
with the maximum AT1 and AT2 of 16, this mode is used for fin of up to 2.048 MHz.

Circuit Design
This section describes how the first fine stage is designed to realize time interpolation with reconfigurable AT1. The second fine stage is designed to be identical to the first one. Figure 7 shows the structure of the time splitter, which consists of three D flip-flops and one NOR gate. As shown in Figures 5 and 6, the time splitter extracts the quantization error of the coarse stage with an offset of Tclk. This offset is employed to avoid the metastability issue of the D flip-flops [20]. Therefore, Tf1 takes the value from Tclk to 2Tclk, corresponding to 30.52 ns to 61.04 ns. As shown in Equations (6) and (10), in mode B and C, the offset is compensated when Tb is calculated from the digital outputs. Figure 7. Structure of the time splitter (reproduced from [18] with permission from the IEEE). Figure 8 shows the block diagram and timing diagram of the reconfigurable time interpolator. The reconfigurable time interpolator is similar to the time interpolator in [20]. A variable discharging capacitor, which has the capacitance of CINT, is added to obtain reconfigurable AT1.  Figure 8 shows the block diagram and timing diagram of the reconfigurable time interpolator. The reconfigurable time interpolator is similar to the time interpolator in [20]. A variable discharging capacitor, which has the capacitance of C INT , is added to obtain reconfigurable A T1 .

Reconfigurable Time Interpolator
While φ f1 , which has the pulse width of T f1 , is high, a capacitor which has the capacitance of C F is discharged by a constant current, I F , such that v 1 (t) drops by ∆V. ∆V is expressed as follows: From the falling edge of φ f1 , a capacitor of C INT is discharged by a constant current, I INT , during φ f1,q is high. In the same manner with Equation (12), the pulse width of φ f1,q is expressed as follows: where M is the capacitance ratio, C INT /C F , N is the current ratio, I F /I INT , and A T1 is M·N.
In the proposed TDC, N is kept constant while M is controlled to change A T1 between 2, 4, 8, and 16. Adjustment of the capacitance value is selected over the current value because controlling the capacitance ratio is more accurate than controlling the current ratio in IC implementation. In each fine stage, since N is fixed to 2, C F is kept constant as 3.6 pF, and C INT is changed across 3.6 pF, 7.  Figure 8. Block diagram and timing diagram of the reconfigurable time interpolator (reproduced from [18] with permission from the IEEE).
While f1, which has the pulse width of Tf1, is high, a capacitor which has the capacitance of CF is discharged by a constant current, IF, such that v1(t) drops by DV. DV is expressed as follows: From the falling edge of f1, a capacitor of CINT is discharged by a constant current, IINT, during f1,q is high. In the same manner with Equation (12), the pulse width of f1,q is expressed as follows: ( ) where M is the capacitance ratio, CINT/CF, N is the current ratio, IF/IINT, and AT1 is M· N.
In the proposed TDC, N is kept constant while M is controlled to change AT1 between 2, 4, 8, and 16. Adjustment of the capacitance value is selected over the current value because controlling the capacitance ratio is more accurate than controlling the current ratio in IC implementation. In each fine stage, since N is fixed to 2, CF is kept constant as 3.6 pF, and CINT is changed across 3.6 pF, 7.2 pF, 14.4 pF, and 28.8 pF. IF and IINT are 80 A and 40 A, respectively.

Novel Features of the Proposed TDC
The proposed TDC employs time interpolation technique, which can improve time resolution without increasing fclk in the counter-based TDC. However, two inherent issues are associated with large AT. Although the resolution becomes much higher when the front-stage quantization error is interpolated with AT, the chip size or power consumption increases by a substantial amount because AT is determined by capacitance ratio or current ratio. Also, the conversion time increases significantly because the interpolated pulse width increases as AT increases. A novel structure of cascading two separate fine stages resolves these two issues at the same time.
When AT of 256 is obtained by using a single-stage time interpolator with CF of 1 pF and CINT of 256 pF, this results in excessively large chip size and poor area efficiency. In the proposed TDC, two interpolation stages are cascaded. As a result, the interpolation factor of only 16 is required in each stage instead of 256. In other words, this system requires two capacitors with the size of CINT, which

Novel Features of the Proposed TDC
The proposed TDC employs time interpolation technique, which can improve time resolution without increasing f clk in the counter-based TDC. However, two inherent issues are associated with large A T . Although the resolution becomes much higher when the front-stage quantization error is interpolated with A T , the chip size or power consumption increases by a substantial amount because A T is determined by capacitance ratio or current ratio. Also, the conversion time increases significantly because the interpolated pulse width increases as A T increases. A novel structure of cascading two separate fine stages resolves these two issues at the same time.
When A T of 256 is obtained by using a single-stage time interpolator with C F of 1 pF and C INT of 256 pF, this results in excessively large chip size and poor area efficiency. In the proposed TDC, two interpolation stages are cascaded. As a result, the interpolation factor of only 16 is required in each stage instead of 256. In other words, this system requires two capacitors with the size of C INT , which is equal to 16 C F . Compared to the single stage with A T of 256, this approach reduces the area used for implementing the discharging capacitors by a factor of 257/34 =~7.6 times considering that one time interpolator has two discharging capacitors with the sizes of C INT and C F . As the time interpolators in fine stages occupy a significant portion of the chip size, the area efficiency of the system is greatly improved. On the other hand, when A T of 256 is set by the capacitance ratio, the current consumption of the cascaded time interpolation stages is two times higher than that of the single-stage time interpolator. For the single interpolator with A T of 256, from the falling edge of φ c , the conversion time of A T T f1 is required for fine conversion, and the maximum conversion time is 2A T T clk considering the offset of the time splitter. For two cascaded interpolation stages with A T1 and A T2 of 16, the conversion time of each fine stage is A T1 T f1 or A T2 T f1 , and the maximum conversion time of each stage is 2A T1 T clk or 2A T2 T clk . Compared to the single interpolator with A T of 256, when A T1 = A T2 = 16, the conversion time for fine conversion is reduced by approximately 8 times.
When N f of time interpolation stages are cascaded and A T is set by the capacitance ratio, the area efficiency (E A ), power efficiency (E P ), and conversion-time efficiency for fine stages (E C ) can be defined and expressed as follows: Total capacitance in an interpolation stage when N f = 1 Total capacitance in interpolation stages when E P = The current consumption of an interpolation stage when N f = 1 The current consumption of interpolation stages when The max. conversion time through a fine stage when N f = 1 The max. conversion time through fine stages when N f > 1 where I fine is the current consumption of a single time interpolation stage. Table 3 summarizes E A , E P , and E C calculated using Equations (14)- (16). Although the maximum E A ·E P ·E C value is obtained when N f = 4, we chose N f = 2 to minimize the current consumption while taking advantages of the cascaded time interpolators in terms of area and conversion time. The largest capacitor with size of 28.8 pF is small enough to integrate on chip and 2A T1 T clk =~1 µs of conversion time for the fine stage is short enough. It is also possible to obtain A T through the current ratio of I F /I INT in Figure 8. In this case, setting the current ratio to 256 directly affects the static power, severely degrading the power efficiency of the system. Total discharging current of cascaded time interpolation stages when N f = 2 could be 7.6-times smaller than that of a single time interpolation stage when N f = 1, and the total capacitance of cascaded time interpolation stages when N f = 2 could be two times larger than that of a single time interpolation stage when N f = 1. Compared to the single interpolator with A T of 256 and N f = 1, when N f = 2, the time for fine conversion is reduced by approximately eight times. The optimization process when A T is set by the current ratio would be similar to that when A T is set by the capacitance ratio.

Measurement Results
The proposed TDC has been fabricated with a 0.25-µm CMOS process. The size of the circuit is 787 µm × 524 µm (0.412 mm 2 ). The chip photograph and layout of the fabricated IC are presented in Figure 9.   Figure 10 shows the measurement setup. Two Agilent 33250A function generators are used, one for generating φ clk and another for generating φ in whose pulse width varies from 0 to 0.25 of the period which corresponds to the phase of 0 • to 90 • . These two function generators are synchronized with each other. In the case of generating φ in in the form of pulse train, the period can be adjusted from 20.00 ns to 2000.0 s, and its pulse width can be controlled from 8.0 ns to 1999.9 s. Therefore, when f in = 2.048 MHz, the phase above 5.9 • could be measured. Arduino DUE was selected for a microcontroller unit because it has 54 digital I/O pins which are enough for receiving digital output bits and transmitting assignment codes through SPI for the reconfiguration of TDC. Moreover, its clock speed of 84 MHz allows generating required signals to initialize the SPI communication and select between the read and write modes. Monitoring pads are placed on the main propagation path of signal to examine whether each block and each stage operate as expected. Keysight Technologies DSO7104A oscilloscope was used throughout the measurement. The oscilloscope has enough sample rate of 4 Gsps, bandwidth of 1 GHz, and four scope channels.  Figure 10 shows the measurement setup. Two Agilent 33250A function generators are used, one for generating clk and another for generating in whose pulse width varies from 0 to 0.25 of the period which corresponds to the phase of 0° to 90°. These two function generators are synchronized with each other. In the case of generating in in the form of pulse train, the period can be adjusted from 20.00 ns to 2000.0 s, and its pulse width can be controlled from 8.0 ns to 1999.9 s. Therefore, when fin = 2.048 MHz, the phase above 5.9° could be measured. Arduino DUE was selected for a microcontroller unit because it has 54 digital I/O pins which are enough for receiving digital output bits and transmitting assignment codes through SPI for the reconfiguration of TDC. Moreover, its clock speed of 84 MHz allows generating required signals to initialize the SPI communication and select between the read and write modes. Monitoring pads are placed on the main propagation path of signal to examine whether each block and each stage operate as expected. Keysight Technologies DSO7104A oscilloscope was used throughout the measurement. The oscilloscope has enough sample rate of 4 Gsps, bandwidth of 1 GHz, and four scope channels.
In this section, measurement results for one frequency in mode A, one in mode B, and one in mode C are shown. The input-output characteristics of the fabricated TDC are described in Figures  11a, 12a, and 13a. Figures 11b, 12b, and 13b Figure 10. Measurement setup.

Mode A
Measurement results for fin = 1 kHz are shown in Figure 11. Only the coarse stage is used, and the TDC operates as a counter-based TDC with fclk = 16.384 MHz, halved from the 32.768-MHz clock signal provided by the function generator. The input-output characteristic of the TDC is shown in Figure 11a, where the horizontal axis indicates the pulse width of the input signal in seconds, and the vertical axis shows the TDC output code in units of LSB. The solid line represents theoretical output values for given pulse widths of the input. Figure 11b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0005°, which corresponds to about 1.4 ns. The difference between the maximum In this section, measurement results for one frequency in mode A, one in mode B, and one in mode C are shown. The input-output characteristics of the fabricated TDC are described in Figures 11a,  12a and 13a. Figures 11b, 12b and 13b present the phase errors in each frequency.

Mode A
Measurement results for f in = 1 kHz are shown in Figure 11. Only the coarse stage is used, and the TDC operates as a counter-based TDC with f clk = 16.384 MHz, halved from the 32.768-MHz clock signal provided by the function generator. The input-output characteristic of the TDC is shown in Figure 11a, where the horizontal axis indicates the pulse width of the input signal in seconds, and the vertical axis shows the TDC output code in units of LSB. The solid line represents theoretical output values for given pulse widths of the input. Figure 11b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0005 • , which corresponds to about 1.4 ns. The difference between the maximum and minimum phase errors is about 0.022 • , implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0 • to 90 • and that the TDC operates as expected.
Sensors 2020, 20, x FOR PEER REVIEW 12 of 18 and minimum phase errors is about 0.022°, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0° to 90° and that the TDC operates as expected.

Mode B
Measurement results for fin = 8 kHz are shown in Figure 12. The coarse stage and the first fine stage are used with fclk = 32.768 MHz and AT1 = 4. However, AT1 of 4.05 is obtained from the measured Tint1 and Tf1, and this value is substituted to Equation (6) to derive Tb using output code. The inputoutput characteristic of the TDC is shown in Figure 12a, where the horizontal axis, vertical axis, and solid line are as described in Figure 11a. Figure 12b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0003°, which corresponds to 0.1 ns. The peak-to-peak phase error is about 0.022°, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0° to 90°. This result shows a good agreement with the theoretical prediction.

Mode C
Measurement results for fin = 2.048 MHz are shown in Figure 13. For fin = 2.048 MHz, AT1 and AT2 are both set to 16 to achieve the largest AT of 256. However, AT1 of 15.9 and AT2 of 15.9 are obtained, and these values are substituted to Equation (10) to derive Tb using output code. The input-output characteristic of the TDC is shown in Figure 13a, where the horizontal axis, vertical axis, and the solid

Mode B
Measurement results for f in = 8 kHz are shown in Figure 12. The coarse stage and the first fine stage are used with f clk = 32.768 MHz and A T1 = 4. However, A T1 of 4.05 is obtained from the measured T int1 and T f1 , and this value is substituted to Equation (6) to derive T b using output code. The input-output characteristic of the TDC is shown in Figure 12a, where the horizontal axis, vertical axis, and solid line are as described in Figure 11a. Figure 12b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0003 • , which corresponds to 0.1 ns. The peak-to-peak phase error is about 0.022 • , implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0 • to 90 • . This result shows a good agreement with the theoretical prediction.
Sensors 2020, 20, x FOR PEER REVIEW 12 of 18 and minimum phase errors is about 0.022°, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0° to 90° and that the TDC operates as expected.

Mode B
Measurement results for fin = 8 kHz are shown in Figure 12. The coarse stage and the first fine stage are used with fclk = 32.768 MHz and AT1 = 4. However, AT1 of 4.05 is obtained from the measured Tint1 and Tf1, and this value is substituted to Equation (6) to derive Tb using output code. The inputoutput characteristic of the TDC is shown in Figure 12a, where the horizontal axis, vertical axis, and solid line are as described in Figure 11a. Figure 12b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0003°, which corresponds to 0.1 ns. The peak-to-peak phase error is about 0.022°, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0° to 90°. This result shows a good agreement with the theoretical prediction.

Mode C
Measurement results for fin = 2.048 MHz are shown in Figure 13. For fin = 2.048 MHz, AT1 and AT2 are both set to 16 to achieve the largest AT of 256. However, AT1 of 15.9 and AT2 of 15.9 are obtained, and these values are substituted to Equation (10) to derive Tb using output code. The input-output characteristic of the TDC is shown in Figure 13a, where the horizontal axis, vertical axis, and the solid

Mode C
Measurement results for f in = 2.048 MHz are shown in Figure 13. For f in = 2.048 MHz, A T1 and A T2 are both set to 16 to achieve the largest A T of 256. However, A T1 of 15.9 and A T2 of 15.9 are obtained, and these values are substituted to Equation (10) to derive T b using output code. The input-output characteristic of the TDC is shown in Figure 13a, where the horizontal axis, vertical axis, and the solid line are as described in Figure 11a. Figure 13b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.07 • , which corresponds to 0.1 ns. The peak positive phase error is 1.123 • , and the peak negative phase error is −1.846 • , resulting in the peak-to-peak phase error of 2.969 • . This phase error is beyond the target quantization error of 0.088 • and target phase error of 1 • . The error analysis for the mode-C operation is presented in the next sub-section with a summary of the measurement results.
Sensors 2020, 20, x FOR PEER REVIEW 13 of 18 line are as described in Figure 11a. Figure 13b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.07°, which corresponds to 0.1 ns. The peak positive phase error is 1.123°, and the peak negative phase error is -1.846°, resulting in the peak-to-peak phase error of 2.969°. This phase error is beyond the target quantization error of 0.088° and target phase error of 1°. The error analysis for the mode-C operation is presented in the next sub-section with a summary of the measurement results.

Error Analysis
The peak-to-peak phase error and corresponding time error for fin from 1 kHz to 2.048 MHz are described in Figure 14. The peak-to-peak phase error is proportional to fin and exceeds 1° for only when fin = 1.024 MHz and fin = 2.048 MHz.  Table 4 summarizes the exact values of the peak-to-peak phase error and corresponding time error as a function of fin. It also shows the values of AT1 and AT2 set for the measurement. Although AT2 increases, the corresponding time error does not decrease below 1.06 ns.

Error Analysis
The peak-to-peak phase error and corresponding time error for f in from 1 kHz to 2.048 MHz are described in Figure 14. The peak-to-peak phase error is proportional to f in and exceeds 1 • for only when f in = 1.024 MHz and f in = 2.048 MHz.
Sensors 2020, 20, x FOR PEER REVIEW 13 of 18 line are as described in Figure 11a. Figure 13b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.07°, which corresponds to 0.1 ns. The peak positive phase error is 1.123°, and the peak negative phase error is -1.846°, resulting in the peak-to-peak phase error of 2.969°. This phase error is beyond the target quantization error of 0.088° and target phase error of 1°. The error analysis for the mode-C operation is presented in the next sub-section with a summary of the measurement results.

Error Analysis
The peak-to-peak phase error and corresponding time error for fin from 1 kHz to 2.048 MHz are described in Figure 14. The peak-to-peak phase error is proportional to fin and exceeds 1° for only when fin = 1.024 MHz and fin = 2.048 MHz.  Table 4 summarizes the exact values of the peak-to-peak phase error and corresponding time error as a function of fin. It also shows the values of AT1 and AT2 set for the measurement. Although AT2 increases, the corresponding time error does not decrease below 1.06 ns.  Table 4 summarizes the exact values of the peak-to-peak phase error and corresponding time error as a function of f in . It also shows the values of A T1 and A T2 set for the measurement. Although A T2 increases, the corresponding time error does not decrease below 1.06 ns. These extra errors would come from the uncertainty of comparator operation in time interpolators. The schematic of comparators and the uncertainty caused by the comparator operation during time interpolation are shown in Figure 15a,b, respectively. The comparators are designed by cascading two self-biased inverters as in [21,22]. These extra errors would come from the uncertainty of comparator operation in time interpolators. The schematic of comparators and the uncertainty caused by the comparator operation during time interpolation are shown in Figure 15a, b, respectively. The comparators are designed by cascading two self-biased inverters as in [21] and [22].

Fully-differential self-biased inverter [21]
Differential-to-single-ended self-biased inverter [22] Dv comp As shown in Figure 15b, if there is a voltage-domain uncertainty of Dvcomp when v1(t) and v2(t) cross each other, Dvcomp causes a time-domain uncertainty of Dtcomp, which is given by:

Region of uncertainty
Therefore, Dvcomp should be minimized in order to reduce Dtcomp and hence extra time errors. The finite resolution and noise of the comparator would cause the uncertainty in the voltage domain, which, in turn, is translated into the uncertainty in the time domain.
The resolution of the comparator (Dvmin,comp), which means the minimum input difference that saturates the output, is expressed as follows [23]: where Av0 is the open-loop gain of the comparator, VOH is the output voltage when the output is high, and VOL is the output voltage when the output is low. VOH and VOL should be large and small enough, respectively, so that the following digital logic can distinguish binary states. That is, when the transient behavior of v1(t) and v2(t) is not fast enough or Av0 is not sufficiently large, the comparator suffers from a substantial uncertainty in time domain (Dtcomp) because it will take relatively longer time for the following digital logic to determine binary states.
Considering that Tf1 and Tf2 vary within the range from Tclk to 2Tclk, the crossing point of v1(t) and v2(t) in Figure 15b (17). This Dtcomp in the first fine stage is divided by AT1 after being quantized by the fine counter. Therefore, the fabricated TDC could not achieve the time error below 0.92 ns. As shown in Figure 15b, if there is a voltage-domain uncertainty of ∆v comp when v 1 (t) and v 2 (t) cross each other, ∆v comp causes a time-domain uncertainty of ∆t comp , which is given by: Therefore, ∆v comp should be minimized in order to reduce ∆t comp and hence extra time errors. The finite resolution and noise of the comparator would cause the uncertainty in the voltage domain, which, in turn, is translated into the uncertainty in the time domain.
The resolution of the comparator (∆v min,comp ), which means the minimum input difference that saturates the output, is expressed as follows [23]: where A v0 is the open-loop gain of the comparator, V OH is the output voltage when the output is high, and V OL is the output voltage when the output is low. V OH and V OL should be large and small enough, respectively, so that the following digital logic can distinguish binary states. That is, when the transient behavior of v 1 (t) and v 2 (t) is not fast enough or A v0 is not sufficiently large, the comparator suffers from a substantial uncertainty in time domain (∆t comp ) because it will take relatively longer time for the following digital logic to determine binary states.
Considering that T f1 and T f2 vary within the range from T clk to 2T clk , the crossing point of v 1 (t) and v 2 (t) in Figure 15b falls within the voltage range from 0.9 V to 1.4 V. In this voltage range, A v0 varies between 41.8 dB and 58.0 dB depending on the voltage level where v 1 (t) and v 2 (t) intersect.
From A v0 = 41.8 dB and supply voltage of 2.5 V, ∆v min,comp is about 20.3 mV. For f in = 128 kHz with A T1 = 15.9 and A T2 = 4.05, ∆t comp in the first stage caused by ∆v min,comp is calculated as about 14.6 ns by substituting C INT = 28.8 pF and I INT = 40 µA into Equation (17). This ∆t comp in the first fine stage is divided by A T1 after being quantized by the fine counter. Therefore, the fabricated TDC could not achieve the time error below 0.92 ns.
The noise of comparator would become another source of uncertainty. The input-referred noise voltage of the differential-to-single-ended self-biased inverter in Figure 15a is expressed as follows [24]: where W P and L P are the width and length of the input PMOS transistor, respectively, while W N and L N are the width and length of the input NMOS transistor, respectively. K is the process-dependent flicker noise constant. g m,N and g m,P are the transconductances of the NMOS and PMOS input transistors, respectively. The input-referred noise of the fully differential self-biased inverter is also given by Equation (19).
Since the noise of the first stage is dominant compared to that of the second stage and the 1/f noise can be ignored because of the wide bandwidth of the comparator, the input-referred noise voltage of the comparator can be approximated as follows: When T = 300 K, γ = 1, and noise bandwidth = 100 MHz, the input-referred noise of the comparator is about 1.8 mV rms , 180 µV rms , and 18 µV rms for g m,N + g m,P = 1 µS, g m,N + g m,P = 10 µS, g m,N + g m,P = 100 µS, respectively. Since our TDC consumes enough current, the uncertainty due to the comparator noise is not significant in our design. However, if the bandwidth of the comparator is very large and g m,N + g m,P is small, considerable uncertainties may occur. For f in = 128 kHz with A T1 = 15.9 and A T2 = 4.05, the voltage-domain uncertainty of 1.8 mV rms causes ∆t comp = 1.3 ns rms , which corresponds to the time error of 0.08 ns rms . In particular, it is important to ensure that the value of g m,N + g m,P is sufficiently large when the bandwidth of the comparator is wide. Since the extra time errors are mainly due to the resolution of comparators, the errors would be mitigated if the comparators based on multi-stage amplifiers are used as in [15]. In such comparators, the optimum number of amplifier stages, N OPT , is expressed as follows [15]: By replacing the two-stage high-gain amplifiers with multiple stages of low-gain amplifiers, the improved ∆t comp can be obtained as ∆v min,comp is reduced. Moreover, when A T2 increases from 8 to 16, the time error increases rather than decreases. Therefore, another way of improving the extra time error is measuring the quantization error of the first stage without performing time interpolation of the second fine stage. In [19], we employed a chain delay line in the second fine stage instead of the time interpolator, and the results were verified by simulation. Since the mismatches between unit delay cells would occur, the proposed architecture needs to be verified by measurement. Table 5 summarizes performances of the presented TDC, together with those of two polar demodulators and two TDCs, reported previously. In comparison with the TDC in [20] that consists of a coarse counter and a single-stage time interpolator with large A T of 250, our TDC offers lower complexity and shorter conversion time for achieving the same phase resolution, as analyzed in Section 4.3. Compared to the TDC presented in this manuscript, another kind of our TDC in [19] seems to achieve smaller phase error. However, the TDC in [19] has not yet been verified by measurement. Through our future work, the TDC in [19] will be fabricated and measured. The phase error performance of our TDC presented in this paper is competitive when compared with previously reported designs in [15,17].

Conclusions
A reconfigurable time-to-digital converter (TDC) used to quantize the phase of impedance in electrical impedance spectroscopy (EIS) is introduced in this manuscript and verified through the fabricated IC. This TDC adopts a coarse counter to have a wide input-time range and cascaded time interpolators to improve resolution in the high-frequency analysis without increasing counting clock speed. When the same large interpolation factor is assumed, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. The reconfigurable time interpolation factor maintains phase resolution within an appropriate level while providing reasonable measurement time. The fabricated TDC achieves the peak-to-peak phase error of under 0.72 • for the input frequency range from 1 kHz to 512 kHz and the peak-to-peak phase error of 2.70 • when it covers up to 2.048 MHz, demonstrating competitive performances in comparison with previously reported designs. Two precision improvement methods are also proposed: revision of the comparator, and revision of the second fine stage. As future work, we plan to fabricate the TDC that uses chain delay lines in the second fine stage and compare it with the TDC based on cascaded time interpolators.