A Single-Chip High-Voltage Integrated Actuator for Biomedical Ultrasound Scanners †

This article presents a high-voltage (HV) pulse driver based on silicon-on-insulator (SOI) technology for biomedical ultrasound actuators and multi-channel portable imaging systems specifically. The pulse driver, which receives an external low-voltage drive signal and produces high-voltage pulses with a balanced rising and falling edge, is designed by synthesizing high-speed, capacitor-coupled level-shifters with a high-voltage H-bridge output stage. In addition, an on-chip floating power supply has also been developed to simplify powering the entire system and reduce static power consumption. The electrical and acoustic performance of the integrated eight-channel pulse driver has been verified by using medical-grade ultrasound probes to acquire the transmit/echo signals. The driver can produce pulse signals >100 Vpp with rise and fall times within 18.6 and 18.5 ns, respectively. The static power required to support the overall system is less than 3.6 mW, and the power consumption of the system during excitation is less than 50 mW per channel. The second harmonic distortion of the output pulse signal is as low as −40 dBc, indicating that the integrated multi-channel pulse driver can be used in advanced portable ultrasonic imaging systems.


Introduction
Biomedical ultrasound imaging, which is relatively fast, inexpensive, portable and radiation-free compared to computed tomography (CT), X-ray and magnetic resonance imaging (MRI), has become one of the most popular modalities for clinical examinations [1]. Currently, in addition to conventional B-mode and Doppler ultrasonic modality, tissue harmonic imaging is becoming an important medical evaluation tool for echographic medical systems because of its characteristics of easy integration into conventional ultrasound scanners and higher lateral resolution, lower side lobes, and reduced sensitivity to clutter and off-axis distortions [2][3][4]. The principle of tissue harmonic imaging is to transmit an ultrasonic wave at a certain fundamental frequency and receive an echo at the harmonics of the frequency (usually the second harmonic) that is generated by the nonlinear propagation of waves in the tissue [5]. The method needs to control the transmitter of the ultrasound scanner well, since the high-frequency harmonics generated in the ultrasonic transmitted pulses easily interfere with the harmonics generated in the tissue in the signal propagation process, degrading the image quality. In addition, the detected echo signal generated by the nonlinearity reaction of the propagating medium is easily affected by other harmonic leakages in the system, including the limited transducer

Excitation Signals for Harmonic Imaging System
Since high-voltage excitation signals such as square waves or trapezoidal waveforms can efficiently drive ultrasonic transducers, harmonic components of such waveforms need to be considered in order to achieve low harmonic output for certain applications. Given the nature of these ideal waveforms, Fourier analysis makes it easier to display their spectrums and explore the possibility of generating such waveforms [25]. In this section, the basic spectrum of the high-voltage pulse waveform is analyzed specifically from the perspective of the harmonics of the pulse wave as a design standard for the low second harmonic pulse driver. First of all, slew-rate limiting signals can reduce radiated emissions (electromagnetic interference (EMI) and radio frequency interference) and harmonics of its fundamental portion. Therefore, a digital signal, f(t), that is not an ideal square wave, but may be approximated by a trapezoidal waveform with finite rise and fall times, tr and tf, can be employed for desired output signal analysis ( Figure 1). This waveform exhibits characteristics of many other types of digital signals, including clock pulses and pulse width modulation (PWM) waveforms. In Figure 1, A stands for the amplitude of the signal, Tperiod is the signal's period and Ton and Toff represent the turn-on and turn-off periods, respectively. The waveform can be expanded in a Fourier series, as shown in Equation (1), and the expansion coefficients are given by Equation (2) [25].
C n cos(nω 0 t + ∅ cn ) (1) where To simulate the higher harmonic terms caused by unbalanced rising and falling edges, a repetitive trapezoidal waveform with a limited slew-rate and normalized −1.0 V to +1.0 V peak-to-peak voltage can be used to illustrate the effects. As shown in Equation (7), the effects of different slew-rates can be readjusted by changing the boundary conditions of each section. The simulated bipolar pulse signal with unbalanced slew-rates is plotted in Figure 2, which shows a general phenomenon when using a switching semiconductor device to generate such a waveform. These semiconductor devices typically exhibit a non-linear on-resistance, resulting in asymmetry in the rise and fall times of the output waveform. The pulses in Figure 2 assume uniform amplitude envelopes. The bandwidth of such waveforms is inversely proportional to the time duration. The center frequency of the signal is set to 2 MHz.
In Figure 2, the slew-rate difference in percentage (SRDP) of the Rising_time and Falling_time can be defined in Equation (8) as an important factor in evaluating signal harmonic leakage. In Equation (8), Rising_time and Falling_time are defined as the pulse signal responses to rise/fall from 10%/90% to 90%/10% of its final values, respectively. For n 0 and if t r = t f , the magnitudes of the Fourier coefficients, Cn, are given by From Equation (4) it can be observed that the waveform's harmonic energy at high frequencies is less than that of an ideal square wave if the tr and tf are finite. Moreover, if the pulse has equal duty cycles for the turn-on and turn-off periods, that is, and sin ( nπT on T period ) Cn is equal to zero for even n, which stands for no even harmonics when the duty cycle of the excitation pulses is 50% (this is a reasonable assumption and can be easily achieved by tweaking the duty cycles of a trapezoidal-like waveform). The value of tr in Equation (4) affects the higher-order terms of Cn. Basically, the larger the tr or tf, the lower the harmonic terms at high frequency, which, in fact, has a low-pass filtering effect. Another issue that causes excessive harmonics is due to the difference between the rising and falling edges of such signals. When deriving the spectrum of this  (4), equal tr and tf is assumed. However, even if the duty cycle is kept at 50%, large even harmonic signals still appear at the output of the pulse signals due to the inconsistency between the tr and tf.
To simulate the higher harmonic terms caused by unbalanced rising and falling edges, a repetitive trapezoidal waveform with a limited slew-rate and normalized −1.0 V to +1.0 V peak-to-peak voltage can be used to illustrate the effects. As shown in Equation (7), the effects of different slew-rates can be readjusted by changing the boundary conditions of each section. The simulated bipolar pulse signal with unbalanced slew-rates is plotted in Figure 2, which shows a general phenomenon when using a switching semiconductor device to generate such a waveform. These semiconductor devices typically exhibit a non-linear on-resistance, resulting in asymmetry in the rise and fall times of the output waveform. The pulses in Figure 2 assume uniform amplitude envelopes. The bandwidth of such waveforms is inversely proportional to the time duration. The center frequency of the signal is set to 2 MHz.
Sensors 2019, 19, 5063 5 of 22 Each of the trapezoidal waveforms shown in Figure 2 can be mixed with the impulse response of the ultrasonic transducer and subjected to Fourier analysis to obtain the harmonic amplitude of the output waveform, as shown in Figure 3. A unit-gain ultra-wideband transducer is assumed here without loss of generality. The spectral differences between the signals shown in Figure 3 have equal turn-on/turn-off times, but different rising/falling slew-rates, and it is clearly indicated that the second harmonic component of the pulse waveform changes greatly due to the unbalanced slew-rates. For instance, the desired SRDP should be less than 33% in order to keep the second harmonic signal amplitude 40 dB lower than the fundamental one. Therefore, in order to generate an excitation signal with a low second harmonic content, equal rising and falling edges of the output pulses have to be carefully coordinated for the ultrasonic actuators. In Figure 2, the slew-rate difference in percentage (SRDP) of the Rising_time and Falling_time can be defined in Equation (8)  Each of the trapezoidal waveforms shown in Figure 2 can be mixed with the impulse response of the ultrasonic transducer and subjected to Fourier analysis to obtain the harmonic amplitude of the output waveform, as shown in Figure 3. A unit-gain ultra-wideband transducer is assumed here without loss of generality. The spectral differences between the signals shown in Figure 3 have equal turn-on/turn-off times, but different rising/falling slew-rates, and it is clearly indicated that the second harmonic component of the pulse waveform changes greatly due to the unbalanced slew-rates. For instance, the desired SRDP should be less than 33% in order to keep the second harmonic signal amplitude 40 dB lower than the fundamental one. Therefore, in order to generate an excitation signal with a low second harmonic content, equal rising and falling edges of the output pulses have to be carefully coordinated for the ultrasonic actuators. Each of the trapezoidal waveforms shown in Figure 2 can be mixed with the impulse response of the ultrasonic transducer and subjected to Fourier analysis to obtain the harmonic amplitude of the output waveform, as shown in Figure 3. A unit-gain ultra-wideband transducer is assumed here without loss of generality. The spectral differences between the signals shown in Figure 3 have equal turn-on/turn-off times, but different rising/falling slew-rates, and it is clearly indicated that the second harmonic component of the pulse waveform changes greatly due to the unbalanced slew-rates. For instance, the desired SRDP should be less than 33% in order to keep the second harmonic signal amplitude 40 dB lower than the fundamental one. Therefore, in order to generate an excitation signal with a low second harmonic content, equal rising and falling edges of the output pulses have to be carefully coordinated for the ultrasonic actuators.

Single-Chip High-Voltage Driver for Biomedical Ultrasound
A biomedical ultrasound image is acquired by transmitting acoustic waves and receiving echoes that are reflected from cell boundaries [1,2]. Figure 4 shows a typical biomedical ultrasound actuator/receiver system that comprises a pulse driver, a high-voltage multiplexer (HV MUX), a transmit/receive (T/R) switch, a low noise amplifier (LNA), a variable-gain amplifier (VGA) and an analog-to-digital converter (ADC) [16][17][18]. The digital signal processor generates thousands of

Single-Chip High-Voltage Driver for Biomedical Ultrasound
A biomedical ultrasound image is acquired by transmitting acoustic waves and receiving echoes that are reflected from cell boundaries [1,2]. Figure 4 shows a typical biomedical ultrasound actuator/receiver system that comprises a pulse driver, a high-voltage multiplexer (HV MUX), a transmit/receive (T/R) switch, a low noise amplifier (LNA), a variable-gain amplifier (VGA) and an analog-to-digital converter (ADC) [16][17][18]. The digital signal processor generates thousands of properly delayed, low-voltage transmit patterns to the pulse drivers, which are converted into high-voltage signals (HV signals) to excite the transducers. These pulse-excited transducer arrays are used to generate a focused acoustic transmission. Then, due to the discontinuity of the acoustic impedance, the acoustic energy generated by the reflected wave is received by the transducer and converted into an electrical signal (LV signals) and sent to the LNA through the T/R switch. The HV MUX is designed to multiplex the transmit and receive signals to and from multiple piezoelectric transducers in the system, while the T/R switch is used to protect the LNA. When the driver is sending high-voltage transmit pulses, the LNA is isolated from the transducer by turning off the T/R switch. When the system is on the receive mode, the driver is disabled and the T/R switch is turned on. The LNA and VGA amplify the received echo signal and send the amplified signal to the ADC. The digital signal processor generates 2D and pulsed wave/color-flow Doppler information from the output data of the ADC [18]. In order to increase the strength of the echo signal, multi-channel transceivers are often indispensable in modern biomedical ultrasound systems, and they inevitably increase system complexity and power budgets. The generation of multiple high-voltage pulses, however, has been a challenge for ultrasonic imaging systems, particularly today's portable systems. In the following section, we focused on the design and implementation of an integrated high-voltage pulse driver for multi-channel biomedical ultrasound actuators.
from the output data of the ADC [18]. In order to increase the strength of the echo signal, multi-channel transceivers are often indispensable in modern biomedical ultrasound systems, and they inevitably increase system complexity and power budgets. The generation of multiple high-voltage pulses, however, has been a challenge for ultrasonic imaging systems, particularly today's portable systems. In the following section, we focused on the design and implementation of an integrated high-voltage pulse driver for multi-channel biomedical ultrasound actuators. Figure 4. A typical biomedical ultrasound actuator/receiver system (HV MUX presents high-voltage multiplexer, LV and HV signals present low-voltage reflected and high-voltage excited signals, respectively, T/R switch presents the transmit/receive switch, LNA is the low noise amplifier, VGA is the variable gain amplifier, and ADC is the analog-to-digital converter).
The schematic of the integrated high-voltage pulse driver is shown in Figure 5. It mainly consists of three stages, including the input stage, on-chip floating power supplies and H-bridge power driver. Several techniques are employed in this high-voltage pulse driver design to achieve low static power and low harmonics at the output. These techniques are described in the following section.  Figure 4. A typical biomedical ultrasound actuator/receiver system (HV MUX presents high-voltage multiplexer, LV and HV signals present low-voltage reflected and high-voltage excited signals, respectively, T/R switch presents the transmit/receive switch, LNA is the low noise amplifier, VGA is the variable gain amplifier, and ADC is the analog-to-digital converter).

Input buffer &
The schematic of the integrated high-voltage pulse driver is shown in Figure 5. It mainly consists of three stages, including the input stage, on-chip floating power supplies and H-bridge power driver. Several techniques are employed in this high-voltage pulse driver design to achieve low static power and low harmonics at the output. These techniques are described in the following section.
multi-channel transceivers are often indispensable in modern biomedical ultrasound systems, and they inevitably increase system complexity and power budgets. The generation of multiple high-voltage pulses, however, has been a challenge for ultrasonic imaging systems, particularly today's portable systems. In the following section, we focused on the design and implementation of an integrated high-voltage pulse driver for multi-channel biomedical ultrasound actuators. Figure 4. A typical biomedical ultrasound actuator/receiver system (HV MUX presents high-voltage multiplexer, LV and HV signals present low-voltage reflected and high-voltage excited signals, respectively, T/R switch presents the transmit/receive switch, LNA is the low noise amplifier, VGA is the variable gain amplifier, and ADC is the analog-to-digital converter).
The schematic of the integrated high-voltage pulse driver is shown in Figure 5. It mainly consists of three stages, including the input stage, on-chip floating power supplies and H-bridge power driver. Several techniques are employed in this high-voltage pulse driver design to achieve low static power and low harmonics at the output. These techniques are described in the following section.  Figure 5. Proposed architecture of the integrated bipolar pulse driver (VDDH is the highest voltage, while VSSL is the lowest voltage supplied to the system, RTZ presents the return-to-zero control signal. HSDP and LSDN present the high-side and low-side control signal, VDD sets 5V and VSS sets -5V, and VSSH and VDDL are set by VDDH and VSSL, respectively, as defined in Equations (9) and (10)).

Input Stage
The input stage, as shown in Figure 6a, consists of signal conditioners (buffers), the delay element and a return-to-zero signal generator. The input stage processes the input signal fed from the outside signal generator (i.e., the Field Programmable Gate Array (FPGA)) controller and produces three signals (i.e., HSDP, LSDN, and RTZ as shown in Figure 5) to switch the H-bridge power driver on and off. Since the input signals IN1 and IN2 work independently to control the H-bridge, a non-overlapping circuit inside the pulse driver system was designed to avoid any possible current shoot-through between power transistors. In order to achieve this, a 3-bit digitally adjustable delay element was designed to control the timing gap of the non-overlapping circuit (Figure 6b). The truth table of the output driving signal vs the input signal is shown in Figure 6c. produces three signals (i.e., HSDP, LSDN, and RTZ as shown in Figure 5) to switch the H-bridge power driver on and off. Since the input signals IN1 and IN2 work independently to control the H-bridge, a non-overlapping circuit inside the pulse driver system was designed to avoid any possible current shoot-through between power transistors. In order to achieve this, a 3-bit digitally adjustable delay element was designed to control the timing gap of the non-overlapping circuit (Figure 6b). The truth table of the output driving signal vs the input signal is shown in Figure 6c.

H-Bridge Power Driver
The H-bridge power driver consists of level-shifters, pre-drivers, two high-voltage (HV) diodes (D1/D2) and four power FETs (MP1/2 and MN1/2), as shown in Figure 7. The two signals, HSDP and LSDN, are used to turn on MP1 and MN1 by employing two floating level-shifters, Level-Shifter-up #1 and Level-Shifter-down #2, as well as pre-drivers to boost their driving voltage levels to within the voltage level of VSSH to VDDH and VDDL to VSSL, respectively. When the ultrasound system is in the receive mode, the RTZ signal turns on MP2 and MN2 and returns zero voltage from either the VDDH or VSSL voltage level to avoid affecting the reception of the echo signals. In order to adjust the turn-on dV/dt rate of the final-stage power FETs, diodes are placed in a series between the gates of MP1/MN1 and the pre-drivers. The diodes set the turn-on voltage and hence can be used to adjust the overall turn-on rising edge of the power FETs. Another advantage is the ability to reduce EMI or circuit switching noise. Figure 8 shows the schematic of the turn-on sequences and turn-on dV/dt slew-rate adjustment of the H-bridge. On the other hand, the size of the HV diodes and MP2/MN2 set the return-to-zero speed of the H-bridge, which should be set comparable to the turn-on rising edge of MP1/MN1. The size selection for four power FETs will be described in detail in Section 3.5.
hence can be used to adjust the overall turn-on rising edge of the power FETs. Another advantage is the ability to reduce EMI or circuit switching noise. Figure 8 shows the schematic of the turn-on sequences and turn-on dV/dt slew-rate adjustment of the H-bridge. On the other hand, the size of the HV diodes and MP2/MN2 set the return-to-zero speed of the H-bridge, which should be set comparable to the turn-on rising edge of MP1/MN1. The size selection for four power FETs will be described in detail in Section 3.5.

Low-Power Floating Power Supply
Since the output stage uses push-pull architecture, a pair of high-voltage power devices are employed as the output stage. The design of their driver stages can also use push-pull architectures the ability to reduce EMI or circuit switching noise. Figure 8 shows the schematic of the turn-on sequences and turn-on dV/dt slew-rate adjustment of the H-bridge. On the other hand, the size of the HV diodes and MP2/MN2 set the return-to-zero speed of the H-bridge, which should be set comparable to the turn-on rising edge of MP1/MN1. The size selection for four power FETs will be described in detail in Section 3.5.

Low-Power Floating Power Supply
Since the output stage uses push-pull architecture, a pair of high-voltage power devices are employed as the output stage. The design of their driver stages can also use push-pull architectures

Low-Power Floating Power Supply
Since the output stage uses push-pull architecture, a pair of high-voltage power devices are employed as the output stage. The design of their driver stages can also use push-pull architectures to efficiently drive the output stage. Since the gate voltage of high-voltage PMOS/NMOS devices is limited by the maximum operating voltage of Vgs, the output voltage swing of the driver has to be within 5 V. Therefore, each driver requires a set of 5-V rail-to-rail power supplies to provide a source/sink current to the output. In order to simplify the power supplies, a floating voltage source architecture is employed. Figure 9 shows two floating voltage sources generated by the VDDH and VSSL to ground, respectively. The pair of high-voltage PMOS/NMOS devices in series with two sets of Zener and high-voltage diodes form a voltage divider loop and output two voltages respective to the voltage drop of the Zener diode. Another two high-voltage PMOS/NMOS devices in parallel with the divider loop are functioned as the source follower to provide stable output voltages. For instance, the output voltages VDDL and VSSH are generated by VSSL and VDDH, as shown in Equations (9) and (10), respectively.
One of the advantages of this architecture is its fast settling and stable output, even though the output voltage is not accurately regulated. However, it dissipates power once the VDDH or VSSL is applied, which degrades the efficiency of the overall system. Therefore, switch control signals generated by the inputs IN1 and IN2 are employed. The floating power supply can only work following the input signal's commands. When there is no input signal for a period of time, the floating power supply can be turned off to reduce power dissipation.

Capacitor-Coupled Floating Level-Shifter Design
Level-shifters are used in applications that require interfaces between different voltage domains. There are two types of level-shifters, full-swing and floating, which can be distinguished by whether the voltage domain shares a common ground potential. Figure 10 shows a schematic of a conventional latch-based full-swing level-shifter, which is used to boost the input signal from a "Vlow" level to a "Vhigh" level. The inverter chain (M1-M12) is used to reconstruct the rail-to-rail digital signal from the off-chip input control signal. The cross-couple pair (M15 and M16) can latch the "high" digital signal level. When the input signal switches to a "low" level, M16 and M17 are turned off, and M15 and M18 are turned on. The output voltage is 0 V. However, as the input signal becomes a "high" level, M16 and 17 are switched on, and M15 and M18 are switched off. The output voltage then becomes Vhigh. One of the advantages of this architecture is its fast settling and stable output, even though the output voltage is not accurately regulated. However, it dissipates power once the VDDH or VSSL is applied, which degrades the efficiency of the overall system. Therefore, switch control signals generated by the inputs IN1 and IN2 are employed. The floating power supply can only work following the input signal's commands. When there is no input signal for a period of time, the floating power supply can be turned off to reduce power dissipation.

Capacitor-Coupled Floating Level-Shifter Design
Level-shifters are used in applications that require interfaces between different voltage domains. There are two types of level-shifters, full-swing and floating, which can be distinguished by whether the voltage domain shares a common ground potential. Figure 10 shows a schematic of a conventional latch-based full-swing level-shifter, which is used to boost the input signal from a "Vlow" level to a "Vhigh" level. The inverter chain (M1-M12) is used to reconstruct the rail-to-rail digital signal from the off-chip input control signal. The cross-couple pair (M15 and M16) can latch the "high" digital signal level. When the input signal switches to a "low" level, M16 and M17 are turned off, and M15 and M18 are turned on. The output voltage is 0 V. However, as the input signal becomes a "high" level, M16 and 17 are switched on, and M15 and M18 are switched off. The output voltage then becomes Vhigh. The full-swing level-shifter shown in Figure 10 is not appropriate for power FET gate driver design since the gate driver needs a floating rail to switch on/off the final stage of the power devices. Floating level-shifters, however, can shift the potential of control signals from circuits of a low-voltage power rail to potential with floating and ground rails, and therefore floating level-shifters are often used in gate drivers to drive output stages. Figure 11 shows the designed capacitive-coupled level-shifter architecture employed for the H-bridge power driver. For instance, the Level Shifter #1 in Figure 7, is used to shift the signal voltage levels of 0 V and VDD to VSSH and VDDH, respectively. The level-shifter consists of a pair of inverters (Mi1-Mi4), two coupling capacitors (C1 and C2), a latch (M19-M22), an output inverter (M23-M24) and a dummy inverter The full-swing level-shifter shown in Figure 10 is not appropriate for power FET gate driver design since the gate driver needs a floating rail to switch on/off the final stage of the power devices. Floating level-shifters, however, can shift the potential of control signals from circuits of a low-voltage power rail to potential with floating and ground rails, and therefore floating level-shifters are often used in gate drivers to drive output stages. Figure 11 shows the designed capacitive-coupled level-shifter architecture employed for the H-bridge power driver. For instance, the Level Shifter #1 in Figure 7, is used to shift the signal voltage levels of 0 V and VDD to VSSH and VDDH, respectively. The level-shifter consists of a pair of inverters (Mi1-Mi4), two coupling capacitors (C1 and C2), a latch (M19-M22), an output inverter (M23-M24) and a dummy inverter (Mdum1 or Mdum2), which is utilized to keep the same output impedance seen by inverters of M21 and M22. The pair of inverters (Mi1-Mi4) operates at a 5-V power supply, while the latch, dummy inverter and output inverter are supplied by VSSH and VDDH power sources. Mi1 and Mi4 and the latch are isolated by two coupling capacitors, C1 and C2, which couple through the control signals to the output stages. The full-swing level-shifter shown in Figure 10 is not appropriate for power FET gate driver design since the gate driver needs a floating rail to switch on/off the final stage of the power devices. Floating level-shifters, however, can shift the potential of control signals from circuits of a low-voltage power rail to potential with floating and ground rails, and therefore floating level-shifters are often used in gate drivers to drive output stages. Figure 11 shows the designed capacitive-coupled level-shifter architecture employed for the H-bridge power driver. For instance, the Level Shifter #1 in Figure 7, is used to shift the signal voltage levels of 0 V and VDD to VSSH and VDDH, respectively. The level-shifter consists of a pair of inverters (Mi1-Mi4), two coupling capacitors (C1 and C2), a latch (M19-M22), an output inverter (M23-M24) and a dummy inverter (Mdum1 or Mdum2), which is utilized to keep the same output impedance seen by inverters of M21 and M22. The pair of inverters (Mi1-Mi4) operates at a 5-V power supply, while the latch, dummy inverter and output inverter are supplied by VSSH and VDDH power sources. Mi1 and Mi4 and the latch are isolated by two coupling capacitors, C1 and C2, which couple through the control signals to the output stages. Figure 11. Schematic of a latch-based capacitor-coupled floating level-shifter. Figure 12 shows the simplified model of the latched stage with capacitor coupling between the input and the leveled outputs, where Gm represents the sum of the trans-conductance of M19 and M20 (same as M21 and M22), CL is the input capacitance of M23 and M24 and RL represents the output node impedance of M19 and M20. Following Figure 11, the dynamic behaviors of the latch outputs, Vx and Vy, can be written into Equations (11) and (12).  Figure 12 shows the simplified model of the latched stage with capacitor coupling between the input and the leveled outputs, where Gm represents the sum of the trans-conductance of M19 and M20 (same as M21 and M22), CL is the input capacitance of M23 and M24 and RL represents the output node impedance of M19 and M20. Following Figure 11, the dynamic behaviors of the latch outputs, Vx and Vy, can be written into Equations (11) and (12). . .
By replacing RL and CL with τ = RLCL, Av = GmRL, and reordering the formula, Equations (13) and (14) represent the cross-correlation between Vx and Vy. By replacing RL and CL with τ = RLCL, Av = GmRL, and reordering the formula, Equations (13) and (14) represent the cross-correlation between Vx and Vy.
Using Equations (13) and (14) we can solve where δV is the voltage difference between the input and output of the Latch (i.e., Vx-Vy in our design), and δV 0 is the initial voltage difference at the beginning of the latch phase. Based on Equation (15), the transition time of the latch can be solved as expressed in Equation (16).
The rising/falling slew-rate of the level-shifter,SR +/− , can then be defined as Since the latched time is reversed-logarithmic proportional to δV 0 , Tlatch will be too large to affect the desired slew-rate if δV 0 is a small value. From Figure 11, we can find δV 0 = C 1 C 1 +C in VDD. The ratio between the coupling capacitance and the input capacitance of the latches affects the latched time. The value of C1 can therefore be designed comparably to that of Cin in order to avoid a small δV 0 , as shown in Figure 11. In addition, in order to have a balanced slew-rate of the level-shifters, the coupling capacitance ratio between C1 and C2 has to be investigated to ensure the slew-rate performance between these level-shifters once the latches have been designed. Figure 13 shows that the simulated slew-rate of the level-shifter as the value of the coupling capacitance is varied accordingly. The optimal design can be found by choosing the corresponding coupling capacitance with SR+ equal to SR−. Since the coupling capacitor has to withstand a large voltage drop between VDDH and VDD, on-chip metal-oxide-metal (MOM) capacitors are employed in series to increase the voltage resistance to 100 V for such applications. Figure 14 shows the schematic diagram and layout of the on-chip MOM capacitor.

Final Stage Power Inverter Design
In addition to considering the size of the transistor providing the load driving capability, the parasitic effects of the package and bonding wires were also attended in the design phase to design the output power FETs,. Figure 15 shows the outline of the QFN-64L package for the eight-channel ultrasound pulse driver IC. The equivalent parasitic parameters Cpad, Cpin, Rb and Lb extracted by Ansys Q3D extractor (ANSYS Inc., Canonsburg, PA, USA) are 0.4 pF, 1 pF, 0.4 Ω and 1 nH, respectively. These parameters, along with the equivalent load impedance, participate in the design to determine the size of the power FETs. As described in Section 3.2, the size ratio between the MP1/2, MN1/2 and the HV diodes determines the turn-on/turn-off time of the high-voltage H-bridge. In our design, the dimensions of the transistors MP1 and MP2 are swept accordingly to account for the external slew-rate of the final stage, which is based on the fixed size of MN1 shown in Figure 15. Since the output current capability of the power FET is approximately proportional to the transistor size, the current capability of the output node becomes stronger and the charging rise-time can become shorter as the size increases. However, as the transistor size gets too big, the excessive capacitance at the output node increases the discharge time. Therefore, the size selection

Final Stage Power Inverter Design
In addition to considering the size of the transistor providing the load driving capability, the parasitic effects of the package and bonding wires were also attended in the design phase to design the output power FETs,. Figure 15 shows the outline of the QFN-64L package for the eight-channel ultrasound pulse driver IC. The equivalent parasitic parameters Cpad, Cpin, Rb and Lb extracted by Ansys Q3D extractor (ANSYS Inc., Canonsburg, PA, USA) are 0.4 pF, 1 pF, 0.4 Ω and 1 nH, respectively. These parameters, along with the equivalent load impedance, participate in the design to determine the size of the power FETs. As described in Section 3.2, the size ratio between the MP1/2, MN1/2 and the HV diodes determines the turn-on/turn-off time of the high-voltage H-bridge. In our design, the dimensions of the transistors MP1 and MP2 are swept accordingly to account for the external slew-rate of the final stage, which is based on the fixed size of MN1 shown in Figure 15. Since the output current capability of the power FET is approximately proportional to the transistor size, the current capability of the output node becomes stronger and the charging rise-time can become shorter as the size increases. However, as the transistor size gets too big, the excessive capacitance at the output node increases the discharge time. Therefore, the size selection of the power transistors must seek an appropriate dimension for the power transistors, as the rise and fall times can overlap (i.e., the rise and fall times become almost equal). Figure 16 shows the simulated rise/fall times (from 10% to 90% VDDH or VSSL) versus the size of MP1 and MP2, respectively. The best design for this application is to set a width of approximately 9500 µm for MP1 and 8000 µm for MP2 in order to allow the final-stage power FETs to operate at the similar slew-rate. To ensure the quality of the final output, corner and Monte Carlo simulations were performed during the design phase with a special emphasis on the effect of the output stage size. During the layout phase, we set several adjustment points inside the circuit to reduce the impact of process-voltage-temperature (PVT) on overall performance. Table 1 summarizes the optimized dimensions of each power transistor in this design.
MP1 and 8000 μm for MP2 in order to allow the final-stage power FETs to operate at the similar slew-rate. To ensure the quality of the final output, corner and Monte Carlo simulations were performed during the design phase with a special emphasis on the effect of the output stage size. During the layout phase, we set several adjustment points inside the circuit to reduce the impact of process-voltage-temperature (PVT) on overall performance. Table 1 summarizes the optimized dimensions of each power transistor in this design.   and fall times can overlap (i.e., the rise and fall times become almost equal). Figure 16 shows the simulated rise/fall times (from 10% to 90% VDDH or VSSL) versus the size of MP1 and MP2, respectively. The best design for this application is to set a width of approximately 9500 μm for MP1 and 8000 μm for MP2 in order to allow the final-stage power FETs to operate at the similar slew-rate. To ensure the quality of the final output, corner and Monte Carlo simulations were performed during the design phase with a special emphasis on the effect of the output stage size. During the layout phase, we set several adjustment points inside the circuit to reduce the impact of process-voltage-temperature (PVT) on overall performance. Table 1 summarizes the optimized dimensions of each power transistor in this design.

Experimental Results and Discussions
The high-voltage pulse driver was fabricated in a 0.5 µm CMOS-SOI technology, which allows mixing different structures such as CMOS for digital circuits and high-voltage MOS structures for power and high-voltage applications on the same wafer with buried isolation layer [26]. Figure 17 shows a cross-section of the CMOS-SOI process, and the high-voltage MOS transistors are fully compatible with the existing CMOS process. The final stage power transistors used in the design are 150-V N-and P-channel drain-extension field-effect transistors (FETs). The chip micrograph of the designed eight-channel pulse driver is shown in Figure 18, and it measures 8000 µm × 7100 µm area.
The performance verification of the high-voltage pulse driver was carried out by electrical and acoustic field measurements, which will be introduced in the following section.
mixing different structures such as CMOS for digital circuits and high-voltage MOS structures for power and high-voltage applications on the same wafer with buried isolation layer [26]. Figure 17 shows a cross-section of the CMOS-SOI process, and the high-voltage MOS transistors are fully compatible with the existing CMOS process. The final stage power transistors used in the design are 150-V N-and P-channel drain-extension field-effect transistors (FETs). The chip micrograph of the designed eight-channel pulse driver is shown in Figure 18, and it measures 8000 μm × 7100 μm area. The performance verification of the high-voltage pulse driver was carried out by electrical and acoustic field measurements, which will be introduced in the following section.

Electrical Performance Verification
The electrical characteristics of the designed high-voltage ultrasound pulse driver were verified using a gated input signal at 3.5 MHz and dummy loads with a 1-K ohm resistance in parallel with a 220-pF capacitance. Figures 19 and 20 show the measured output bipolar voltage waveform and its spectrum diagram, respectively. The output voltage can reach more than 100 Vpp with rising and falling times of 18.6 and 18.5 nsec. The second harmonic distortion is down to −40 dBc. Table 2 records that the static power consumption of a single channel pulse driver of approximately 3.6 mW (including the power consumption of 11.24 μW from the leakage of the floating power supply) without a drive signal input (VDD = 50 V, VSS = −50 V). The power consumption of the driver increases slightly with the switching frequency of the input drive signal. Since the floating power supply is triggered by the input signal and is intended to supply the eight-channel pulse drivers, it consumes about 100 μA of static DC current. The power consumed by each driver is approximately 48~49 mW when the excitation period of the high-voltage pulse signals accounts for

Electrical Performance Verification
The electrical characteristics of the designed high-voltage ultrasound pulse driver were verified using a gated input signal at 3.5 MHz and dummy loads with a 1-K ohm resistance in parallel with a 220-pF capacitance. Figures 19 and 20 show the measured output bipolar voltage waveform and its spectrum diagram, respectively. The output voltage can reach more than 100 Vpp with rising and falling times of 18.6 and 18.5 nsec. The second harmonic distortion is down to −40 dBc. Table 2 records that the static power consumption of a single channel pulse driver of approximately 3.6 mW (including the power consumption of 11.24 µW from the leakage of the floating power supply) without a drive signal input (VDD = 50 V, VSS = −50 V). The power consumption of the driver increases slightly with the switching frequency of the input drive signal. Since the floating power supply is triggered by the input signal and is intended to supply the eight-channel pulse drivers, it consumes about 100 µA of static DC current. The power consumed by each driver is approximately 48~49 mW when the excitation period of the high-voltage pulse signals accounts for 1% of the pulse repetition frequency (PRF = 10 kHz). Table 3 summarizes a performance comparison with several published works. Compared to the other more complex circuit architectures in Table 3, the proposed pulse driver achieves the same operating frequency and rise/fall slew-rates (>3.5 kV/µsec), while the HD2 performance is also less than −40 dBc, meeting the requirements for harmonic imaging applications as described in Section 2. In addition, there are two aspects of performance that are more prominent than the earlier works. First, the proposed architecture designs floating voltage sources inside the chip that can greatly reduce the number of voltage sources required externally. Moreover, the floating power supply activated by the input control signal can reduce the overall chip power dissipation, thereby reducing the input power of the driver without affecting the output drive capability. This is very important for portable ultrasound scanners. The lower the power consumption per channel, the more channels the system can use to excite the ultrasonic actuator with a fixed input power, which helps to improve the overall quality of the ultrasound image.

Acoustic Field Measurement Results
The integrated eight-channel ultrasound pulse driver test board for verifying transmit beamforming was assembled and tested with a phased array probe. The probe under test was BS7L3 made from Broadsound corporation (Hsinchu, TW), which has a fractional bandwidth of over 60%. The experiment was performed using the Acoustic Intensity Measurement System (AIMS) made from Onda corporation (Sunnyvale, CA, USA). Figure 21a shows a picture of the designed eight-channel driver test board and Figure 21b shows the high-voltage output waveform of four of the channels. The measurement setup, including a water tank to model the underwater environment and a sound file analyzer to synthesize the beamforming results, is shown in Figure 21c. After generating the input beamforming signals of different delay times by FPGA encoding, transducers were excited by these eight sets of high-voltage pulses. A wide dynamic range preamplifier was used to measure the sound field produced by the ultrasound probe after excitation by the actuators. Figure 21d presents the wideband receiver for the acoustic field measurements. Figure 22 shows the measurement results of the transmit beamforming. The maximum 4 MPa was obtained at the focal plane after beamforming. At a focal plane 3.5~4.0 cm away from the probe, the beam intensity is about 180 µJ/cm 2 .
To verify the harmonic content of the echo signal, another measurement setup was performed using a single-channel patch transducer with the designed driver. Figure 23 shows the measurement setup. The patch transducer can act as both an excitation and an echo signal acquisition device. Figure 24a shows the picture of the patch transducer, and the impedance measurement result is shown in Figure 24b. The high-voltage pulse waveform for excitation and the echo signal measured by the transducer are shown in Figure 24c. The spectrum obtained by Fourier analysis of the echo signal is shown in Figure 24d. The second harmonic leakage at the receiver compared to the fundamental signal was less than 40 dB, indicating that this ultrasound driver meets the basic criteria for harmonic imaging applications.    Figure 22 shows the measurement results of the transmit beamforming. The maximum 4 MPa was obtained at the focal plane after beamforming. At a focal plane 3.5~4.0 cm away from the probe, the beam intensity is about 180 μJ/cm 2 . To verify the harmonic content of the echo signal, another measurement setup was performed using a single-channel patch transducer with the designed driver. Figure 23 shows the measurement setup. The patch transducer can act as both an excitation and an echo signal acquisition device. Figure 24a shows the picture of the patch transducer, and the impedance measurement result is shown in Figure 24b. The high-voltage pulse waveform for excitation and the echo signal measured by the transducer are shown in Figure 24c. The spectrum obtained by Fourier analysis of the echo signal is shown in Figure 24d. The second harmonic leakage at the receiver compared to the fundamental signal was less than 40 dB, indicating that this ultrasound driver meets the basic criteria for harmonic imaging applications.  The measurement setup for underwater echo signal acquisition using the actuator/receiver system. Figure 23. The measurement setup for underwater echo signal acquisition using the actuator/receiver system. Figure 24. The actuator/receiver harmonic leakage verification measurement with a patch transducer as the load of the actuator (a), the impedance measurement of the patch transducer (b), high-voltage bipolar pulses as transmitting signals (orange) and receiving signals (green) (c) and the spectrum analysis of the echo signals (d).

Conclusions
The designed high-voltage pulse driver, which includes a high-voltage H-bridge driver with two pairs of P/N high-voltage MOSFETs and diodes associated with high-speed capacitor-coupled level-shifters and an input stage for the signal conditioner, can provide a low second harmonic (−40 dBc), a high-voltage output (>100 Vpp) with a wide oscillation frequency (>10 MHz) and low power consumption (<3.6 mW/per channel). In addition, a dual input signal control floating power supply simplifies the design of integrated ultrasound systems. The overall performance of the eight-channel high-voltage bipolar pulse driver was electrically and Transmit pulses Echo signals Figure 24. The actuator/receiver harmonic leakage verification measurement with a patch transducer as the load of the actuator (a), the impedance measurement of the patch transducer (b), high-voltage bipolar pulses as transmitting signals (orange) and receiving signals (green) (c) and the spectrum analysis of the echo signals (d).

Conclusions
The designed high-voltage pulse driver, which includes a high-voltage H-bridge driver with two pairs of P/N high-voltage MOSFETs and diodes associated with high-speed capacitor-coupled level-shifters and an input stage for the signal conditioner, can provide a low second harmonic (−40 dBc), a high-voltage output (>100 Vpp) with a wide oscillation frequency (>10 MHz) and low power consumption (<3.6 mW/per channel). In addition, a dual input signal control floating power supply simplifies the design of integrated ultrasound systems. The overall performance of the eight-channel high-voltage bipolar pulse driver was electrically and acoustically verified by the ONDA sound field measurement system, respectively. The experimental results indicate the proposed design has high potential for medical ultrasound scanners, especially for advanced tissue harmonic imaging applications.