Interface Optimization and Performance Enhancement of Er2O3-Based MOS Devices by ALD-Derived Al2O3 Passivation Layers and Annealing Treatment

In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10−9 A/cm2 and the smallest interfacial density of states (Dit) of 2.38 × 1012 cm−2 eV−1 have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10−9 A/cm2. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.


Introduction
Metal oxide semiconductor (MOS) capacitors are used in many different fields, such as optoelectronics, microelectronics, and biomedical diagnosis, for their excellent optical and electrical properties. However, with the increase in circuit integration, the feature size of metal oxide semiconductor field effect transistors (MOSFETs) must be reduced to less than 1 nm, which leads to a sharp deterioration in the performance of the previous MOSFETs with SiO 2 gate dielectric due to the reduction in the size of SiO 2 to its physical limits. The great leakage current brings about a sharp increase in the static power consumption of the logic circuit, as well as high-frequency dispersion, poor reliability, increased errors, and other problems [1]. Direct electron tunneling of SiO 2 films with thicknesses less than 1 nm has been reported to result in severe leakage currents. Therefore, high-k gate dielectric is sought to increase the physical thickness and reduce the leakage current instead of SiO 2 [2][3][4].
In the past decades, to decrease the leakage current and keep gate capacitance per unit area constant, some high-k gate dielectrics have been adopted to substitute SiO 2 as the gate dielectric for MOS capacitors [5][6][7][8]. Among these candidates, rare earth oxides have gained attention due to their high dielectric constant and large band gap. Er 2 O 3 , as a classic rare earth oxide, is one of the most promising gate dielectrics to replace SiO 2 for its large band gap (5.8 eV), large valence band offset (3.5 eV), suitable high-k value (8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) [9], and good chemical stability when in contact with Si substrates. Moreover, Er 2 O 3 remains amorphous when annealed at 700 • C, and its good thermal stability reduces the formation of silicide and surface roughness [10]. The gate dielectric is the most important part of MOS capacitors because the electrical characteristics of MOS capacitors depend mainly on the process parameters of the deposited film, the quality of the substrate/oxide interface, and the chemical stability of the interface. So far, the commonly used methods to obtain Er 2 O 3 thin films include atomic layer deposition (ALD), chemical vapor deposition (CVD), and molecular beam epitaxy (MBE). The cost and environmental pollution are comparatively high for the above methods. In the current work, sputtering was carried out to sputter metallic Er targets under vacuum conditions to obtain Er 2 O 3 films with appropriate rates at low cost and no contamination. Due to the high water vapor absorption characteristics of rare earth oxides, low dielectric constant hydroxides may be generated at the interface, resulting in reduced reliability and electrical performance of the device [11]. The water absorption of rare earth oxides may also be caused by oxygen vacancies in the film [12]. Based on previous investigations, it can be noted that aluminum oxide dielectric prepared by ALD has excellent thermal stability, oxidation resistance, and mature technology, making it an ideal passivation layer [13]. Meanwhile, the thermal annealing method is adopted to decrease the hydroxyl content in the films. Although the dielectric properties of Er 2 O 3 gate insulator have been investigated, the effect of the location of the ALD-driven Al 2 O 3 passivation layer and different annealing temperatures on the electric performance and interfacial bonding states of Si-based MOS capacitors have not been systematically investigated.
In this work, Er 2 O 3 thin films were deposited using magnetron sputtering. Al 2 O 3 passivation layers were obtained with ALD equipment, and four different gate stacks were constructed on Si, corresponding to Er 2 O 3 /Si, Er 2 O 3 /Al 2 O 3 /Si, Al 2 O 3 /Er 2 O 3 /Si, and Al 2 O 3 /Er 2 O 3 /Al 2 O 3 /Si, labeled S1, S2, S3, S4, respectively. Finally, Al 2 O 3 /Er 2 O 3 /Si gate stack was annealed from room temperature to 550 • C. Measurements were performed using X-ray photoelectron spectroscopy (XPS), capacitance-voltage (C-V), leakage current density-voltage (J-V), and conductance-voltage (G-V). The variation of the chemical composition and electrical properties of the apparent interface with the position of the alumina passivation layer and the effect of annealing temperature were systematically investigated. Three leakage current conduction mechanisms for silicon-based MOS capacitors with different passivation layer positions measured at 277 K were also investigated.

Experimental Section
N-type silicon wafers (100) with doping concentration of 1 × 10 15 cm −3 and resistivity of 1-10 Ω·cm have been selected as the substrate in this study. The Si substrates were ultrasonically cleaned for 10 min at 75 • C in a mixed solution of alcohol and ammonia with H 2 O:NH 3 ·H 2 O:H 2 O 2 = 7:2:1 concentration ratio before depositing Er 2 O 3 gate dielectric to remove organic contaminants and alkali metal impurities from the surface of the substrates. Then, wafers were rinsed with deionized water and blown dry with high-purity nitrogen. Finally, the as-processed wafers were immediately transferred from sputtering chamber to the ALD system. A total of 2 nm Al 2 O 3 passivation layers were deposited on Si substrate by ALD, using H 2 O and trimethylaluminum (TMA) as the oxidant and Al metal precursor, respectively. After ALD Al 2 O 3 passivation, the wafers were transferred to a sputtering chamber to deposit Er 2 O 3 gate dielectrics by sputtering the Er target with purity of 99.9% at an operating pressure of 0.6 Pa, argon/oxygen = 50/10 SCCM, and a sputtering power of 15 W, respectively. To explore the electrical characteristics of Er 2 O 3 /Si MOS capacitor with a different stacking position of the Al 2 O 3 passivation layer, Al electrodes with a diameter of 200 µm were deposited by thermal evaporation. Metal Al was thermally evaporated on the back side to form back ohmic contacts. Figure 1 shows the schematics of Si-based capacitors with different stacked gate dielectric structures. Sample S1 corresponds to Er 2 O 3 (16 nm)/Si, sample S2 corresponds to Er 2 O 3 (14 nm)/Al 2 O 3 (2 nm)/Si, sample S3 corresponds to Al 2 O 3 (2 nm)/Er 2 O 3 (14 nm)/Si, and sample S4 corresponds to Al 2 O 3 (2 nm)/Er 2 O 3 (12 nm)/Al 2 O 3 (2 nm)/Si, respectively. To gain high-quality films, the Al 2 O 3 /Er 2 O 3 /Si stacked device was selected for rapid thermal annealing (RTA) in a high vacuum of 5.0 × 10 −4 Pa at 350 • C-550 • C for 2 min. The initial temperature of the rapid annealing furnace was 20 • C, and after rising to the set temperature at a rate of 10 • C/S, the temperature was maintained for 120 S, and then lowered to room temperature. XPS measurements were performed to investigate the interface chemistry of Er 2 O 3 /Si gate stacks as functions of the Al 2 O 3 passivation layer by using the ESCALAB 250Xi system with Al Ka (1486.7 eV). The capacitance-voltage (C-V), transconductance-voltage (G-V), and leakage current-voltage (I-V) measurements were performed with the semiconductor analysis equipment (Agilent B1500A) matching with the Cascade Probe Station at room temperature. All electrical-related measurements were carried out in a dark and electrically shielded environment. Nanomaterials 2023, 13, x FOR PEER REVIEW 3 of 17 S1 corresponds to Er2O3(16 nm)/Si, sample S2 corresponds to Er2O3(14 nm)/Al2O3(2 nm)/Si, sample S3 corresponds to Al2O3(2 nm)/Er2O3(14 nm)/Si, and sample S4 corresponds to Al2O3(2 nm)/Er2O3(12 nm)/Al2O3(2 nm)/Si, respectively. To gain high-quality films, the Al2O3/Er2O3/Si stacked device was selected for rapid thermal annealing (RTA) in a high vacuum of 5.0 × 10 −4 Pa at 350 °C-550 °C for 2 min. The initial temperature of the rapid annealing furnace was 20 °C, and after rising to the set temperature at a rate of 10 °C/S, the temperature was maintained for 120 S, and then lowered to room temperature. XPS measurements were performed to investigate the interface chemistry of Er2O3/Si gate stacks as functions of the Al2O3 passivation layer by using the ESCALAB 250Xi system with Al Ka (1486.7 eV). The capacitance-voltage (C-V), transconductance-voltage (G-V), and leakage current-voltage (I-V) measurements were performed with the semiconductor analysis equipment (Agilent B1500A) matching with the Cascade Probe Station at room temperature. All electrical-related measurements were carried out in a dark and electrically shielded environment.

Interface Chemistry Analyses
XPS measurements have been carried out to analyze the influence of different stack orders of ALD-derived Al2O3 passivation layers on the interfacial chemical bonding states of the Er2O3/Si gate stack. Figure 2 shows the Er 4d spectra of Er2O3/Si gate stacks with different Al2O3 stacking orders. As shown in Figure S1, all elements are detected. The spectra taken from the S1, S2, S3, and S4 samples are decomposed into three different components. The peaks located at 167.49 eV can be attributed to the Er-M bonding states (M = Er, Al, Si). The peaks centered at 168.64 and 170.18 eV originate from Er-O and Er-O-Si bonds [14,15], respectively. The intensity of each component is different for each sample. It is worth noting that it is impossible to segregate the peaks of hydroxyl and silicate due to their very close binding energies, and here, ErSi(OH)x is also included in Er-O-Si.

Interface Chemistry Analyses
XPS measurements have been carried out to analyze the influence of different stack orders of ALD-derived Al 2 O 3 passivation layers on the interfacial chemical bonding states of the Er 2 O 3 /Si gate stack. Figure 2 shows the Er 4d spectra of Er 2 O 3 /Si gate stacks with different Al 2 O 3 stacking orders. As shown in Figure S1, all elements are detected. The spectra taken from the S1, S2, S3, and S4 samples are decomposed into three different components. The peaks located at 167.49 eV can be attributed to the Er-M bonding states (M = Er, Al, Si). The peaks centered at 168.64 and 170.18 eV originate from Er-O and Er-O-Si bonds [14,15], respectively. The intensity of each component is different for each sample. It is worth noting that it is impossible to segregate the peaks of hydroxyl and silicate due to their very close binding energies, and here, ErSi(OH) x is also included in Er-O-Si.
To compare more intuitively how much of each component is present, the corresponding content values are given in Table 1. S1 sample contains the highest silicate concentration, compared to the other samples, suggesting that the addition of Al 2 O 3 can effectively prevent the diffusion of oxygen from the air via the high-k layer of the substrate. Meanwhile, it is also obvious that the silicate content of the S3 and S4 samples is almost half of those of the S1 and S2 samples. The difference among them is that S3 and S4 samples have deposited Al 2 O 3 in the topmost layer. Due to the rare earth oxide hygroscopicity, the top Er 2 O 3 layer will lead to the formation of the low dielectric constant hydroxides, thus causing a sharp increase in the silicate content of S1 and S2 samples. As mentioned earlier, ErSi(OH) x may also be included in the silicate, which could be the reason for the difference in their silicate contents. The silicate content of S2 samples decreases by only 4% compared to S1 sample, suggesting that direct deposition of Al 2 O 3 on the substrate may not be the best choice for the passivation of Si-based rare earth oxide interfaces. To compare more intuitively how much of each component is present, the corresponding content values are given in Table 1. S1 sample contains the highest silicate concentration, compared to the other samples, suggesting that the addition of Al2O3 can effectively prevent the diffusion of oxygen from the air via the high-k layer of the substrate. Meanwhile, it is also obvious that the silicate content of the S3 and S4 samples is almost half of those of the S1 and S2 samples. The difference among them is that S3 and S4 samples have deposited Al2O3 in the topmost layer. Due to the rare earth oxide hygroscopicity, the top Er2O3 layer will lead to the formation of the low dielectric constant hydroxides, thus causing a sharp increase in the silicate content of S1 and S2 samples. As mentioned earlier, ErSi(OH)x may also be included in the silicate, which could be the reason for the difference in their silicate contents. The silicate content of S2 samples decreases by only 4% compared to S1 sample, suggesting that direct deposition of Al2O3 on the substrate may not be the best choice for the passivation of Si-based rare earth oxide interfaces. The O 1s core-level XPS spectra of all samples shown in Figure 3 are deconvoluted into four components. The first peak at 529.68 eV is caused by the Al-O bond in Al2O3. The second peak at 530.56 eV is attributed to the Er-O-Er bonds in Er2O3. It is worth noting that the Er-O-Er binding energy of S1 sample is slightly smaller than the other three samples, which may be caused by the relatively high defect density of the S1 sample, which affects the binding energy magnitude [16]. The third binding energy peak is from the Er-O-Si  The O 1s core-level XPS spectra of all samples shown in Figure 3 are deconvoluted into four components. The first peak at 529.68 eV is caused by the Al-O bond in Al 2 O 3 . The second peak at 530.56 eV is attributed to the Er-O-Er bonds in Er 2 O 3 . It is worth noting that the Er-O-Er binding energy of S1 sample is slightly smaller than the other three samples, which may be caused by the relatively high defect density of the S1 sample, which affects the binding energy magnitude [16]. The third binding energy peak is from the Er-O-Si bond in silicate at 531.95 eV, and the highest binding energy peak is from the Si-O bond in SiO 2 , corresponding to 533.02 eV [17,18]. The positions of the individual peaks extracted from O 1s are given in Table 2. It can be found that, under the stacking conditions of S3 (Al 2 O 3 /Er 2 O 3 /Si), a decrease in the strength of the Si-O and Er-O-Si bonds, as well as an increase in the strength of the Er-O-Er bonds, has been observed. The silicate contents of S1 and S2 samples are about twice that of S3 and S4 samples. The evolution tendency of the O 1s XPS spectra is similar to the Er 4d spectra, indicating that Al 2 O 3 passivation layer deposited on the topmost layer can better protect the device and reduce the formation of silicate to prevent the deterioration of device performance.
from O 1s are given in Table 2. It can be found that, under the stacking conditions of S3 (Al2O3/Er2O3/Si), a decrease in the strength of the Si-O and Er-O-Si bonds, as well as an increase in the strength of the Er-O-Er bonds, has been observed. The silicate contents of S1 and S2 samples are about twice that of S3 and S4 samples. The evolution tendency of the O 1s XPS spectra is similar to the Er 4d spectra, indicating that Al2O3 passivation layer deposited on the topmost layer can better protect the device and reduce the formation of silicate to prevent the deterioration of device performance.

Electrical Characteristics Analysis
The C-V characteristic curves of all samples measured at high frequencies (1 MHz) are illustrated in Figure 4a, demonstrating a double sweep mode from inversion to accumulation. Error plots of the J-V images of the S1-S4 samples are shown in Figure S2. Based on Figure 4, it can be seen that S1 sample has the smallest accumulation capacitance (Cox) and the largest hysteresis voltage, which may be caused by the low-k interface layer that occurs due to the presence of more Si oxides on the substrate. This corresponds to the maximum silicate content of S1 sample in previous XPS results. Compared with the S1 sample, optimized C-V characteristics have been observed in the sample with the passivated layer, including a significant increase of capacitance in the accumulation region and a reduction in the hysteresis and stretching phenomena, revealing that a passivation layer

Electrical Characteristics Analysis
The C-V characteristic curves of all samples measured at high frequencies (1 MHz) are illustrated in Figure 4a, demonstrating a double sweep mode from inversion to accumulation. Error plots of the J-V images of the S1-S4 samples are shown in Figure S2. Based on Figure 4, it can be seen that S1 sample has the smallest accumulation capacitance (C ox ) and the largest hysteresis voltage, which may be caused by the low-k interface layer that occurs due to the presence of more Si oxides on the substrate. This corresponds to the maximum silicate content of S1 sample in previous XPS results. Compared with the S1 sample, optimized C-V characteristics have been observed in the sample with the passivated layer, including a significant increase of capacitance in the accumulation region and a reduction in the hysteresis and stretching phenomena, revealing that a passivation layer of Al 2 O 3 passivated layer significantly suppresses the generation of low-k interfacial layers, thus weakening the interfacial Fermi pinning effect. In particular, compared with samples S2 and S4, the capacitance of the accumulation region of sample S3 is more saturated and the hysteresis is smaller, and sample S3 has the best electrical properties, which suggests that the passivation treatment has effectively controlled the interfacial trap density and slow interface states density [19]. As shown in Table 3, some important electrical parameters extracted from the C-V curves can help us in the quantitative analysis of the electrical properties of the silicon-based MOS capacitors. Also, in Figures S3 and S4, a line graph is  Table 3 also displays the values of flat band voltage (V fb ), hysteresis voltage (∆V fb ), the density of oxide charges (Q ox ), and the border-trapped oxide charge (N bt ) of all deposited samples. The flat-band voltage of the MOS capacitor is 0 V in the ideal state, but the flat-band voltages of our measured samples are −0.33, 0.41, 0.15, and 0.47 V, respectively, which can be due to the presence of the oxide charges located in the oxide layer or at the interface between the oxide layer and the semiconductor. Before the induction of the passivation layer, the V fb of the sample is negative, indicating that a positive oxide charge is created in Er 2 O 3 film. After the introduction of the Al 2 O 3 passivation layer, the positive V fb indicates that the passivation layer probably brings some oxygen vacancies, which can trap electrons to form negatively charged centers [20]. The oxide charge mainly includes fixed oxide charge (Q f ), movable charge (Q m ), oxide trap charge (Q ot ), and interface trap charge (Q it ). Q f is generated mainly because of oxygen vacancies formed during the oxidation process. The Al 2 O 3 /Er 2 O 3 /Si stacked structure of S3 sample has the smallest V fb value (0.15 V), which proves that it can effectively reduce the oxidation charge defects. As the oxygen vacancy at the interface diminishes, the flat-band voltage also decreases [21]. This is also evidenced by the smallest oxide charge density Q ox (−7.21 × 10 11 cm −2 ) of the S3 sample, which probably occurs because the Al 2 O 3 passivation layer deposited on the topmost part effectively isolates the air from contact with the gate oxide and the substrate, and the extremely low oxygen diffusion of the Al 2 O 3 layer avoids the introduction of new impurity defects and natural oxides.   To characterize the interfacial state density quantitatively and show the distribution in the trap energy level, Figure 5a-d show the conductance/angular frequency-voltage (G/ω-V) curves of the samples measured at 500 kHz-1 MHz. The relationship between the interface trap capacitance and the interface density of states is Cit = qDit. Interfacial traps around the Fermi energy level could shift their occupancy and change the conductivity, producing regular changes. The apparent shift in the location of the peak conductivity indicates the effectiveness of the Fermi energy level shift. The conductivity approach is based on the analysis concerning losses due to changes in the charge state of trap energy levels. The largest loss takes place when the interface trap and the applied AC signal move in resonance (ωτ = 1), the frequency dependence is associated with the response time of the characteristic trap, τ = 2π/ω, and the capture and emission rates from the Shockley-Read-Hall theory modulate the response time [24].  The difference between the V fb of the C-V curve in two directions with double-sweep mode is the ∆V fb . The magnitude of ∆V fb is associated with the boundary-captured oxide charge (Q bt ) [22]. Compared to the control S1, the hysteresis voltage of the sample with the added passivation layer is significantly reduced, indicating a significant decrease in the boundary trapping charge density, while the almost zero hysteresis voltage of the S3 sample proves that the top wrapped structure is more effective in reducing defects and protecting the device. Based on the measured values of V fb and ∆V fb , the associated Q ox and N bt values are determined by the following equations [23].
where Φ ms is the contact potential difference between the Al electrode and Si substrate, q is the fundamental charge, and A is the area of the Al electrode. The lowest Q ox value (−7.21 × 10 11 cm −2 ) and the lowest N bt value (−1.80 × 10 11 cm −2 ) visualize the optimized electrical performance of the Al 2 O 3 /Er 2 O 3 /Si gate stacking junction of the S3 sample.
To characterize the interfacial state density quantitatively and show the distribution in the trap energy level, Figure 5a-d show the conductance/angular frequency-voltage (G/ω-V) curves of the samples measured at 500 kHz-1 MHz. The relationship between the interface trap capacitance and the interface density of states is C it = qD it . Interfacial traps around the Fermi energy level could shift their occupancy and change the conductivity, producing regular changes. The apparent shift in the location of the peak conductivity indicates the effectiveness of the Fermi energy level shift. The conductivity approach is based on the analysis concerning losses due to changes in the charge state of trap energy levels. The largest loss takes place when the interface trap and the applied AC signal move in resonance (ωτ = 1), the frequency dependence is associated with the response time of the characteristic trap, τ = 2π/ω, and the capture and emission rates from the Shockley-Read-Hall theory modulate the response time [24].
where ∆E is the energy difference between the trap energy level E T and the edge of the majority carrier energy band, k B is the Boltzmann constant, T is the temperature, υ th is the average speed of the majority carrier produced by thermal excitation, D dos is the effective density of states of the majority carrier energy band, and σ is the trapping cross-section of the trap [25]. The significant shift of the peak in Figure 5 indicates that the fabricated devices have few interfacial defects and a low degree of interfacial Fermi energy level pinning. Under the assumption that the surface potential could be neglected, D it can be evaluated from the normalized parallel conductance peak (G P /ω) max [26].
Here, A is the area of the device. To determine the position of the trap energy level E T , the difference between the E T and the E c , that is, the energy band bending potential of E T , needs to be determined. Where the value of E T could be obtained from the frequencies in (G P /ω) max . Using the above formula to calculate D it , with correspondence to ∆E [27].
According to the conductivity method, the D it data of each sample was obtained, as displayed in Figure 6. It is clear that, as E c −E T increases, the D it of each sample also increases gradually. Meanwhile, the overall defect density of S3 sample is the lowest, compared with the other three samples. Experimental results have shown that the ALDderived Al 2 O 3 passivation layer on the topmost layer of the device can effectively inhibit the formation of Er(OH) x or silicate and reduce the interfacial density of states, thus preparing high-quality Si-MOS capacitors. Compared with S1, the average D it value of S3 samples was reduced from 3.08 × 10 12 eV −1 cm −2 to 2.35 × 10 12 eV −1 cm −2 . Nanomaterials 2023, 13, x FOR PEER REVIEW 8 of 17 Figure 5. Multi-frequency G/ω-V characteristic curves of (a) S1, (b) S2, (c) S3, and (d) S4 samples.
Here, A is the area of the device. To determine the position of the trap energy level ET, the difference between the ET and the Ec, that is, the energy band bending potential of ET, needs to be determined. Where the value of ET could be obtained from the frequencies in (Gp/ω)max. Using the above formula to calculate Dit, with correspondence to ΔE [27].
According to the conductivity method, the Dit data of each sample was obtained, as displayed in Figure 6. It is clear that, as Ec−ET increases, the Dit of each sample also increases gradually. Meanwhile, the overall defect density of S3 sample is the lowest, compared with the other three samples. Experimental results have shown that the ALD-derived Al2O3 passivation layer on the topmost layer of the device can effectively inhibit the formation of Er(OH)x or silicate and reduce the interfacial density of states, thus preparing high-quality Si-MOS capacitors. Compared with S1, the average Dit value of S3 samples was reduced from 3.08 × 10 12 eV −1 cm −2 to 2.35 × 10 12 eV −1 cm −2 . The conduction mechanism in dielectric films is the key to the successful application of dielectric materials. Different leakage current conduction mechanisms can cause significant differences in leakage currents. To explore the effects of different gate dielectric stacking methods on carrier transport mechanisms, three current conduction mechanisms (CCMs) are systematically discussed under substrate injection including Schottky Emission (SE), Poole-Frenkel Emission (PF) and Fowler-Nordheim Tunneling (FN) [28]. SE emission is a very classical form of thermal ionization emission where a charge gains energy under the action of an applied electric field and overcomes the potential barrier between the metal electrode and the gate dielectric, forming a leakage current. SE emission is usually found at high temperatures, and SE is formulated as follows. The conduction mechanism in dielectric films is the key to the successful application of dielectric materials. Different leakage current conduction mechanisms can cause significant differences in leakage currents. To explore the effects of different gate dielectric stacking methods on carrier transport mechanisms, three current conduction mechanisms (CCMs) are systematically discussed under substrate injection including Schottky Emission (SE), Poole-Frenkel Emission (PF) and Fowler-Nordheim Tunneling (FN) [28]. SE emission is a very classical form of thermal ionization emission where a charge gains energy under the action of an applied electric field and overcomes the potential barrier between the metal electrode and the gate dielectric, forming a leakage current. SE emission is usually found at high temperatures, and SE is formulated as follows.
Among them, A* represents the effective Richardson constant, m o is the mass of free electrons, m ox is the effective mass of electrons in the gate oxygen layer, ϕ B is the Schottky barrier height, and E is the applied electric field, which could be determined by using the equation: E = (V − V fb )/t ox . ε 0 and ε r denote the vacuum dielectric constant and the optical dielectric constant, respectively, and k B is the Boltzmann constant [29]. The optical permittivity ε r is meant to be close to the square of refractive index (n = ε r 1/2 = 1.95). For a standard SE emission, E 1/2 and ln(J/T 2 ) are in a proportional relationship. Figure 7 presents good linear fits of ln(J/T 2 ) and E 1/2 at a low field region (0.1-0.8 MV/cm), the slope of the SE-fitted curve is: PF emission mechanism is attributed to the phenomenon of thermally excited electrons gaining enough energy to jump between the traps in the dielectric layer, forming a gate leakage current in the conduction band of the gate dielectric, which can be expressed by the following equation [30].
where φt is the trap energy level, ε0 denotes the oxide dielectric constant, and B represents a constant [31]. For standard PF emission, E 1/2 and ln(J/E) should be in a good proportional relationship, as shown in Figure 8. It can be seen that PF emission mechanism at 277 K is consistent in the higher electric field region (0.6-1.4 MV/cm), but the extracted εox for S1, S2, S3, S4 is calculated to be 82.1, 82.6, 458, 648, respectively. The large difference from the measured value means that PF emission mechanism is not dominant at lower temperatures. PF emission mechanism is attributed to the phenomenon of thermally excited electrons gaining enough energy to jump between the traps in the dielectric layer, forming a gate leakage current in the conduction band of the gate dielectric, which can be expressed by the following equation [30].
where ϕ t is the trap energy level, ε 0 denotes the oxide dielectric constant, and B represents a constant [31]. For standard PF emission, E 1/2 and ln(J/E) should be in a good proportional relationship, as shown in Figure 8. It can be seen that PF emission mechanism at 277 K is consistent in the higher electric field region (0.6-1.4 MV/cm), but the extracted ε ox for S1, S2, S3, S4 is calculated to be 82.1, 82.6, 458, 648, respectively. The large difference from the measured value means that PF emission mechanism is not dominant at lower temperatures.   FN tunneling is a slightly temperature-dependent conduction mechanism that is usually observed at lower temperatures, that is, the process by which electrons pass directly from the gate medium and enter the conduction band, and the J FN is expressed by the following Equation [32].
where m * T is the tunneling effective mass in the gate oxide film, ϕ B is the potential barrier height, and the other parameters are defined as before [33]. For the FN tunneling conduction mechanism, ln(J/E 2 ) and 1/E for all samples conforms to a linear relationship, as shown in Figure 9. The measured J-V curves for all the samples at 0.8-1.4 cm/MV are also in good agreement with FN tunneling, indicating that the lower temperature (277 K) suppresses the hot electron SE and P-F emission, while the temperature-independent FN tunneling currents can be conducted at lower temperatures; therefore, smaller currents are formed at low temperatures.

Annealing Dependent Electrical Characteristics Analysis
Based on previous analyses, it can be concluded that the S3 sample (Al2O3/Er2O3/n-Si MOS capacitors) generates fewer interfacial defects and the smallest interfacial state density, indicating that the best device performance has been obtained for the Al2O3/Er2O3/Si with the appropriate passivation layer position. However, the sputtering-derived gate dielectric films do not reach the ideal state and still have a high density of interfacial states and a high leakage current density. Therefore, annealing of the sample should be carried

Annealing Dependent Electrical Characteristics Analysis
Based on previous analyses, it can be concluded that the S3 sample (Al 2 O 3 /Er 2 O 3 /n-Si MOS capacitors) generates fewer interfacial defects and the smallest interfacial state density, indicating that the best device performance has been obtained for the Al 2 O 3 /Er 2 O 3 /Si with the appropriate passivation layer position. However, the sputtering-derived gate dielectric films do not reach the ideal state and still have a high density of interfacial states and a high leakage current density. Therefore, annealing of the sample should be carried out to reduce the number of defects and impurities in the film. Nevertheless, with increasing annealing temperature, the morphology of the erbium oxide film may change, and silicates may be formed at the interface, which might lead to compromised electrical properties of MOS capacitors [34]. Therefore, it is very important to determine the optimal annealing conditions for the fabrication of high-quality devices. Figure 10 shows the AFM images of the S3 sample annealed at different temperatures from 350 • C to 550 • C. The root mean square (RMS) of the S3 sample has been calculated to be 0.668, 0.602, 0.581, and 0.674 nm, respectively. It can be seen that a suitable annealing temperature can reduce the surface roughness, and the S3 sample annealed at 450 • C has the smallest RMS value. This is mainly because a suitable annealing temperature can enhance the stoichiometric ratio of the insulator and deal with defects. Low surface roughness is conducive to the preparation of high-performance devices, and a flatter surface can effectively avoid interfacial charge generation [35]. The sample is still amorphous after annealing at 550 • C, as shown in Figure S5. Figure 11a shows the C-V curves of the S3 sample annealed at different temperatures. The important electrical parameters extracted from Figure 11a are listed in Table 4. Meanwhile, in Figures S6 and S7, a line graph is used to more visually represent the data. It is evident that the k values increase significantly increase with the increased annealing temperature, and that all the k values are within the reported values. The capacitance of the accumulation region of the annealed samples increases from the as-deposited state to the annealed state at 450 • C, while the capacitance value decreases after annealing at 450 • C. The reduction of the capacitance may result from the thickening of the interface layer between Si and Er 2 O 3 , and higher annealing temperature may lead to the breakage of the sub-stable Er-Si bond, while ErSiO y may be the major component of the interfacial layer [36]. In addition to the interfacial layer, another reason for the decrease in capacitance may be the leakage current, as the higher the leakage current, the smaller the capacitance [37]. Comparing all the parameters, it can be seen that the S3@450 • C sample obtains a smaller oxide charge density (−1.20 × 10 12 cm −2 ), a smaller boundary trap density (−2.74 × 10 10 cm −2 ), the largest dielectric constant (15.8), and the smallest hysteresis voltage (0.005 V) and leakage current density(3.68 × 10 −10 A/cm 2 ). This result indicates that treatment at an appropriate annealing temperature of 450 • C can further optimize the interfacial and electrical properties of S3 samples. out to reduce the number of defects and impurities in the film. Nevertheless, with increasing annealing temperature, the morphology of the erbium oxide film may change, and silicates may be formed at the interface, which might lead to compromised electrical properties of MOS capacitors [34]. Therefore, it is very important to determine the optimal annealing conditions for the fabrication of high-quality devices. Figure 10 shows the AFM images of the S3 sample annealed at different temperatures from 350 °C to 550 °C. The root mean square (RMS) of the S3 sample has been calculated to be 0.668, 0.602, 0.581, and 0.674 nm, respectively. It can be seen that a suitable annealing temperature can reduce the surface roughness, and the S3 sample annealed at 450 °C has the smallest RMS value. This is mainly because a suitable annealing temperature can enhance the stoichiometric ratio of the insulator and deal with defects. Low surface roughness is conducive to the preparation of high-performance devices, and a flatter surface can effectively avoid interfacial charge generation [35]. The sample is still amorphous after annealing at 550 °C, as shown in Figure S5.  Table 4. Meanwhile, in Figures S6 and S7, a line graph is used to more visually represent the data. It is evident that the k values increase significantly increase with the increased annealing temperature, and that all the k values are within the reported values. The capacitance of the accumulation region of the annealed samples increases from the as-deposited state to the annealed state at 450 °C, while the capacitance value decreases after annealing at 450 °C. The reduction of the capacitance may result from the thickening of the interface layer between Si and Er2O3, and higher annealing temperature may lead to the breakage of the sub-stable Er-Si bond, while ErSiOy may be the major component of the interfacial layer [36]. In addition to the interfacial layer, another reason for the decrease in capacitance may be the leakage current, as the higher the leakage current, the smaller the capacitance [37]. Comparing all the parameters, it can be seen that the S3@450 °C sample obtains a smaller  Figure 11b displays the J-V curves of the capacitor with the leakage current density values of 1.83 × 10 −9 , 1.33 × 10 −9 , 3.68 × 10 −10 , and 7.19 × 10 −10 A/cm 2 for S3 and 350 • C-550 • C treated samples at 1 V, respectively. The best current-voltage characteristics are achieved for the 450 • C-annealed sample compared to the as-deposited one, which can be due to the fact that the proper annealing treatment reduces the generation of defective states at the gate dielectrics as well as at the interface, thus reducing the probability of trap-assisted current generation. Figure 11c-f show the G/ω-V curves of all the samples, and it can be observed that the conductivity peaks of all samples are significantly shifted, demonstrating the effectiveness of the fermi energy level shift, and that the obtained D it has a good reference value. To quantify the defective interfacial defect distribution, the interfacial density of states (D it ) from G/ω-V curves for all samples in the frequency range from 500 kHz to 1 MHz have been extracted. oxide charge density (−1.20 × 10 12 cm −2 ), a smaller boundary trap density (−2.74 × 10 10 cm −2 ), the largest dielectric constant (15.8), and the smallest hysteresis voltage (0.005 V) and leakage current density(3.68 × 10 −10 A/cm 2 ). This result indicates that treatment at an appropriate annealing temperature of 450 °C can further optimize the interfacial and electrical properties of S3 samples.  Figure 11b displays the J-V curves of the capacitor with the leakage current density values of 1.83 × 10 −9 , 1.33 × 10 −9 , 3.68 × 10 −10 , and 7.19 × 10 −10 A/cm 2 for S3 and 350 °C-550 °C treated samples at 1 V, respectively. The best current-voltage characteristics are achieved for the 450 °C-annealed sample compared to the as-deposited one, which can be due to the fact that the proper annealing treatment reduces the generation of defective states at the gate dielectrics as well as at the interface, thus reducing the probability of trap-assisted  According to the electrical conductivity method, as shown in Figure 12, the relationship between D it distribution and ∆E has been obtained for all samples. It is observed that, with the gradual increase of E C −E T value, the D it of each sample gradually increases, and the D it of the unannealed S3 sample is significantly larger than the other samples. The overall defect density of the S3@450 • C sample is significantly smaller than that of the other samples, indicating an optimized interfacial quality. Thus, it could be summarized that the degradation of the interfacial chemistry results in the highest D it for S3 samples, and the qualitative annealing efficacy leads to the discrepancy between S3 and S3@350 • C, S3@450 • C, and S3@550 • C samples. This is mainly because a suitable annealing temperature can effectively reduce the interfacial intrinsic oxide and silicate content, which reduces the interfacial defects. Based on the above analysis, the device at S3@450 • C achieves the best dielectric properties by reducing the interfacial state. According to the electrical conductivity method, as shown in Figure 12, the relationship between Dit distribution and ΔE has been obtained for all samples. It is observed that, with the gradual increase of EC−ET value, the Dit of each sample gradually increases, and the Dit of the unannealed S3 sample is significantly larger than the other samples. The overall defect density of the S3@450 °C sample is significantly smaller than that of the other samples, indicating an optimized interfacial quality. Thus, it could be summarized that the degradation of the interfacial chemistry results in the highest Dit for S3 samples, and the qualitative annealing efficacy leads to the discrepancy between S3 and S3@350 °C, S3@450 °C, and S3@550 °C samples. This is mainly because a suitable annealing temperature can effectively reduce the interfacial intrinsic oxide and silicate content, which reduces the interfacial defects. Based on the above analysis, the device at S3@450 °C achieves the best dielectric properties by reducing the interfacial state.

Conclusions
In summary, the effect of ALD-derived layered passivation layer position and annealing temperature on the interfacial chemistry and current transport characteristics of sputter-deposited Er 2 O 3 /Si gate-stacks are explored in detail. It can be found that the Al 2 O 3 /Er 2 O 3 /Si gate stack structure can significantly protect the substrate oxide from diffusion and significantly improve the MOS device's electrical performance, including larger accumulation region capacitance, and lowest leakage current density of 4.57 × 10 −9 A/cm 2 . Different laminated gate structures were evaluated using the density of interfacial states extracted by the conductivity method, and the results have showed that the Al 2 O 3 /Er 2 O 3 /Si gate stacks have achieved the lowest density of interfacial states at 2.35 × 10 12 eV −1 cm −2 . According to the analysis of CCMs, the lower temperature (277 K) suppresses the hot electron SE and PF emission, while the temperature-independent FN tunneling current can be conducted at lower temperatures, and FN tunneling is the only predominant mechanism at the lower temperature, thus forming a smaller current at low temperatures. The annealing treatment of Al 2 O 3 /Er 2 O 3 /Si MOS capacitors at 450 • C has showed improved electrical properties, including suppression of interfacial growth, leakage current density of 1.38 × 10 −9 A/cm 2 at 1 V, as well as maximum dielectric constant of 15.8, and the minimum interfacial density of states of 7.4 × 10 11 eV −1 cm −2 . In conclusion, both the surface passivation and heat treatment can effectively suppress the regrowth of interface species and guarantee the potential application of Al 2 O 3 /Er 2 O 3 /Si gate stacks in future microelectronics.

Supplementary Materials:
The following supporting information can be downloaded at: https://www.mdpi.com/article/10.3390/nano13111740/s1. Figure S1. XPS full spectrum of S4 sample. Figure S2. XRD patterns of S3 and S3@550 • C. Figure S3. Comparison of k, V fb , and ∆V fb values for S1-S4 samples. Figure S4. Comparison of absolute values of Q ox and N bt and comparison of leakage current density values for S1-S4 samples. Figure S5. Comparison of C ox , k, and ∆V fb values for S3, S3@350 • C, S3@450 • C and S3@550 • C samples. Figure S6. Comparison of absolute values of Q ox and N bt and comparison of leakage current density values for S3, S3@350 • C, S3@450 • C and S3@550 • C samples. Figure S7. (a-d) are the error plots of J-V curves for S1-S4 samples.