Positive Bias Temperature Instability in SiC-Based Power MOSFETs

This paper investigates the threshold voltage shift (ΔVTH) induced by positive bias temperature instability (PBTI) in silicon carbide (SiC) power MOSFETs. By analyzing ΔVTH under various gate stress voltages (VGstress) at 150 °C, distinct mechanisms are revealed: (i) trapping in the interface and/or border pre-existing defects and (ii) the creation of oxide defects and/or trapping in spatially deeper oxide states with an activation energy of ~80 meV. Notably, the adoption of different characterization methods highlights the distinct roles of these mechanisms. Moreover, the study demonstrates consistent behavior in permanent ΔVTH degradation across VGstress levels using a power law model. Overall, these findings deepen the understanding of PBTI in SiC MOSFETs, providing insights for reliability optimization.


Introduction
The rapid growth of renewable energy [1] and electric vehicles (EVs) [2] is driving the development of power devices based on wide bandgap (WBG) semiconductors.Renewable energy sources such as solar and wind energy require efficient solutions to convert and manage electricity [3], as well as electric vehicles requiring high-power reliable semiconductor devices to control electric motors and charging systems [4].
Silicon carbide (SiC) stands out in the realm of power electronics, offering a robust and high-performance alternative to conventional silicon (Si) counterparts [5], thus representing one of the best choices for applications where high power and reliability are required, such as solar inverters, wind turbine control systems, and electric vehicle motor control systems.
SiC's inherent properties enable devices to operate at higher voltages, maintain stability at elevated temperatures, and switch at high frequencies.In particular, the breakdown electric field strength, nearly ten-fold that of silicon, and a band gap three times wider [6], allow for operation at elevated voltages and temperatures.Another key advantage of SiC lies in its thermal performance; it can maintain consistent operation even under hightemperature conditions [7], which is crucial for many industrial and automotive applications.The high thermal conductivity of SiC also aids in mitigating temperature-dependent degradation, ensuring longevity and reliability.
The high-frequency operation capability of SiC devices enables more compact power electronics systems [8], offering higher power density and reduced cooling requirements and opening a spectrum of possibilities in various sectors, from power systems to switchmode power supplies and EVs [9].However, while SiC technology offers significant benefits, different challenges are still present, including intricate production processes, resulting in elevated costs, and notably, issues related to device reliability.
One reliability challenge is the lower short circuit tolerance of SiC devices compared with Si ones [10,11].This necessitates the use of fast-acting gate drivers to ensure device safety and reliability.In addition, SiC devices have been observed to exhibit larger threshold voltage (V TH ) instability compared with their Si counterparts, with a tendency to faster recovery [12][13][14].In [15], two distinct trapping mechanisms contributing to V TH shift (∆V TH ) have been identified under gate bias stress tests, i.e., trapping of charges in the near-interface oxide traps (also referred as border traps) and in intrinsic defects at the SiO 2 /SiC interface.
The presence of pre-existing border traps has also been investigated in [16][17][18][19][20], highlighting the role of the tunneling in the charging and discharging processes [19], and measuring capture and emission times in the order of µs [20].The role of fast trapping mechanisms related to pre-existing interface defects has been analyzed in [21][22][23][24].
In addition to interface and border defects, the creation of new traps and/or the charge trapping in deeper energy-level defects, both localized within the oxide, has been demonstrated in [25] by applying a relatively large gate voltage.
Further investigations have indicated the role of the testing methods on the observed ∆V TH .In particular, the influence of positive/negative bias temperature instability (P/NBTI) on the electrical characteristics of SiC MOSFETs has been thoroughly studied using both slow and fast measurement techniques [26].
Recently, we reported a distinct temperature dependence of ∆V TH , which varies based on the measurement technique employed [27].When using a slow-PBTI procedure, the effect of fast interface and border traps is not accounted for in ∆VTH, as their recovery time is shorter than the V TH characterization time.As a result, the oxide charge trapping dominates ∆V TH , resulting in a positive temperature dependency, i.e., the higher the temperature, the greater the charge trapping, the higher ∆V TH .Conversely, a negative temperature dependency is observed when a fast-PBTI test is adopted, emphasizing the role of a fast interface and border traps in the overall behavior [27].
In this work, the ∆V TH of SiC MOSFETs induced by different PBTI test procedures suggested by JEDEC JEP184 [28], here named transistor and diode modes, has been investigated.The role of the gate bias level on the different underneath trapping mechanisms has been analyzed.

Devices under Test (DUTs) and BTI Characterization Techniques
In this study, a 650 V automotive grade silicon carbide power MOSFET with a verticaldiffused structure (VD-MOSFET), manufactured by STMicroelectronics, has been considered.The room temperature transfer characteristics is reported in Figure 1, additional key features can be found in [29].
The Keysight Power Device Analyzer B1505A has been adopted for this analysis.Initially, a PBTI stress and characterization procedure according to the JEDEC standard JEP184, namely transistor mode, has been adopted and reported in Figure 2a.It illustrates the gate voltage (V G ), drain voltage (V D ), and drain current (I D ) for the initial three stress and characterization periods.The gate maintains a steady bias during the stress phase, while the drain and source are grounded.Stress time periods, which increase logarithmically, are interspersed with V TH sensing intervals.Following each stress interval, the gate stress is removed to allow for conditioning and V TH sensing.To stabilize the V TH readout, a conditioning phase is carried out by a 100 ms long positive gate pulse before the V TH measurement.For the extrapolation of V TH , the I D -V G transfer characteristics are measured.During this process, V D remains constant whereas V G is swept from V G_MAX to 0 V to minimize V TH recovery.V TH is calculated at fixed I D = 1 mA.Waveforms of PBTI stress and measure procedure in the case of transistor (a) and d mode (b) method, as reported by JEDEC JEP184 standard [28].Each cycle consists of a logarit cally increasing stress period, conditioning and threshold voltage measurement.
However, as ΔVTH can be induced by slow and fast trapping/de-trapping compon [16][17][18][19][20][21][22][23][24][25], slower measurements might result in the partal loss of the contribution ascr to faster defects, i.e., fast defects recover before and/or during the VTH characteriza phase, thus not contributing to it.To gain a clearer understanding of these fast com nents, it is necessary to use faster measurement techniques.
Standard JEP184 also provides the gated-diode method for measuring the VTH o power transistors under BTI stress conditions.It involves biasing both the VG and VD ultaneously while maintaining the source at the ground potential.The test consists of blocks: a stress phase for a specified period and VTH characterization.
Similar to the previous method, during stress, VG stress is applied to the gate te nal.The increasing gate stress time corresponds to a logarithmic scale.
The VTH measurement method follows the JEDEC standard JEP183 [30], show Figure 2b.Firstly, as for the previous method, a gate conditioning pulse is applied,  Waveforms of PBTI stress and measure procedure in the case of transistor (a) a mode (b) method, as reported by JEDEC JEP184 standard [28].Each cycle consists of a log cally increasing stress period, conditioning and threshold voltage measurement.
However, as ΔVTH can be induced by slow and fast trapping/de-trapping com [16][17][18][19][20][21][22][23][24][25], slower measurements might result in the partal loss of the contribution a to faster defects, i.e., fast defects recover before and/or during the VTH characte phase, thus not contributing to it.To gain a clearer understanding of these fast nents, it is necessary to use faster measurement techniques.
Standard JEP184 also provides the gated-diode method for measuring the VT power transistors under BTI stress conditions.It involves biasing both the VG and ultaneously while maintaining the source at the ground potential.The test consist blocks: a stress phase for a specified period and VTH characterization.
Similar to the previous method, during stress, VG stress is applied to the gat nal.The increasing gate stress time corresponds to a logarithmic scale.
The VTH measurement method follows the JEDEC standard JEP183 [30], sh Figure 2b.Firstly, as for the previous method, a gate conditioning pulse is appli Waveforms of PBTI stress and measure procedure in the case of transistor (a) and diode mode (b) method, as reported by JEDEC JEP184 standard [28].Each cycle consists of a logarithmically increasing stress period, conditioning and threshold voltage measurement.
However, as ∆V TH can be induced by slow and fast trapping/de-trapping components [16][17][18][19][20][21][22][23][24][25], slower measurements might result in the partal loss of the contribution ascribed to faster defects, i.e., fast defects recover before and/or during the V TH characterization phase, thus not contributing to it.To gain a clearer understanding of these fast components, it is necessary to use faster measurement techniques.
Standard JEP184 also provides the gated-diode method for measuring the V TH of SiC power transistors under BTI stress conditions.It involves biasing both the V G and V D simultaneously while maintaining the source at the ground potential.The test consists of two blocks: a stress phase for a specified period and V TH characterization.
Similar to the previous method, during stress, V G stress is applied to the gate terminal.The increasing gate stress time corresponds to a logarithmic scale.
The V TH measurement method follows the JEDEC standard JEP183 [30], shown in Figure 2b.Firstly, as for the previous method, a gate conditioning pulse is applied, then V TH of the SiC power MOSFET is measured in diode mode, which consists of the shorting gate and drain.The instrument forces the target threshold current (I TH ), which determines the V TH with a faster spot measurement (10 ms) compared with the full I D V G characterization (few seconds), therefore avoiding V TH recovery as much as possible.

Results and Discussion
Figure 3 reports the ∆V TH under different gate stress voltages (V Gstress ) at an ambient temperature of 150 • C. Notably, the ∆V TH obtained by means of the diode mode approach is higher, especially for lower V Gstress values (i.e., 30 V), although the stress phase is the same.The difference is ascribed to the different characterization phase, which is temporally shorter in the case of diode mode, allowing for a smaller V TH recovery, hence capturing a larger ∆V TH .The difference between the two methods becomes more pronounced when operating at lower V Gstress settings or for shorter stress durations.This is because the trapping and de-trapping processes in/from shallow pre-existing defects, which demand less time to capture and release charges, emerge as the predominant mechanism responsible for ∆V TH .As the gate voltage and stress time increase, the creation of new defects or the trapping in spatially deeper oxide defects starts to play a significant role, producing a permanent or slowly recoverable ∆V TH .As a result, the different characterization time that distinguishes the two methods no longer has an impact on the ∆V TH , as the recoverable part is negligible with respect to the permanent one.

Results and Discussion
Figure 3 reports the ΔVTH under different gate stress voltages (VGstress) at an ambient temperature of 150 °C.Notably, the ΔVTH obtained by means of the diode mode approach is higher, especially for lower VGstress values (i.e., 30 V), although the stress phase is the same.The difference is ascribed to the different characterization phase, which is temporally shorter in the case of diode mode, allowing for a smaller VTH recovery, hence capturing a larger ∆VTH.The difference between the two methods becomes more pronounced when operating at lower VGstress settings or for shorter stress durations.This is because the trapping and de-trapping processes in/from shallow pre-existing defects, which demand less time to capture and release charges, emerge as the predominant mechanism responsible for ΔVTH.As the gate voltage and stress time increase, the creation of new defects or the trapping in spatially deeper oxide defects starts to play a significant role, producing a permanent or slowly recoverable ∆VTH.As a result, the different characterization time that distinguishes the two methods no longer has an impact on the ∆VTH, as the recoverable part is negligible with respect to the permanent one.To demonstrate the occurrence of an additional mechanism (creation of new oxide defects or trapping in spatially deeper defects) with respect to trapping in the pre-existing defects, the PBTI analysis is performed at different VGstress ranging from 20 V to 47 V; the latter is a few volts below the breakdown voltage.Figure 4 shows ΔVTH versus the stress time as a function of different applied VGstress.It is possible to note the following: (i) for VGstress up to 32.5 V, the long-term ∆VTH shows signs of saturation.This confirms the trapping in pre-existing defects with a finite concentration; (ii) from VGstress = 35 V to VGstress = 45 V, the ∆VTH shows a second (higher) slope, indicating the triggering of an additional trapping mechanism, which occurs at shorter stress times by increasing VGstress; (iii) for VGstress > 45 V, i.e., close to breakdown voltage, further trapping mechanisms seem to show up producing a further ∆VTH slope variation.Moreover, under these high field conditions, a negative or smaller threshold voltage drift is observed for short stress times (<30 s), while a negligible VGstress dependency is observed for long stress times (>10 4 s), indicating the presence of an additional competing mechanism, e.g., electron de-trapping from the oxide to the gate metal, contributing to VTH decrease.Overall, by focusing on the long-term behavior reported in points (ii) and (iii), it may be ascribed to the creation of new oxide defects or charge trapping into spatially deep states, i.e., oxide traps far away from the SiO2/SiC interface.To demonstrate the occurrence of an additional mechanism (creation of new oxide defects or trapping in spatially deeper defects) with respect to trapping in the pre-existing defects, the PBTI analysis is performed at different V Gstress ranging from 20 V to 47 V; the latter is a few volts below the breakdown voltage.Figure 4 shows ∆V TH versus the stress time as a function of different applied V Gstress .It is possible to note the following: (i) for V Gstress up to 32.5 V, the long-term ∆V TH shows signs of saturation.This confirms the trapping in pre-existing defects with a finite concentration; (ii) from V Gstress = 35 V to V Gstress = 45 V, the ∆V TH shows a second (higher) slope, indicating the triggering of an additional trapping mechanism, which occurs at shorter stress times by increasing V Gstress ; (iii) for V Gstress > 45 V, i.e., close to breakdown voltage, further trapping mechanisms seem to show up producing a further ∆V TH slope variation.Moreover, under these high field conditions, a negative or smaller threshold voltage drift is observed for short stress times (<30 s), while a negligible V Gstress dependency is observed for long stress times (>10 4 s), indicating the presence of an additional competing mechanism, e.g., electron de-trapping from the oxide to the gate metal, contributing to V TH decrease.Overall, by focusing on the long-term behavior reported in points (ii) and (iii), it may be ascribed to the creation of new oxide defects or charge trapping into spatially deep states, i.e., oxide traps far away from the SiO 2 /SiC interface.To strengthening this hypothesis, a stress test followed by the recovery phase has been carried out in the case of VGstress = 25 V and 35 V. Figure 5 reports a permanent or slowly recoverable ∆VTH, even after an extended recovery period of approximately 83 h at 150 °C, in the case of VGstress = 35 V, i.e., the bias condition in which ∆VTH shows the occurring of a second slope.On the contrary, a lower stress level of VGstress = 25 V leads to a full recoverable ΔVTH within just a few hours, confirming trapping and de-trapping in shallow pre-existing defects.Focusing on the dynamics of ΔVTH leading to permanent degradation (VGstress ≥ 35 V), it can model by using a power law, as shown in Figure 6.It is worth noting that ΔVTH curves with VGstress > 45 V have not been considered because they are very close to the breakdown voltage.Therefore, the additional observed mechanisms are unlikely to occur under normal operating conditions.Figure 6 illustrates that the effect of the second To strengthening this hypothesis, a stress test followed by the recovery phase has been carried out in the case of V Gstress = 25 V and 35 V. Figure 5 reports a permanent or slowly recoverable ∆V TH , even after an extended recovery period of approximately 83 h at 150 • C, in the case of V Gstress = 35 V, i.e., the bias condition in which ∆V TH shows the occurring of a second slope.On the contrary, a lower stress level of V Gstress = 25 V leads to a full recoverable ∆V TH within just a few hours, confirming trapping and de-trapping in shallow pre-existing defects.To strengthening this hypothesis, a stress test followed by the recovery phase has been carried out in the case of VGstress = 25 V and 35 V. Figure 5 reports a permanent or slowly recoverable ∆VTH, even after an extended recovery period of approximately 83 h at 150 °C, in the case of VGstress = 35 V, i.e., the bias condition in which ∆VTH shows the occurring of a second slope.On the contrary, a lower stress level of VGstress = 25 V leads to a full recoverable ΔVTH within just a few hours, confirming trapping and de-trapping in shallow pre-existing defects.Focusing on the dynamics of ΔVTH leading to permanent degradation (VGstress ≥ 35 V), it can model by using a power law, as shown in Figure 6.It is worth noting that ΔVTH curves with VGstress > 45 V have not been considered because they are very close to the breakdown voltage.Therefore, the additional observed mechanisms are unlikely to occur under normal operating conditions.Figure 6 illustrates that the effect of the second Focusing on the dynamics of ∆V TH leading to permanent degradation (V Gstress ≥ 35 V), it can model by using a power law, as shown in Figure 6.It is worth noting that ∆V TH curves with V Gstress > 45 V have not been considered because they are very close to the breakdown voltage.Therefore, the additional observed mechanisms are unlikely to occur under normal operating conditions.Figure 6 illustrates that the effect of the second mechanism on ∆V TH , whether it is creating new defects or trapping in spatially deeper states, always shows the same power slope (exponent) of n = 0.27, regardless of the gate stress voltage.Consequently, it is possible to assume that the same mechanism occurs even at lower V Gstress , but its impact is masked by trapping in the shallow pre-existing defects during the observed time windows.In particular, by obtaining the scaling factor k (symbols in Figure 7) through fitting the region of ∆V TH experiments with steeper slope (dotted lines in Figure 6), the dependency of k on the gate voltage can be analyzed, resulting in a power-law relationship, as depicted in Figure 7. Consequently, the effect of this second mechanism can be estimated even at gate voltages closer to nominal operation (dashed lines in Figure 6) by deriving k from the model presented in Figure 7, utilizing n = 0.27.For instance, considering a maximum V G = 25 V, the induced ∆V TH due to the creation of new defects is estimated to be roughly 300 mV after 10 years at 150 • C. mechanism on ΔVTH, whether it is creating new defects or trapping in spatially deeper states, always shows the same power slope (exponent) of n = 0.27, regardless of the gate stress voltage.Consequently, it is possible to assume that the same mechanism occurs even at lower VGstress, but its impact is masked by trapping in the shallow pre-existing defects during the observed time windows.In particular, by obtaining the scaling factor k (symbols in Figure 7) through fitting the region of ΔVTH experiments with steeper slope (dotted lines in Figure 6), the dependency of k on the gate voltage can be analyzed, resulting in a power-law relationship, as depicted in Figure 7. Consequently, the effect of this second mechanism can be estimated even at gate voltages closer to nominal operation (dashed lines in Figure 6) by deriving k from the model presented in Figure 7, utilizing n = 0.27.For instance, considering a maximum VG = 25 V, the induced ∆VTH due to the creation of new defects is estimated to be roughly 300 mV after 10 years at 150 °C.By considering the ∆VTH ascribed to the oxide charge trapping (i.e., dotted and dashed lines in Figure 6), the corresponding oxide trapped charge density (∆NOX) is calculated and reported in Figure 8 as a function of VGstress.It is worth noting that the possible mechanism on ΔVTH, whether it is creating new defects or trapping in spatially deeper states, always shows the same power slope (exponent) of n = 0.27, regardless of the gate stress voltage.Consequently, it is possible to assume that the same mechanism occurs even at lower VGstress, but its impact is masked by trapping in the shallow pre-existing defects during the observed time windows.In particular, by obtaining the scaling factor k (symbols in Figure 7) through fitting the region of ΔVTH experiments with steeper slope (dotted lines in Figure 6), the dependency of k on the gate voltage can be analyzed, resulting in a power-law relationship, as depicted in Figure 7. Consequently, the effect of this second mechanism can be estimated even at gate voltages closer to nominal operation (dashed lines in Figure 6) by deriving k from the model presented in Figure 7, utilizing n = 0.27.For instance, considering a maximum VG = 25 V, the induced ∆VTH due to the creation of new defects is estimated to be roughly 300 mV after 10 years at 150 °C.By considering the ∆VTH ascribed to the oxide charge trapping (i.e., dotted and dashed lines in Figure 6), the corresponding oxide trapped charge density (∆NOX) is calculated and reported in Figure 8 as a function of VGstress.It is worth noting that the possible By considering the ∆V TH ascribed to the oxide charge trapping (i.e., dotted and dashed lines in Figure 6), the corresponding oxide trapped charge density (∆N OX ) is calculated and reported in Figure 8 as a function of V Gstress .It is worth noting that the possible creation of new interface and/or border defects is excluded because, as demonstrated in [27], no degradation of the subthreshold slope has been observed (not shown).
Micromachines 2024, 15, 872 7 of 9 creation of new interface and/or border defects is excluded because, as demonstrated in [27], no degradation of the subthreshold slope has been observed (not shown).Finally, a temperature-dependent PBTI analysis has been carried out to calculate the activation energy of the oxide traps inducing permanent or slowly recoverable ∆VTH, hence degradation.In particular, VGstress = 42.5 V has been adopted as it represents the bias condition in which the second ∆VTH slope (trapping mechanism of interest) is clearly visible, whereas the short-term additional mechanism occurring at larger gate biases (close to the breakdown voltages) is almost negligible.As observed from the Arrhenius plot in Figure 9, such oxide defects feature an activation energy of ~80 meV.The relatively shallow energy level combined with the long recovery time (permanent) further confirms the creation of new oxide defects or the trapping in states far away from the SiC/SiO2 interface (spatially deep).Finally, a temperature-dependent PBTI analysis has been carried out to calculate the activation energy of the oxide traps inducing permanent or slowly recoverable ∆V TH , hence degradation .In particular, V Gstress = 42.5 V has been adopted as it represents the bias condition in which the second ∆V TH slope (trapping mechanism of interest) is clearly visible, whereas the short-term additional mechanism occurring at larger gate biases (close to the breakdown voltages) is almost negligible.As observed from the Arrhenius plot in Figure 9, such oxide defects feature an activation energy of ~80 meV.The relatively shallow energy level combined with the long recovery time (permanent) further confirms the creation of new oxide defects or the trapping in states far away from the SiC/SiO 2 interface (spatially deep).
creation of new interface and/or border defects is excluded because, as demonstrated in [27], no degradation of the subthreshold slope has been observed (not shown).Finally, a temperature-dependent PBTI analysis has been carried out to calculate the activation energy of the oxide traps inducing permanent or slowly recoverable ∆VTH, hence degradation.In particular, VGstress = 42.5 V has been adopted as it represents the bias condition in which the second ∆VTH slope (trapping mechanism of interest) is clearly visible, whereas the short-term additional mechanism occurring at larger gate biases (close to the breakdown voltages) is almost negligible.As observed from the Arrhenius plot in Figure 9, such oxide defects feature an activation energy of ~80 meV.The relatively shallow energy level combined with the long recovery time (permanent) further confirms the creation of new oxide defects or the trapping in states far away from the SiC/SiO2 interface (spatially deep).

Conclusions
The positive bias temperature instability of SiC MOSFETs has been analyzed, revealing insights into the underlying mechanisms contributing to ∆V TH .The results demonstrate the importance of characterization methods, with the diode mode approach proving more sensitive to fast pre-existing defects compared with the transistor mode one, because of the reduced V TH measure time, eventually leading to a smaller recovery.The analysis of ∆V TH under different gate stress voltage conditions confirmed the presence of multiple trapping mechanisms, including trapping in pre-existing defects and the creation of new defects or trapping in spatially deeper states.These mechanisms exhibit distinct behaviors at varying V Gstress levels, contributing to permanent or slowly recoverable ∆V TH .Overall, the findings contribute to a deeper understanding of the PBTI phenomena in SiC MOSFETs and provide valuable insights for enhancing device reliability.

Figure 1 .Figure 2 .
Figure 1.ID-VG transfer characteristics of SiC MOSFETs with VG sweep from 0 V to 18 V, VDS and ambient temperature T = 25 °C.

Figure 1 .
Figure 1.I D -V G transfer characteristics of SiC MOSFETs with V G sweep from 0 V to 18 V, V DS = 1 V and ambient temperature T = 25 • C.

Figure 1 .Figure 2 .
Figure 1.ID-VG transfer characteristics of SiC MOSFETs with VG sweep from 0 V to 18 V, V and ambient temperature T = 25 °C.

Figure 2 .
Figure2.Waveforms of PBTI stress and measure procedure in the case of transistor (a) and diode mode (b) method, as reported by JEDEC JEP184 standard[28].Each cycle consists of a logarithmically increasing stress period, conditioning and threshold voltage measurement.

Figure 3 .
Figure 3. ∆VTH during the stress time by means of transistor (blue) and diode mode (red) technique, under different gate stress voltages and T = 150 °C.

Figure 3 .
Figure 3. ∆V TH during the stress time by means of transistor (blue) and diode mode (red) technique, under different gate stress voltages and T = 150 • C.

Figure 4 .
Figure 4. ∆VTH during the stress time as a function of different VGstress, monitored by the transistor mode method, with T = 150 °C.

Figure 5 .
Figure 5. ∆VTH during the stress and recovery time as a function of different gate stress voltages, monitored by the transistor mode technique.Recovery condition: VG = 0 V, T = 150 °C.

Figure 4 .
Figure 4. ∆V TH during the stress time as a function of different V Gstress , monitored by the transistor mode method, with T = 150 • C.

Figure 4 .
Figure 4. ∆VTH during the stress time as a function of different VGstress, monitored by the transistor mode method, with T = 150 °C.

Figure 5 .
Figure 5. ∆VTH during the stress and recovery time as a function of different gate stress voltages, monitored by the transistor mode technique.Recovery condition: VG = 0 V, T = 150 °C.

Figure 5 .
Figure 5. ∆V TH during the stress and recovery time as a function of different gate stress voltages, monitored by the transistor mode technique.Recovery condition: V G = 0 V, T = 150 • C.

Figure 6 .
Figure 6.∆VTH versus the stress time as a function of different VGstress, monitored by the transistor method, with T = 150 °C.Solid lines: experiments.Dashed lines: ∆VTH fitting by means of a power law, considering the second slope/mechanism observable for VGstress > 35 V.A 2.5 V voltage step has been adopted from VGstress = 30 V to VGstress = 45 V.

Figure 7 .
Figure 7. Scaling factor (k) dependence of the gate stress voltage.Symbols: k extrapolated from experiments (Figure6).Line: fitting.The power law provides the smallest fitting error.

Figure 6 .
Figure 6.∆V TH versus the stress time as a function of different V Gstress , monitored by the transistor method, with T = 150 • C. Solid lines: experiments.Dashed lines:∆V TH fitting by means of a power law, considering the second slope/mechanism observable for V Gstress > 35 V.A 2.5 V voltage step has been adopted from V Gstress = 30 V to V Gstress = 45 V.

Figure 6 .
Figure 6.∆VTH versus the stress time as a function of different VGstress, monitored by the transistor method, with T = 150 °C.Solid lines: experiments.Dashed lines: ∆VTH fitting by means of a power law, considering the second slope/mechanism observable for VGstress > 35 V.A 2.5 V voltage step has been adopted from VGstress = 30 V to VGstress = 45 V.

Figure 7 .
Figure 7. Scaling factor (k) dependence of the gate stress voltage.Symbols: k extrapolated from experiments (Figure6).Line: fitting.The power law provides the smallest fitting error.

Figure 7 .
Figure 7. Scaling factor (k) dependence of the gate stress voltage.Symbols: k extrapolated from experiments (Figure6).Line: fitting.The power law provides the smallest fitting error.

Figure 9 .
Figure 9. Arrhenius plot for the ∆VTH measured after 10 4 s of stress in the case of VGstress = 42.5 V.

Figure 8 .
Figure 8. Oxide trapped charge density calculated from ∆V TH data reported in Figure 6 (dashed/dotted lines).

Figure 9 .
Figure 9. Arrhenius plot for the ∆VTH measured after 10 4 s of stress in the case of VGstress = 42.5 V.

Figure 9 .
Figure 9. Arrhenius plot for the ∆V TH measured after 10 4 s of stress in the case of V Gstress = 42.5 V.