Switching Regulator Based on a Non-Inverting Step-Down/Up DC–DC Converter for Lithium-Ion Battery Applications

A regulator based on a converter with step-down/up characteristics is discussed in this paper, which is suitable for processing energy from a lithium-ion battery pack, where the voltage fluctuates from above or below the nominal value. However, this regulator can also be used for applications such as unregulated line rectifiers and renewable energy sources, among others. The converter consists of a non-cascaded interconnection of boost and buck–boost converters such that part of the input energy is transferred directly to the output without reprocessing. Furthermore, it has a non-pulsating input current and a non-inverting output voltage, making it easier to feed the power to other devices. For control purposes, non-linear and linear converter models are derived. The transfer functions of the linear model are used to implement the regulator using a current-mode control scheme. Finally, experimental results for a nominal output voltage of 48 V at 500 W are obtained for the converter in open-loop and closed-loop tests.


Introduction
Step-down and step-up converters are widely used topologies in conventional switching converters [1]; however, with the development of new technologies, applications have arisen where DC-DC converters, including control schemes, that provide both characteristics are necessary.
Among these are systems and vehicles powered by fuel cells [2], by batteries that include both electric vehicles and more electric aircraft (MEA) [3][4][5], as well as mobile telecommunications equipment [6][7][8]. All of them require an interface that regulates the output voltage of the power supply, which fluctuates around its nominal value and supplies a load.
Lithium-ion batteries (LIBs) are used as power sources in electric vehicles, digital cameras, and many other portable devices such as mobile phones, laptops, and medical equipment. However, one of the most common problems is that LIBs require a connection to a voltage regulator to maintain a constant output voltage [9], as shown in Figure 1. A typical case is IoT (Internet of things) devices that need a bus of 3.3 V to regulate the LIB fluctuation from 1.8 V to 5 V [10], or in portable bioelectric equipment such as the cardiac pacemaker and capsule endoscopy [11] where 3.6 V are regulated from a battery fluctuation of 2.5 V to 5 V. Another is the regulator based on a SEPIC converter with a switched inductor proposed in [12] to maintain a fluctuating voltage of 18-24 V to a constant value of 21 V for a laptop. Lithium batteries are preferred over other rechargeable batteries with similar power characteristics because they have a higher energy density. In addition, lithium is a highly reactive element, and LIBs are lighter than other batteries [13]. Connecting LIBs in a pack with different serial or parallel arrangements gives different nominal voltages and current capacities [14]. Power source requirements in many areas have increased over time in electronic systems that have caused the battery requirement of 12 V or 24 V to change to 48 V, such as in powering data centers [15], telecommunications systems, electric vehicles [16], as well as storing energy from renewable sources [17,18]. The nominal 48 V of an LIB pack varies from 40 V when the battery is discharged to 56 V when fully charged. Then, to maintain the constant nominal output voltage, the battery requires regulators based on DC-DC converters.
An essential issue in an LIB pack is the behavior of its output current. High ripple currents, faster charge and discharge periods, or high harmonic currents might reduce the lifetime of the LIB pack and increase heating and the overpotential built-up, negatively affecting the efficiency [19][20][21]. Therefore, the converter selected to implement a regulator must exhibit step-down/up characteristics and a non-pulsating input current. The latter considerably reduce the current ripple demanded from the battery, guaranteeing the best performance of the LIB.
The following review of different topologies of step-down/up converters presented in the technical literature that could suit this application is given. The simplest is the conventional buck-boost converter; however, it has an inverting output voltage, making it challenging to connect other devices to the same power source [22]. Therefore, many noninverting buck-boost converter topologies have been proposed. Based on structures with zero-voltage switching, in [23] is presented a converter with continuous input current but manages a low power of 35 W; meanwhile, in [24], a converter with coupled inductors and a soft switching scheme is proposed, with the drawback of non-continuous input current. Moreover, this class of topologies using synchronous switching is presented in [25,26]. In the first one, the converter has an efficiency near 93% but with a low power of 60 W and a non-continuous input current. The second converter is used only as a buck or boost converter, aiming to increase efficiency. Finally, an interleaving non-inverter buck converter structure for low-power applications is proposed in [27] with the drawback of a non-continuous input current, making it unsuitable for the intended application. Meanwhile, in [28], another interleaving non-inverter structure with three output stages to improve the voltage gain is analyzed. Although this converter has a non-pulsing input current, it also has a very high output gain that is inadequate for regulating an output voltage around an operating value. Other alternatives are the Cuk or SEPIC converters; they have a non-pulsating input current and step-down/up the input voltage capabilities. However, they require semiconductors with a high current stress capacity and high capacitance in the transfer stage [29]. Quadratic step-up/down converters handle a higher voltage gain as 2 (1 − ) 2 ⁄ [30] or (1 − ) 2 ⁄ [31]; however, a simple voltage gain of (1 − ⁄ ) is enough to regulate the voltage fluctuations of an LIB to its nominal value, and both converters are used only to reduce or increase an output voltage. Finally, isolated converters might be considered, but the isolation transformer makes them less efficient, more expensive, and bulkier than the last options. Another alternative solution could be the cascaded Lithium batteries are preferred over other rechargeable batteries with similar power characteristics because they have a higher energy density. In addition, lithium is a highly reactive element, and LIBs are lighter than other batteries [13]. Connecting LIBs in a pack with different serial or parallel arrangements gives different nominal voltages and current capacities [14]. Power source requirements in many areas have increased over time in electronic systems that have caused the battery requirement of 12 V or 24 V to change to 48 V, such as in powering data centers [15], telecommunications systems, electric vehicles [16], as well as storing energy from renewable sources [17,18]. The nominal 48 V of an LIB pack varies from 40 V when the battery is discharged to 56 V when fully charged. Then, to maintain the constant nominal output voltage, the battery requires regulators based on DC-DC converters.
An essential issue in an LIB pack is the behavior of its output current. High ripple currents, faster charge and discharge periods, or high harmonic currents might reduce the lifetime of the LIB pack and increase heating and the overpotential built-up, negatively affecting the efficiency [19][20][21]. Therefore, the converter selected to implement a regulator must exhibit step-down/up characteristics and a non-pulsating input current. The latter considerably reduce the current ripple demanded from the battery, guaranteeing the best performance of the LIB.
The following review of different topologies of step-down/up converters presented in the technical literature that could suit this application is given. The simplest is the conventional buck-boost converter; however, it has an inverting output voltage, making it challenging to connect other devices to the same power source [22]. Therefore, many non-inverting buck-boost converter topologies have been proposed. Based on structures with zero-voltage switching, in [23] is presented a converter with continuous input current but manages a low power of 35 W; meanwhile, in [24], a converter with coupled inductors and a soft switching scheme is proposed, with the drawback of non-continuous input current. Moreover, this class of topologies using synchronous switching is presented in [25,26]. In the first one, the converter has an efficiency near 93% but with a low power of 60 W and a non-continuous input current. The second converter is used only as a buck or boost converter, aiming to increase efficiency. Finally, an interleaving non-inverter buck converter structure for low-power applications is proposed in [27] with the drawback of a non-continuous input current, making it unsuitable for the intended application. Meanwhile, in [28], another interleaving non-inverter structure with three output stages to improve the voltage gain is analyzed. Although this converter has a non-pulsing input current, it also has a very high output gain that is inadequate for regulating an output voltage around an operating value. Other alternatives are the Cuk or SEPIC converters; they have a non-pulsating input current and step-down/up the input voltage capabilities. However, they require semiconductors with a high current stress capacity and high capacitance in the transfer stage [29]. Quadratic step-up/down converters handle a higher voltage gain as D 2 /(1 − D) 2 [30] or D/(1 − D) 2 [31]; however, a simple voltage gain of D/(1 − D) is enough to regulate the voltage fluctuations of an LIB to its nominal value, and both converters are used only to reduce or increase an output voltage. Finally, isolated converters might be considered, but the isolation transformer makes them less efficient, more expensive, and bulkier than the last options. Another alternative solution could be the cascaded connection of boost and buck converters; however, the power processed by the boost converter will be processed by the buck converter resulting in poor efficiency.
Based on the above, it is concluded that a non-cascading connection of simple converters could be a better solution. In these topologies, part of the energy is processed only by one converter; thus, they have reduced redundant power processing (r 2 p 2 ) [32,33]. To carry out the analysis, a converter made up of two stages can be represented by three ports, as shown in Figure 2: the input port or source that supplies energy, the storage port or capacitor that stores energy but also delivers it, and the output port or load that only absorbs power. connection of boost and buck converters; however, the power processed by the boost converter will be processed by the buck converter resulting in poor efficiency. Based on the above, it is concluded that a non-cascading connection of simple converters could be a better solution. In these topologies, part of the energy is processed only by one converter; thus, they have reduced redundant power processing (r 2 p 2 ) [32,33]. To carry out the analysis, a converter made up of two stages can be represented by three ports, as shown in Figure 2: the input port or source that supplies energy, the storage port or capacitor that stores energy but also delivers it, and the output port or load that only absorbs power. In a cascade connection of converters, the first stage processes all the input energy and then delivers it to the storage port; and the second stage processes the energy from the storage port and sends it to the output. Therefore, the two stages process all the energy. However, when part of the power taken from the source goes directly to the output port, that is, it is only processed by one stage, there is a converter with a non-cascade structure or reduced redundant power processing converter.
There are fifteen configurations in how to interconnect two converters with r 2 p 2 . A deep study about which configurations are feasible and non-feasible is developed using the buck, boost, and buck-boost converters [34,35]. Following the possible configurations, a converter based on a non-cascading interconnection with two stages is built; the first stage is a boost converter, and the second is a buck-boost converter, as shown in Figure 2. The structure can be simplified for better visualization, as shown in Figure 3, in which represents the input voltage and VO the output voltage. The transfer capacitor is represented by 1 , and the output capacitor by 2 . The inductor of the first stage is 1 , and the inductor of the second stage is 2 . The MOSFETs 1 and 2 are the active switches operating simultaneously; 1 and 2 are the diodes; and is the load. Thus, the resulting converter to be used in the regulator has the following advantages: In a cascade connection of converters, the first stage processes all the input energy and then delivers it to the storage port; and the second stage processes the energy from the storage port and sends it to the output. Therefore, the two stages process all the energy. However, when part of the power taken from the source goes directly to the output port, that is, it is only processed by one stage, there is a converter with a non-cascade structure or reduced redundant power processing converter.
There are fifteen configurations in how to interconnect two converters with r 2 p 2 . A deep study about which configurations are feasible and non-feasible is developed using the buck, boost, and buck-boost converters [34,35]. Following the possible configurations, a converter based on a non-cascading interconnection with two stages is built; the first stage is a boost converter, and the second is a buck-boost converter, as shown in Figure 2. The structure can be simplified for better visualization, as shown in Figure 3, in which E represents the input voltage and V O the output voltage. The transfer capacitor is represented by C 1 , and the output capacitor by C 2 . The inductor of the first stage is L 1 , and the inductor of the second stage is L 2 . The MOSFETs M 1 and M 2 are the active switches operating simultaneously; D 1 and D 2 are the diodes; and R is the load.
connection of boost and buck converters; however, the power processed by the boost converter will be processed by the buck converter resulting in poor efficiency.
Based on the above, it is concluded that a non-cascading connection of simple converters could be a better solution. In these topologies, part of the energy is processed only by one converter; thus, they have reduced redundant power processing (r 2 p 2 ) [32,33]. To carry out the analysis, a converter made up of two stages can be represented by three ports, as shown in Figure 2: the input port or source that supplies energy, the storage port or capacitor that stores energy but also delivers it, and the output port or load that only absorbs power. In a cascade connection of converters, the first stage processes all the input energy and then delivers it to the storage port; and the second stage processes the energy from the storage port and sends it to the output. Therefore, the two stages process all the energy. However, when part of the power taken from the source goes directly to the output port, that is, it is only processed by one stage, there is a converter with a non-cascade structure or reduced redundant power processing converter.
There are fifteen configurations in how to interconnect two converters with r 2 p 2 . A deep study about which configurations are feasible and non-feasible is developed using the buck, boost, and buck-boost converters [34,35]. Following the possible configurations, a converter based on a non-cascading interconnection with two stages is built; the first stage is a boost converter, and the second is a buck-boost converter, as shown in Figure 2. The structure can be simplified for better visualization, as shown in Figure 3, in which represents the input voltage and VO the output voltage. The transfer capacitor is represented by 1 , and the output capacitor by 2 . The inductor of the first stage is 1 , and the inductor of the second stage is 2 . The MOSFETs 1 and 2 are the active switches operating simultaneously; 1 and 2 are the diodes; and is the load. Thus, the resulting converter to be used in the regulator has the following advantages: Thus, the resulting converter to be used in the regulator has the following advantages:

•
Step-down/up voltage with the non-cascade interconnection of stages, that increase power processing efficiency; • Low number of active and passive switches as well as electrical components; • Non-pulsating input current; • Non-inverting output voltage; • The input and output share a common ground.
This paper aims to develop a procedure to design a switching regulator based on a noninverting step-down/up converter for an LIB pack, as shown in Figure 1. Waveforms of the main variables of the converter, a detailed procedure to obtain its output-to-input-voltage relationship and mathematical expressions for an appropriate parameter selection based on steady-state analysis, and dynamical models to design a control scheme are derived for the converter. Finally, the switching regulator is designed using loop-shaping techniques. The outline of this paper is as follows: In Section 2, the structure of the converter and its operation are studied; then, steady-state and semiconductor stress expressions are obtained, as well as relationships for an adequate selection of components. In Section 3, nonlinear and linear models are developed to describe the dynamical behavior of the converter where the transfer functions of interest are obtained. Section 4 gives expressions to calculate the power losses in each component. In Section 5, a current-mode scheme is proposed to control the converter. In Section 6, open-loop and closed-loop experimental results are shown. Finally, in Section 7, conclusions and remarks are provided.

Steady State Response
The non-inverting step-down/up converter shown in Figure 3 is assumed to operate in continuous conduction mode (CCM), which means that the inductor currents never decay to zero. The active switches M 1 and M 2 operate simultaneously. The electrical circuits are shown in Figure 4 and the resulting wave forms in Figure 5, when they are ON and OFF.

•
Non-pulsating input current; • Non-inverting output voltage; • The input and output share a common ground.
This paper aims to develop a procedure to design a switching regulator based on a non-inverting step-down/up converter for an LIB pack, as shown in Figure 1. Waveforms of the main variables of the converter, a detailed procedure to obtain its output-to-inputvoltage relationship and mathematical expressions for an appropriate parameter selection based on steady-state analysis, and dynamical models to design a control scheme are derived for the converter. Finally, the switching regulator is designed using loop-shaping techniques. The outline of this paper is as follows: In Section 2, the structure of the converter and its operation are studied; then, steady-state and semiconductor stress expressions are obtained, as well as relationships for an adequate selection of components. In Section 3, nonlinear and linear models are developed to describe the dynamical behavior of the converter where the transfer functions of interest are obtained. Section 4 gives expressions to calculate the power losses in each component. In Section 5, a current-mode scheme is proposed to control the converter. In Section 6, open-loop and closed-loop experimental results are shown. Finally, in Section 7, conclusions and remarks are provided.

Steady State Response
The non-inverting step-down/up converter shown in Figure 3 is assumed to operate in continuous conduction mode (CCM), which means that the inductor currents never decay to zero. The active switches 1 and 2 operate simultaneously. The electrical circuits are shown in Figure 4 and the resulting wave forms in Figure 5, when they are ON and OFF.   The ON state is shown in Figure 4a, for a time corresponding to DT in which D represents the duty cycle and T the period of a switching cycle of the converter, respectively; 1 and 2 are closed; and 1 and 2 are reverse biased. It is possible to identify three different parallel connections-the source with inductor 1 L , capacitor 1 C with inductor 2 L , and capacitor 2 C with load R-so both inductors charge energy, and both capacitors release energy. Thus, in this condition: (2) and the relationship for the voltage of the first inductor can be written as: Meanwhile, the relationship for the second inductor is given by: Therefore, the current ripple of the first inductor during charging is: and for the second inductor is: The ON state is shown in Figure 4a, for a time corresponding to DT in which D represents the duty cycle and T the period of a switching cycle of the converter, respectively; M 1 and M 2 are closed; and D 1 and D 2 are reverse biased. It is possible to identify three different parallel connections-the source with inductor L 1 , capacitor C 1 with inductor L 2 , and capacitor C 2 with load R-so both inductors charge energy, and both capacitors release energy. Thus, in this condition: and the relationship for the voltage of the first inductor can be written as: Meanwhile, the relationship for the second inductor is given by: Therefore, the current ripple of the first inductor during charging is: and for the second inductor is: In the OFF state, for a time corresponding to (1 − D)T, M 1 and M 2 are open, and D 1 and D 2 are forward biased; therefore, both inductors discharge and capacitors charge. In this condition: and The relationship for the first inductor voltage is now: and for the second one is: Therefore, the current ripple of the first inductor during discharging is given as: and the ripple for second inductor is: Because in the inductor the charge ripple is equal to the discharge ripple, ∆i LC + ∆i LD = 0 results in the following expression: which can by simplified as: By using the same procedure for the second inductor, the following expression is obtained: which can by simplified as: Finally, as V C2 = V O , the voltage gain results in: This expression is plotted and shown in Figure 6. Here, it can be observed that when 0 < D < 0.5, the converter demonstrates step-down behavior because V O /E < 1, and when 0.5 < D < 1, the converter demonstrates step-up behavior because V O /E > 1.
This expression is plotted and shown in Figure 6. Here, it can be observed that when 0 < D < 0.5, the converter demonstrates step-down behavior because , and when 0.5 < D< 1, the converter demonstrates step-up behavior because The expressions for the average voltages in capacitors and average currents in inductors can be computed by: The values of inductors and capacitors are computed using the following expressions: where is the switching frequency, ∆ 1 and ∆ 2 stand for the inductor current ripples, and ∆ 1 and ∆ 2 stand for the capacitor voltage ripples. For simplicity, the The expressions for the average voltages in capacitors and average currents in inductors can be computed by: and The values of inductors and capacitors are computed using the following expressions: and where f S is the switching frequency, ∆I L1 and ∆I L2 stand for the inductor current ripples, and ∆V C1 and ∆V C2 stand for the capacitor voltage ripples. For simplicity, the voltage drops caused by the switching devices were neglected. To guarantee the operation in CCM, the inductors must satisfy the following inequalities: and If some of the inductors do not satisfy this inequality or the resistance R changes considerably, the operation mode of the converter can change to discontinuous conduction mode. Calculating the voltage and current stress of the semiconductor components is essential. For example, the voltage stress in the active and passive switches are computed by: Meanwhile, the current stresses are given by: and

Component Selection
When designing a converter, specifications must be met regarding the values of the voltage ripple in the capacitors and the output voltage, as well as the current ripple in the inductors; these specifications are expressed as percentages. The voltage ripple percentage for the capacitor voltage is given by the relationship ε% = (∆V Ci /2V Ci ) · 100 with a typical value in a conventional converter [22] between 1% and 2%, and the inductor ripple percentage for the current that flows through them by ε% = (∆I Li /2I Li ) · 100 with a typical value between 15% and 30%.
By using the expressions given in (18) to (21) and (22) to (25), it is possible to calculate the corresponding values for the inductors and capacitors. The resulting expressions are shown in Table 1. Table 1. Expressions to design the components of the converter.

Component
Relationship As stated in Section 2.1, inductors L 1 and L 2 must satisfy inequalities (26) and (27) to guarantee CCM.

Modeling and Dynamical Analysis of Step-Down/Up Converter
The dynamical behaviour of the converter is described through mathematical models. It allows for designing a control strategy so the converter can regulate fluctuations in the input voltage and output load and compensate for the parasitic uncertainties.
First, a bilinear piecewise model is obtained. It uses the electric circuits formed with the ON and OFF states of the active switches shown in Figure 4. Then, equations that describe these circuits are calculated and put together through a binary switching function denoted by q, where q = 1 represents the ON state while q = 0 represents the OFF state.
The capacitor voltages and the inductor currents are the four state variables. The resulting model is given by: Now, the nonlinear average model can be derived [36] using the average value of each state variable represented by a superscript "−" and the average value of the variable q represented by the duty cycle d. Here, the state variables are multiplied by the duty cycle; therefore, the resulting system is nonlinear: Finally, linearization techniques are applied to describe the dynamics of the converter. Model (34) is linearized around the operating point corresponding to the steady-state values given by (18) to (21). The control signal and four state variables are decomposed into two parts: the nominal average values, which are denoted by upper-case letters, and their corresponding deviations, which are denoted by letters with a superscript "∼". The resulting linearized model is: Using the Laplace transforms in the average linear model (35), the transfer function of the input current i L1 and the output voltage v O with respect to the duty cycle d are computed for control purposes: and where: When the numerator and denominator polynomials of both transfer functions were analyzed, it was found that all the poles are located in the left-hand side (LHS) of the s-plane. Furthermore, the transfer function i L1 (s)/ d(s) has a minimum phase behavior because it has its zeros in the LHS of the s-plane, and v O (s)/ d(s) has a non-minimum phase behavior because it has zeros in the right-hand side (RHS) of the s-plane. The non-minimum phase behavior makes this converter more challenging to control because a high-gain controller might cause instability [37].

Efficiency Analysis
One of the most important features of power converters is their efficiency. High efficiency leads to a more reliable converter with a reduced cost and size. The power losses of each converter component are caused by their parasitic elements. The main parasitic element of the step-down/up converter is shown in Figure 7. The corresponding equivalent series resistance of L 1 , L 2 , C 1 , C 2 , M 1 , and M 2 are represented by R L1 , R L2 , R C1 , R C2 , R M1 , and R M2 , respectively. The voltage drops caused by diodes D 1 and D 2 are V FD1 and V FD2 . Step-down/up converter with parasitic elements.
Based on the expressions given in [38], the power losses of the step-down/up converter are derived in Table 2. The effective currents 1 and 2 are used to compute the power losses of 1 and 2 ; their values are given by:  The values of 1 and 2 are the turn ON times of 1 and 2 , respectively. The values of 1 and 2 are the turn OFF times. The sum of the individual power losses is the total power loss _ given by: If the output power and the total power losses _ are defined, the estimated efficiency can be computed by: The purpose of estimating the efficiency is to obtain a good approximation of the true efficiency of a regulator.
In addition to the losses due to parasitic resistances, in the case of inductors, the losses in the magnetic core must be considered. Therefore, the Ridley-Nace equation given in Based on the expressions given in [38], the power losses of the step-down/up converter are derived in Table 2. The effective currents I C1 RMS and I C2 RMS are used to compute the power losses of C 1 and C 2 ; their values are given by:

Component Power Loss Equation
The values of t rr1 and t rr2 are the turn ON times of M 1 and M 2 , respectively. The values of t f f 1 and t f f 2 are the turn OFF times.
The sum of the individual power losses is the total power loss P L_T given by: If the output power P and the total power losses P L_T are defined, the estimated efficiency η cal can be computed by: The purpose of estimating the efficiency is to obtain a good approximation of the true efficiency of a regulator.
In addition to the losses due to parasitic resistances, in the case of inductors, the losses in the magnetic core must be considered. Therefore, the Ridley-Nace equation given in [39] is used to calculate the magnetic flux in each inductor employing the relationship B = (L∆I L )/(zS f e ), in which z is the number of turns and S fe is the cross-section area of the core [40].
A comparison of the proposed converter with converters for similar applications given in the references of the introduction is provided in Table 3. In addition, the efficiency of the proposed converter is obtained experimentally and shown for different loads in Section 6. The proposed converter has better efficiency than the converters [9,12]. Conversely, the converter [10] has better efficiency but was computed using a software simulator. Moreover, it has a higher total device count, a limited voltage gain range, and a more complex control scheme because it uses six active switches. The efficiency of the converter described in [24] was also obtained using only simulation. Regarding references [24] and [25], these converters have a pulsating current and are unsuitable for the proposed application. Still, they also have a lower efficiency even though, in [25], two efficiencies are obtained, the first for a circuit based on conventional devices and the second using GaN devices, which are used to improve it. Furthermore, quadratic buck-boost converters [30] and [31] are unsuitable for the intended application, and, given their voltage gain, they are used as buck or boost converters exclusively. Finally, it is important to notice that the power managed for the proposed converter 500 W is higher than that handled by all the previously mentioned converters.

Control Design
The dynamic behavior of switching converters is non-linear; however, linear models can be used for the controller design. Furthermore, the implementation of linear controllers is more straightforward and less expensive than non-linear controllers [41]. Therefore, a linear control scheme is selected.
As described in the previous section, v O (s)/ d(s) has a non-minimum phase behavior but i L1 (s)/ d(s) has a minimum phase behavior. Therefore, a current-mode controller is appropriate for this converter. This control scheme is shown in Figure 8, where the input current is feedback in the inner loop and the output voltage in the outer loop [42]. The controller design procedure is based on loop-shaping techniques applied to outer loop gain, which is obtained by the product of its transfer function.

Control Design
The dynamic behavior of switching converters is non-linear; however, linear models can be used for the controller design. Furthermore, the implementation of linear controllers is more straightforward and less expensive than non-linear controllers [41]. Therefore, a linear control scheme is selected.
As described in the previous section, has a non-minimum phase behavior but ̃1( )/̃( ) has a minimum phase behavior. Therefore, a current-mode controller is appropriate for this converter. This control scheme is shown in Figure 8, where the input current is feedback in the inner loop and the output voltage in the outer loop [42]. The controller design procedure is based on loop-shaping techniques applied to outer loop gain, which is obtained by the product of its transfer function. The following conditions should be satisfied for robust stability: 1. The slope at or near crossover frequency must be not more than −20 dB/dec; 2. The gain at low frequencies should be high to enhance steady-state accuracy; and 3. Appropriate gain and phase margins are required.
The procedure to design each loop, select the gain values [42], and therefore allow to choose the components of the controller circuit, are described below:

Inner Loop
This loop produces a faster transient response and uses a high-gain compensator G(s), a low-pass filter F(s), a sensor gain N, and an oscillator ramp . Here, the average input inductor current follows the reference current.
The expression for this loop is given by: For good results, the zero of compensator () Gs has to be placed at least a decade below half of switching frequency fS, whereas the low-pass filter pole should to be placed either at half of fS or above. The relationships with controller circuit elements, shown in Section 6, are given by The compensator gain is designed so that the inner (current) loop gain has a value close to 10 at frequencies around the zero of G(s). The above criterion is satisfied with the following compensator gain: (1 ) The following conditions should be satisfied for robust stability: 1. The slope at or near crossover frequency must be not more than −20 dB/dec; 2. The gain at low frequencies should be high to enhance steady-state accuracy; and 3. Appropriate gain and phase margins are required.
The procedure to design each loop, select the gain values [42], and therefore allow to choose the components of the controller circuit, are described below:

Inner Loop
This loop produces a faster transient response and uses a high-gain compensator G(s), a low-pass filter F(s), a sensor gain N, and an oscillator ramp V p . Here, the average input inductor current follows the reference current.
The expression for this loop is given by: For good results, the zero of compensator G(s) has to be placed at least a decade below half of switching frequency f S , whereas the low-pass filter pole should to be placed either at half of f S or above. The relationships with controller circuit elements, shown in Section 6, are given by ω Z = 1/R FZ C FZ and ω P = (C FZ + C FP )/R FZ C FZ C FP .
The compensator gain is designed so that the inner (current) loop gain has a value close to 10 at frequencies around the zero of G(s). The above criterion is satisfied with the following compensator gain: As noticed, the gain G p has to be robust to changes in the output load. This condition is reached if the G p value is multiplied by a factor of 8 to 10. In the physical circuit, G p is adjusted through the relationship of resistances R FZ /R 1F .

Outer Loop
This loop is used for output voltage regulation and is designed once the inner loop has been tuned. It uses a PI-controller K(s) and a sensor voltage gain H, so the output voltage is followed by the reference voltage v re f . The expression of this loop is given by: The purpose of K(s) is to provide a high gain to the controller at low frequencies; thus, integrative time T i is selected to place the pole of K(s) a decade below f s , while the gain is selected to obtain the appropriate gain and phase margins of the voltage loop. The expressions for the controller shown in Section 6 are T i = R FC C FC , and the gain K p is given by: This gain is adjusted in the controller circuit by R FC /R 1C . It is important to notice that expressions (42) and (44) provide a first approximation of inner and outer loop controller gains; subsequently, an iterative tuning process has to be carried out to guarantee the appropriate robust stability of the regulator.

Experimental Results
As mentioned in the introduction, new applications have increased power requirements. The battery requirement of 12 V or 24 V is changing to 48 V. Thus, a prototype designed in the laboratory to validate the theoretical analysis of the step-down/up converter regulates a nominal 48 V output voltage at 500 W, which could come from an LIB pack. The photo of the experimental prototype is shown in Figure 9. Next, the converter parameters are shown in Table 4. Then, using the expressions derived in Section 2, the component values of the converter parameters are chosen and listed in Table 5. As noticed, the gain Gp has to be robust to changes in the output load. This condition is reached if the Gp value is multiplied by a factor of 8 to 10. In the physical circuit, Gp is adjusted through the relationship of resistances RFZ/R1F.

Outer Loop
This loop is used for output voltage regulation and is designed once the inner loop has been tuned. It uses a PI-controller K(s) and a sensor voltage gain H, so the output voltage is followed by the reference voltage . The expression of this loop is given by: The purpose of () Ks is to provide a high gain to the controller at low frequencies; thus, integrative time i T is selected to place the pole of () Ks a decade below fs, while the gain is selected to obtain the appropriate gain and phase margins of the voltage loop. The expressions for the controller shown in Section 6 are i FC FC T R C = , and the gain p K is given by: This gain is adjusted in the controller circuit by RFC/R1C. It is important to notice that expressions (42) and (44) provide a first approximation of inner and outer loop controller gains; subsequently, an iterative tuning process has to be carried out to guarantee the appropriate robust stability of the regulator.

Experimental Results
As mentioned in the introduction, new applications have increased power requirements. The battery requirement of 12 V or 24 V is changing to 48 V. Thus, a prototype designed in the laboratory to validate the theoretical analysis of the step-down/up converter regulates a nominal 48 V output voltage at 500 W, which could come from an LIB pack. The photo of the experimental prototype is shown in Figure 9. Next, the converter parameters are shown in Table 4. Then, using the expressions derived in Section 2, the component values of the converter parameters are chosen and listed in Table 5.

Parameter
Value E 40-56 V VO 48 V Figure 9. Prototype of the step-down/up converter built in the laboratory. Table 4. Parameters of the converter.

Parameter Value
0.2I L1 (20% peak to peak ripple) ∆I L2 0.3I L2 (30% peak to peak ripple) ∆V C1 0.02V C1 (2% peak to peak ripple) ∆V C2 0.02V C2 (2% peak to peak ripple) The selected values were used to compute the transfer functions (20) and (21). The resulting poles and zeros of both transfer functions are shown in Table 6. The transfer function input current-to-duty cycle has a minimum phase behavior because all zeros are in the LHS. On the other hand, the transfer function output voltage-to-duty cycle has a non-minimum phase behavior because it has zeros in the RHS. Table 6. Location of poles and zeros of the transfer functions.

Transfer Function
Poles Zeros A current-mode controller is designed for the step-down/up converter, which is shown in Figure 10. In the inner current loop, the sensor gain is N = 0.25, and the high-gain compensator has a gain G P = 1.19 with a pole located at ω Z = 17,857 rad/s. The pole of the low-pass filter is located at ω P = 314,259 rad/s. In the outer voltage loop: the sensor gain value is H = 0.15, and the PI-controller has a gain of K P = 0.1 with an integrative time of T i = 350 µs. The high inrush current produced when the converter is initially powered up, can be avoided using an RC circuit to feed the reference voltage v REF .

Open Loop Test
The converter prototype is tested in an open loop to validate the steady-state expressions, transfer functions, and the behavior to load changes. The steady-state values of the prototype are computed according to their corresponding expression: 1 = 10.41 A, 2 = 10.41 A, 1 = 48 V, and VO = 48 V. Now, measuring the steady-state values from the prototype in the laboratory, the experimental inductor currents are shown in Figure  11. The average inductor currents are: 1 = 11.5 A and 2 = 10.41 A with 20% and 30% of ripples, respectively. The experimental value 1 slightly differs from its theoretical

Open Loop Test
The converter prototype is tested in an open loop to validate the steady-state expressions, transfer functions, and the behavior to load changes. The steady-state values of the prototype are computed according to their corresponding expression: I L1 = 10.41 A, I L2 = 10.41 A, V C1 = 48 V, and V O = 48 V. Now, measuring the steady-state values from the prototype in the laboratory, the experimental inductor currents are shown in Figure 11. The average inductor currents are: I L1 = 11.5 A and I L2 = 10.41 A with 20% and 30% of ripples, respectively. The experimental value I L1 slightly differs from its theoretical value because of the parasitic elements. Figure 10. Circuit diagram of the current-mode controller for the switching regulator.

Open Loop Test
The converter prototype is tested in an open loop to validate the steady-state expressions, transfer functions, and the behavior to load changes. The steady-state values of the prototype are computed according to their corresponding expression: 1 = 10.41 A 2 = 10.41 A, 1 = 48 V, and VO = 48 V. Now, measuring the steady-state values from the prototype in the laboratory, the experimental inductor currents are shown in Figure  11. The average inductor currents are: 1 = 11.5 A and 2 = 10.41 A with 20% and 30% of ripples, respectively. The experimental value 1 slightly differs from its theoretical value because of the parasitic elements. The experimental capacitor voltages are shown in Figure 12; they match the calculated values. A zoom for the voltage O v is measured to watch its ripple (see Figure 13) and it matches with the required 2% peak-to-peak ripple. These results validate the calculated design relationships. The experimental voltage values on the semiconductor switching devices are shown in Figure 14; they verify the expected stress calculated by the expressions obtained in Section 2. The experimental capacitor voltages are shown in Figure 12; they match the calculated values. A zoom for the voltage v O is measured to watch its ripple (see Figure 13) and it matches with the required 2% peak-to-peak ripple. These results validate the calculated design relationships. The experimental voltage values on the semiconductor switching devices are shown in Figure 14; they verify the expected stress calculated by the expressions obtained in Section 2.          The converter is tested in an open loop to step changes in the load. The circuit used is depicted in Figure 10 inside the block called load. The load changes from R 1 ||R 2 = 4.6 Ω (500 W) when the MOSFET M C is ON to R 1 = 23 Ω (100 W) when the MOSFET M C is OFF at a frequency of 5 Hz. The output voltage response to those changes is shown in Figure 15. It can be noticed that the output voltage varies when load changes occur. Therefore, a controller is needed to attenuate those variations.
Using the Frequency Response Analyzer 300 from AP Instruments, an experimental response of the transfer function v O (s)/ d(s) is obtained for the prototype. It is compared with the response obtained from the linear model using MATLAB software, as shown in Figure 16. The converter is tested in an open loop to step changes in the load. The circuit used is depicted in Figure 10 inside the block called load. The load changes from 1 || 2 = 4.6 Ω (500 W) when the MOSFET is ON to 1 = 23 Ω (100 W) when the MOSFET is OFF at a frequency of 5 Hz. The output voltage response to those changes is shown in Figure 15. It can be noticed that the output voltage varies when load changes occur. Therefore, a controller is needed to attenuate those variations.

Closed-Loop Test
When the voltage loop is closed, it is crucial to guarantee an adequate gain margin, phase margin, and crossover slope at 0 dB of the voltage loop gain. Using the Frequency Response Analyzer 300, the experimental frequency response of the voltage loop gain is obtained and depicted in Figure 17. It exhibits a crossover slope at 0 dB of about 20 dB/dec, a phase margin of 90 degrees, and a gain margin of 8 dB. Thus, robust stability is achieved in the switching regulator.
With the controller enabled, the load was again changed from R 1 ||R 2 = 4.6 Ω (500 W) when the M C MOSFET is ON to R 1 = 23 Ω (100 W) when the M C MOSFET is OFF at a frequency of 5 Hz. The controller maintains the output voltage regulated despite load variations, as it is shown in Figure 18. Furthermore, a fluctuation in the input voltage from 40 V to 56 V is applied to show the behavior of the controller with input voltage fluctuations, as shown in Figure 19. It can be noticed that the controller maintains the output voltage regulated at 48 V despite changes in the input voltage.
When the voltage loop is closed, it is crucial to guarantee an adequate gain margin, phase margin, and crossover slope at 0 dB of the voltage loop gain. Using the Frequency Response Analyzer 300, the experimental frequency response of the voltage loop gain is obtained and depicted in Figure 17. It exhibits a crossover slope at 0 dB of about 20 dB/dec, a phase margin of 90 degrees, and a gain margin of 8 dB. Thus, robust stability is achieved in the switching regulator. With the controller enabled, the load was again changed from R1||R2 = 4.6 Ω (500 W) when the MC MOSFET is ON to R1 = 23 Ω (100 W) when the MC MOSFET is OFF at a frequency of 5 Hz. The controller maintains the output voltage regulated despite load variations, as it is shown in Figure 18. Furthermore, a fluctuation in the input voltage from 40 V to 56 V is applied to show the behavior of the controller with input voltage fluctuations, as shown in Figure 19. It can be noticed that the controller maintains the output voltage regulated at 48 V despite changes in the input voltage. gate voltage of the MOSFET that changes the load from 100 W to 500 W (y-axis: 10 V/div) (x-axis: time 100 ms/div).  With the controller enabled, the load was again changed from R1||R2 = 4.6 Ω (500 W) when the MC MOSFET is ON to R1 = 23 Ω (100 W) when the MC MOSFET is OFF at a frequency of 5 Hz. The controller maintains the output voltage regulated despite load variations, as it is shown in Figure 18. Furthermore, a fluctuation in the input voltage from 40 V to 56 V is applied to show the behavior of the controller with input voltage fluctuations, as shown in Figure 19. It can be noticed that the controller maintains the output voltage regulated at 48 V despite changes in the input voltage. gate voltage of the MOSFET that changes the load from 100 W to 500 W (y-axis: 10 V/div) (x-axis: time 100 ms/div). Finally, the estimated and experimental efficiencies for this converter were computed. The parasitic elements used to calculate efficiency are shown in the second column of Table 7. These values were obtained from the manufacturer's datasheet of each component, whose serial number is shown in Table 4. Then, the individual losses are computed using the expressions obtained in Section 5. Finally, the results are shown in the third Finally, the estimated and experimental efficiencies for this converter were computed. The parasitic elements used to calculate efficiency are shown in the second column of Table 7. These values were obtained from the manufacturer's datasheet of each component, whose serial number is shown in Table 4. Then, the individual losses are computed using the expressions obtained in Section 5. Finally, the results are shown in the third column of Table 6. Moreover, the power core losses are included (P LMC ). According to the sum of the individual losses, the total power loss for the prototype is 49.57 W for a power output of 500 W. Evaluating the expression (23), the corresponding estimated efficiency is η cal = 91%. Using a procedure similar to the one developed in Table 7, calculations were made to obtain the power losses and the estimated power efficiency from 100 W to 500 W; the results are shown in Table 8. Then, the experimental efficiency is obtained by measuring the input and the output power from the prototype at different loads, and it is compared with the estimated efficiency, as shown in Figure 20. It can be noticed that, in a full load (500 W), the experimental efficiency is 90.5%. Therefore, the estimated efficiency gives a good approximation of the experimental efficiency. Most of the power losses are in the active switches. Moreover, as can be seen, the efficiency remains almost the same for the suggested power range.

Concluding Remarks
This paper discusses a switching regulator based on a non-inverter output voltage converter, consisting of the non-cascading connection of two converters where part of the energy is processed by only one converter. The converter has two active switches that

Concluding Remarks
This paper discusses a switching regulator based on a non-inverter output voltage converter, consisting of the non-cascading connection of two converters where part of the energy is processed by only one converter. The converter has two active switches that operate simultaneously with the same duty cycle. The proposed topology can be used when stepping up and down characteristics are required. This converter is suitable when the regulator works as an interface between a lithium-ion battery pack and a load. An improvement in the lifetime of the LIBs will result due to the non-pulsating input current of the converter. The expressions to find the values of circuit elements for this converter are given. For dynamic analysis, the transfer functions of the linear models were derived. A procedure based on loop-shaping techniques was used to design a 500 W regulator for an output voltage of 48 V. The prototype was tested in an open loop and a closed loop. Plots of the steady-state values, output voltage ripple, frequency responses, and input disturbance rejection were obtained. The experimental results validate the steady-state expressions; furthermore, they demonstrate the proper operation of the converter. Responses to load changes and input voltage variations validate the design of the controller. The estimation of the efficiency of the step-down/up converter approximates the experimental efficiency quite well. Funding: This work was supported by the Consejo Nacional de Ciencia y Tecnologia, Mexico. Academic Scholarship for doctorate: 614339.

Data Availability Statement:
The data that support the findings of this study are available from the corresponding author, upon reasonable request.

Conflicts of Interest:
The authors declare no conflict of interest.