Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.


Introduction
Due to the difficulties associated with the scaling of silicon transistors, various technologies have been investigated as the feasible alternatives. The existing complementary metal-oxide semiconductor (CMOS) technology faces many critical issues, such as highpower dissipation, short channel effects, and reduced gate control when scaled to nanoscale dimensions. These reliability issues significantly degrade the system's performance. However, CNFETs seem to provide better performance because of their increased carrier velocity, excellent carrier mobility, and greater trans-conductance [1]. In addition, CNFETs offer great promise to the design of Multi-Valued Logic (MVL) circuits with the ability to adjust the desired threshold voltages.

How to Produce Logic 1 (V dd /2) in Ternary Circuits?
The hard way is how to produce logic 1 in ternary circuits. One technique consists in using a voltage divider to generate logic 1 (V dd /2) from one power supply (V dd ) by inserting two diode-connected transistors acting like resistors; however, this technique produces a direct current path from the power supply (V dd ) to the ground and generates static power dissipation as shown in Equation (1a) of the general equation of the total power consumption (1), whereas the dynamic power is shown in Equation (1b).
Static : P s = P leakage + k1 * N * V 2 dd /R (1a) where: To illustrate that, in Figure 1, we will analyze the static power and the dynamic power of the Standard Ternary Inverter (STI) [7], which is a classic example of generating logic (1) from a single source .  In this paper, we use the alternative solution with two power supplies (V dd and V dd /2) to remove these two diode-connected transistors to eliminate the static power; however, the drawback is the increase in interconnections.

Literature Review
Many articles proposed different methodologies to design TFAs based on CNFET. Table 1 presents the techniques and the limitations for the most important latest ones. Additionally, we will describe them as follows: (1) Implement the conventional design by converting the ternary inputs to intermediate binary bits using Ternary Decoders (TDecoders), then using binary gates, and, lastly, using ternary encoders to produce the final ternary outputs. This method will generate a high transistor count and PDP, as observed in the following papers: Authors of [7] created a TFA with 412 CNFETs. In [8], the authors presented a TFA with 337 CNFETs and 14 RRAMs (Resistive Random Access Memory). (2) Use algorithms for logic synthesis. This strategy will result in a large transistors count connected in series, resulting in high propagation delays and PDP. Papers using this approach are: Authors of [9] represented a TFA with 105 CNFETs using two custom algorithms to generate unary operators and cascading TMUXs. Authors of [10] showed a TFA with 98 CNFETs using a Ternary-Transformed Binary Decision Diagram (TBDD) algorithm, and the authors of [11] represented a TFA with 106 CNFETs using a modified Quine-McCluskey and post-optimization algorithms. (3) Use unary operators of the ternary system with TMUXs. It is the technique that we use in this paper. This method will generate a low transistor count and low PDP. The articles using this approach are: Authors of [12][13][14] designed TFAs with 74, 89, and 72 CNFETs, respectively. (4) The following papers use mixed techniques: Authors of [15] proposed a TFA with 142 CNFETs using unary operators based on Binary NAND, TMUXs, and ternary encoders. In [17], the authors proposed a TFA with 74 CNFETs using PTL (Pass Transistor Logic) and TMUXs, which produce medium propagation delays and a medium PDP. The authors of [18] proposed a TFA with 54 CNFETs using unary operators, Transmission Gates, PTL, and TDecoders.
Finally, we will discuss the debatable approach. Authors of [16] represented two TFAs with 49 and 37 CNFETs using a capacitive network (the threshold logic approach). The drawback of this method is a drastic reduction in the noise margins when coherent noises are simultaneously present on the different inputs and high propagation delays and PDP. We will exclude these TFAs from the comparison with other TFAs. To our knowledge, a linear combination of inputs has not been used for binary logic circuits since the 1970s, when Resistor Transistor Logic (RTL) was replaced by Diode Transistor Logic (DTL). Replacing resistors with capacitors does not change the issue.

Contributions
The above designs have massive transistors count, high propagation delays, and (or) high PDP.
This paper proposes two TFAs with 59 and 55 CNFETs using unary ternary operators and TMUXs to obtain the lowest PDP.
Remark: Not always the reduction in the number of transistors is a good design. We must consider parameters such as (1) the critical path between the inputs and the outputs (see section "Design Methodology"); (2) the direct current path from the power supply to the ground, as described above. That is why we use unary ternary operators and TMUXs.
The following are the main contributions of this paper: 1. Not using the basic ternary logic gates (STI, TNAND, TNOR), TDecoders, and ternary encoders. Because using the basic ternary logic gates will produce a high transistor count and more energy consumption (compared to [7,8,15]).

2.
Using unary operators can replace basic ternary logic gates, resulting in a considerable reduction in the number of transistors utilized and PDP.

CNFET Transistor
This paper uses the Stanford CNFET model [19], as shown in Figure 2. However, the following Equation (2) shows that the threshold voltage depends on the diameter of the carbon nanotube (CNT): where Dcnt is the CNT diameter. Because we use an unbalanced ternary logic system (0 (0 v), 1 (V dd /2), 2 (V dd )) then we want to choose two threshold voltages to achieve three logic states from the CNFET. The best two threshold voltages are 0.289 V and 0.559 V, as described in Table 2. Table 2 explains how the CNFET transistors work, as well as the relationship between the threshold voltage and the diameter of the carbon nanotubes that are used in this paper.

Design Methodology
This paper proposes two different TFAs using the proposed unary operators combined with two different TMUXs.

Two Proposed Unary Operators
The unary operators of a m-valued system are logic gates with one input and one output. Table 3 shows seven unary functions to be used in the designs of TFAs. Where A is the ternary input, A p is a Positive Ternary Inverter (PTI), A n is a Negative Ternary Inverter (NTI), A 1 = (A + 1) mod (3) called successor or single shift operator and A 2 = (A + 2) mod (3) called Predecessor or dual shift operator are the cycle operators. A 1 is the decisive literal, and the last two unary functions are 1 ·Ā n and 1 ·Ā p [22].
We propose new designs for two unary operators A 1 and A 2 , as shown in Figure 3. The other five unary operators are presented in [23,24].

Ternary Multiplexers
Compared to the typical (2:1) Binary MUX, this special (2:1) Ternary MUX has a 0.289 V instead of 0.559 V threshold voltage for the second transmission gate. Cn is the NTI output of select input C in instead of C in (2:1) Binary MUX.

Proposed Two TFAs
A 1-trit Ternary Full Adder adds three ternary inputs (A, B, and C in (Carry-in)) and produces two outputs, the Sum and the Carry Out (C out ), as described in Table 7. C in has only values 0 or 1 (V dd /2).  The general equations of the Sum and the Carry Out (C out ) are shown in (5): Equations (6) and (7) are derived from Table 7. Using unary operators and TMUXs, they are: where
The three ternary inputs (A, B, C in ) enter the six unary operators sub-circuits. Then the outputs of unary operators enter the special (2:1) TMUXs, and the outputs of (2:1) TMUXs enter the (3:1) TMUXs to produce the final outputs (Sum and Carry Out), as shown in Figure 6. The critical path (dotted red line) is the maximum propagation delay from the input "A" to the output "Sum" via (A, Ap, A 2 , first TG in (2:1) TMUX, third TG in (3:1) TMUX, then Sum) when "A" changes from 1 to 2, "B" = 2, "C in " = 0, and "Sum" from 0 to 1. The path from C in to C out is the critical one in N-trit carry propagate adders (see Section 3.3.2).
The three ternary inputs (A, B, C in ) enter the unary operators sub-circuits. Then the outputs of unary operators enter the (3:1) TMUXs, and the outputs of (3:1) TMUXs enter the special (2:1) TMUXs to produce the final outputs (Sum and Carry Out), as shown in Figure 7.
The propagation delay in the critical path of TFA2 is less than the one of TFA1, as observed by comparing Figures 6 and 7.

4-Trit Ripple Carry Adder
A Ripple Carry Adder (RCA) is a logic circuit that cascades multiple full adder circuits. The carry-out of each full adder is the carry-in of the next one.
This paper proposed two 4-trit RCAs using the proposed TFAs to demonstrate the efficiency of the proposed circuits in the design of larger computational blocks. The general model of the proposed 4-trit RCA is shown in Figure 8. The critical path in N-trit RCA is always from C in to C out .
The simulation parameters for Figure 9 and Table 8 are V dd = 0.9 V, temperature = 27 • C, frequency = 1 GHz, and fall/rise time = 20 ps for all input signals. Figure 9 shows the transient analysis of the proposed (a) TFA1 and (b) TFA2. Table 8 compares all the investigated TFA circuits regarding transistor count, average power, maximum delay, maximum PDP (Power Delay Product), and maximum EDP (Energy Delay Product). The values in bold are the lowest values (best values). Because the results of the proposed TFA2 are better than the proposed TFA1, we will compare the proposed TFA2 to the other designs. The comparison to the lowest value (bolded or *) inside each column regarding the proposed TFA2 using the comparison ratio value Equation (9). Ratio = Best previous design/Proposed design (9) where Ratio > 1: It means that the proposed design is better.

Ou t p u t ( a )
Ou t p u t ( b ) The results show that the proposed TFA2 is better than the best other designs regarding max. propagation Delays, PDP, and EDP.

Different Voltages, Temperatures, and Output Loads
To study the performance and efficiency of the proposed circuits, we simulate the proposed TFA1 and TFA2 for different voltages (Table 9), different temperatures (Table 10), and different output loads (Table 11).
In addition, we simulate the proposed TFAs regarding maximum PDP, and maximum EDP, as shown in Figures 10 and 11, (a)    As shown in Tables 9-11 and in Figures 10 and 11, the proposed TFA2 gives lower results compared to TFA1 in all study parameters, lower power, lower propagation delay (more speed), and lower energy consumption. Therefore, the proposed TFA2 is more stable and better than the proposed TFA1.

Scalability Study
We implement a 4-trit Ripple Carry Adder for each TFA design and simulate them with temperature at 27 • C, power supply at 0.9 V, frequency at 1 GHz, and fall and rise time of 20 ps, as shown in Table 12.
As shown in Table 12, the proposed 4-trit RCA that uses TFA2 has better performance than others. Therefore, the proposed TFA2 can be used for larger adders.

Conclusions
This paper proposes two novel 32 nm channel CNFET-based designs of Unary Operators combined with a Ternary Multiplexer to design two different Ternary Full Adders.
The design process uses different techniques regarding transistor arrangement, two voltage supplies (V dd , V dd /2), and a transistor count reduction to lower the energy consumption of the ternary full adder.
Compared to recent similar designs, the HSPICE simulation results show higher performance and lower energy consumption.
It seems that these designs are closed to the optimal design of ternary adders. This work will be continued by the design of quaternary adders and multipliers to examine how the performance evolves when moving from ternary to quaternary circuits. These ternary and quaternary arithmetic circuits will be compared with the corresponding binary ones.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript: