A 0.6 VIN 100 mV Dropout Capacitor-Less LDO with 220 nA IQ for Energy Harvesting System

A fully integrated and high-efficiency low-dropout regulator (LDO) with 100 mV dropout voltage and nA-level quiescent current for energy harvesting has been proposed and simulated in the 180 nm CMOS process in this paper. A bulk modulation without an extra amplifier is proposed, which decreases the threshold voltage, lowering the dropout voltage and supply voltage to 100 mV and 0.6 V, respectively. To ensure stability and realize low current consumption, adaptive power transistors are proposed to enable system tropology to alter between 2-stage and 3-stage. In addition, an adaptive bias with bounds is utilized in an attempt to improve the transient response. Simulation results demonstrate that the quiescent current is as low as 220 nA and the current efficiency reaches 99.958% in the full load condition, load regulation is 0.0059 mV/mA, line regulation is 0.4879 mV/V, and the optimal PSR is −51 dB.


Introduction
Energy harvesting (EH) technology converts weak energy harvested from the environment into electricity [1][2][3]. EH has been used in many fields, such as the Internet of Things (IoT), wearable devices, and wireless sensors [4][5][6]. The output voltage collected from energy harvesting is unstable. Therefore, the low-dropout regulators (LDOs) are used to provide a stable power supply for the loads, as they have the advantages of uncomplexity, a low cost, and being noise-immune. A typical EH system is depicted in Figure 1. Considering the weakness of the energy source and low collection efficiency, energy collection suffers from a low supply voltage and high power consumption [7][8][9]. Consequently, new challenges and requirements are set forth for the supply voltage and power conversion efficiency of LDO. For the purpose of improving the integration and reducing the cost, [10][11][12][13] proposed the output-capacitor-less (OCL) LDOs consuming µA-level static currents. However, lowpower equipment should consume as little electricity as possible during standby and operation. To further reduce the current to nA levels, [14] adopts an adaptive bias solution based on the super-source follower (SSF) structure. Nevertheless, the minimum supply voltage is as high as 1.8 V, and struggles to meet the EH requirement. In addition, the large dropout voltage leads to large power loss.
Another approach to improving efficiency is to reduce the dropout voltage [15]. A dropout voltage can be defined as the product of the valid channel resistance of the component and the load current in non-regulatory conditions [16]. In [17], a large and wide ratio power transistor is proposed to reduce the equivalent resistance, but this requires a large area. One method to reduce the threshold voltage is the floating meter [18,19], and the other method is body bias [20][21][22]. Recent research has shown that the threshold voltage can be reduced using current-driven bulks [23]. Since V B is less than V S in the PMOS power transistor, the source-end bipolar crystal pipe can be turned on to reduce the threshold voltage. This extra adaptively biased current-driven loop generates a lot of static current, which cannot meet the low I Q requirements.
This paper proposes a 100 mV-dropout and high-efficiency OCL-LDO with low supply voltage, which uses bulk modulation and adaptive bias technology with adaptive power transistors (APT). The bulk modulation without using the auxiliary amplifier has significantly reduced the dropout voltage to 100 mV. The adaptive bias can quickly detect the transient jumps to shorten the recovery times and reduce the quiescent current. Through the use of APT, the system is able to switch between 2-stage and 3-stage amplifiers under different load conditions, ensuring its stability in the full load range. Further, APT reduces power consumption by reducing unnecessary current consumption. On the one hand, ultra-low V I N and V OUT are suitable for weak EH systems, since they require a low input voltage and output voltage. On the other hand, by reducing the dropout voltage, high efficiency can be achieved with low power consumption.
In the rest of this paper, the operating principle of the proposed LDO is discussed in Section 2. Sections 3 and 4 describe the circuit implementation and stability analysis, respectively. The simulation results, along with comparisons with the state-of-the-art designs, are reported in Section 5. Finally, conclusions are drawn in Section 6.

Bulk Modulation without Amplifier
The amount of energy collected by the EH system is extremely small. DC-DC Boost converter only produces a few hundred mV of output voltage, requiring a low V I N in the LDO design. Generally, the V I N can be expressed as: where V G , V GSP , and V THP are the gate voltage, gate-source voltage, and threshold voltage of the power transistor, respectively. When there is a voltage difference between the bulk and source, V TH decreases with V BS due to the body effect and can be written as: where V TH0 is the threshold voltage when V BS is zero, γ denotes the bulk-effect coefficient, and Φ F is the Fermi potential. Generally, γ ranges from 0.3 V 1/2 to 0.4 V 1/2 . This analysis was simplified by replacing source-bulk voltage V SB with −V BS . In the case of a 2 >>b 2 , taking into account a mathematical formula [24]: In Equation (2), there is (2Φ F ) 2 >>V 2 SB , and substitute them into a and b, and considering the relationship of [25,26]: where η ranges from 1.2 to 1.3. Part of Equation (2) can be approximately expressed as follows: Therefore, we can conclude that V TH is linearly related to V SB . Via the body effect approximation, Equation (2) can be simplified as [27]: Previously, the bulk of the power transistor was connected to the source to prevent the conduction of the PN junction between the source and the bulk, as shown in Figure 2a. Thus V TH = V TH0 . The minimum V I N of this kind of LDO is larger than 1 V, which does not meet the criteria for low V I N .
The bulk modulation is proposed to reduce V TH and then V I N , as illustrated in Figure 2b. This system imposes an additional amplifier to generate the bulk voltage V BODY , which increases power consumption. Recently, bulk modulation without an extra amplifier was proposed in [28], which can better realize the balance between power consumption and low V I N . Figure 2c shows its structural block diagram. However, the modulated V G is close to V I N , resulting in low gain and poor performance.
To solve the problems mentioned above, this paper proposes a voltage reuse scheme to generate V BODY . In a typical three-stage structure of OCL-LDO, the buffer is used to increase the drive ability and enhance the load capacity of the power transistor due to the small output resistance. The buffer output is usually only connected to the gate of the power transistor V G . In this paper, the bulk modulation is simplicity obtained by connecting the buffer output to not only the gate but also the bulk of the power transistor, as shown in Figure 3. V I N in this paper can be expressed as: From Equation (7) V I N is determined only by V TH0 and V G . The large value of V BODY is replaced by V G , resulting in a reduction in V I N to 600 mV. In addition, a gain path is established from the bulk to V OUT , and the body transconductance g mb can enhance the regulation gain. Consequently, V I N is more effectively reduced without introducing additional power consumption, ensuring that the transistor performs normally in low V I N . It is important to note that a forward-biased PN junction between bulk and source experiences very low voltage. An exceedingly high V SB may lead to the forward breakdown of the MOS transistor, resulting in device damage. Lowering the bulk voltage appropriately, while ensuring that the PN junction does not undergo breakdown, can reduce V TH . To validate the feasibility of the proposed approach, simulations of the circuit were conducted. Figure 4a shows that the value of V TH as V I N varies under different V BODY when adopting the V BODY reuse method. The simulation results show that V TH increases as V I N decreases, while V BODY remains constant. However, V TH can be effectively reduced by decreasing V BODY . In the proposed design, the MOS transistor is protected from forward breakdown since the maximum value of V BODY is 280 mV, which is less than the forward breakdown voltage. Additionally, Figure 4b shows the drain current with and without V BODY reusing. There is evidence that, within a specific range, after adopting the reuse of V BODY , I Q can be effectively reduced. Therefore, the proposed bulk modulation without an amplifier reduces both V I N and I Q .
Despite this, bulk modulation also has some disadvantages, such as circuit instability due to the excessive modulation or reverse breakdown of PN junctions caused by a V BODY that is too low. To solve the above problems, APT technology is proposed in the next section.

Adaptive Power Transistors
The drain current I D of the power transistor working in the saturation region can be given by: where µ P is the mobility of the PMOS channel, C OX is the capacitance of the gate oxide layer, and W/L is the transistor ratio. As the load current I LOAD gradually increases and V GS increases, so V G decreases accordingly. When employing V BODY reuse, there is V G = V BODY . Reducing V BODY too much will result in increased V BS , which may lead to the forward breakdown of the PN junction.
As a preventative measure, this paper proposes the APT technology. This is based on the principle that, when the load changes, a feedback signal is used to adjust the use of the auxiliary and main power transistors (MP 1 and MP 2 ). Meanwhile, bulk modulation performs on MP 1 and MP 2 . Specifically, the modulation effect will be enhanced as I LOAD increases. The V BODY reuse scheme being implemented for MP 2 will turn off under light loads, making V BODY close to V I N . The schematic diagram and working process of APT are shown in Figure 5. The system works in a twp-stage amplifier topology when the load is light. Due to the second gain stage performing in the triode region, M 14 pulls the output voltage closer to the supply. Therefore, the V GS of MP 2 is minimal, and MP 2 is turned off. This was obtained by designing the aspect ratio of M 14 and M 16 . M 14 is set to be small enough and M 16 is set to be large enough; thus, M 16 works in the saturation region, whereas M 14 is forced into the deep linear region to sustain equilibrium in the light load. The gate of MP 1 is connected to the output of the first-stage amplifier, V EA . MP 2 is forcibly disabled and all the load current flows through MP 1 .
When the load current increases, the I DS of MP 1 increases, as well as its V GS . Therefore, V EA decreases, as well as the V G of M 11 , which increases the current of M 11 and provides a large current to M 15 , as well as M 16 . Thus, the drop-down ability of M 16 becomes strong enough to pull M 14 from the linear region into the saturation region. Hence, MP 2 is activated. The system works in a 3-stage amplifier topology.
To better distinguish the two operating states, we define a threshold current I ON of approximately 350 µA. When the load current is less than I ON , the second-stage amplifier is working in the triode region and turns off MP 2 . When the load current increases to I ON , the second-stage amplifier works in the saturation region and turns on MP 2 .
It is worth mentioning that the proposed LDO can adaptively switch the power transistors according to the load current, allowing the system to transform itself between 2-stage and 3-stage topologies. In addition, simulation results have shown that V BODY ranges between 350 mV and 550 mV with APT, and V BS is less than the forward breakdown voltage, which ensures the safety of the device. Figure 6 shows the LDO structure with the proposed bulk modulation and APT. The gain boost stage with an adaptive bias module (ABM) is used, which obtains a large bandwidth gain depending on the load current. The unity gain buffer (BUF) produces V BODY to modulate the bulk voltages of MP 1 and MP 2 , lowering the total current consumption via bulk modulation. The APT not only achieves satisfactory linearity but also improves the transient response. In an attempt to realize enough stability, the compensation module (CM) with an internal RC network is used.

Circuit Implementation
This section will provide an overview of the OCL-LDO, including its structural realization and design consideration. The proposed OCL-LDO works under the condition of V I N = 0.6 V, V REF = 0.5 V, with V Drop = 100 mV. The LDO's V REF is ultra-low, which can be generated with a BJT-based Kuijk bandgap reference [29].

Maximize the Efficiency under Low V I N
To maximize efficiency, it is necessary to reduce the dropout voltage. However, lowering the dropout voltage degenerates the DC gain of the power stage, which can be expressed as: where g m,linear is the transconductance in the linear region. As V DS in the design is merely 100 mV; it is highly possible for it to be smaller than (V GS − V TH ), implying that the A P is less than one. It is worth noting that this issue is not present for regular 200 mV dropout regulators, as their power stage can supply roughly 20 dB gain for the control loop. To address this problem, the proposed LDO introduces a gain boost stage with ABM. From Figure 7, the gain boost stage employs a single-stage differential amplifier along with a cross-coupled PMOS pair to increase the gain. The cross-coupled pair generates negative resistance that can counteract the equivalent resistance of diode-connected transistors M 5 and M 6 , which effectively increases the resistance of internal nodes V X and V Y . The amplifier gain is obtained as: where g m represents the transconductance of M 3 , M 4 , and g ds denotes the total output conductance of node V X or V Y . The gain is amplified by a factor of ((1 + α)g m + g ds )/ ((1 − α)g m + g ds ). To ensure that it works as an amplifier rather than a hysteresis comparator, the pairs M 3 -M 4 and M 6 -M 5 are set at a ratio of α:1, where α should be kept smaller than 1 to avoid the over-compensation of negative resistance, taking into account the random mismatch under the fabrication. For the push-pull stage structure, the DC gain can be approximated at 1. As a result, the overall circuit gain can be expressed as follows: Thus, the DC performance of this LDO can be significantly improved by increasing A EA when A P is small.

Achieve Low I Q and Transient Response
Realizing nA-level quiescent current is necessary to ensure ultra-high-power efficiency. The proposed LDO uses adaptive bias to ensure a low quiescent current while reducing transient response time and improving transient response.
Unlike traditional adaptive bias circuits, which mirror the current at the gate of the power transistor to bias the amplifier or buffer, the proposed ABM is driven by the firststage amplifier itself and provides a bias current proportional to the load current, which can maintain a large enough gain of the first-stage amplifier over the entire load range. Figure 8 illustrates the specific design of ABM. The ABM's input current is set by M 23 , which is biased by V EA and is proportional to the load current because V EA is closely related to the load current. The output current of ABM is I BI AS , which is used to bias the amplifier and equal to the sum current of M 1 and M 2 . I MI N and I 2 are used to define the bias upper and lower limit. The workflow of ABM can be summarized into the following three phases depending on the load current.
Considering that the current of M 20 is less than I 2 , I BI AS is equal to the current sum of M 21 and I MI N , and can be expressed as: where K and N are the current mirror ratios, as shown in Figure 8.

• Heavy load
Once the current of M 20 increases to larger than I 2 , the current mirror, made up of M 18 and M 19 , is activated. This threshold current I TH2 can be expressed in the following manner: I BI AS stops increasing and reaches the upper limit, which can be expressed as: The bounds of I BI AS ensures stable operation. In the actual design, I MI N and I 2 are set at 7 nA, 18 nA, respectively. N and K are set at 6 and 5150, respectively. It is worth mentioning that ABM also contributes to improvements in gain. The equivalent transconductance g mEA of the gain boost stage can be determined as follows: As I LOAD increases, g m1 increases significantly; thus, g mEA enlarges accordingly. Therefore, the bias current for the amplifier is proportional to the load current.

Stability Analysis
To analyze the stability of the proposed LDO, a small-signal transfer function needs to be derived. It can be seen from Figure 9 that the small-signal model switches between the two-stage amplifier and the three-stage amplifier. Due to the existence of the self-adaptive power transistor, MP 1 , and MP 2 turn on and work sequentially under the condition of different load currents. Thus, the stability analysis of the circuit should be discussed according to the situation: (i) the second-stage amplifier and (ii) the third-stage amplifier. Due to the topology complexity, it is difficult to obtain the transmission function and analyze the stability. To simplify the derivation of the loop without reducing accuracy, the following assumptions are established.
The gains of the first-stage amplifier, the main power transistor, and the side power transistor are far larger than 1, that is, g m<i> r o<i> >> 1. In the case of the third-stage amplifier, g mp2 >> g mp1 . Since the g mb of MP 1 is small, it was ignored in the analysis. The output capacitor C L is larger than compensating capacitors C M , C EA .

Two-Stage Structure
In the case of a small load current, the LDO is equivalent to a secondary structure. There is a pole in V OUT due to the output resistance and load capacitance. Since output resistance is closely related to the load size, a light load will have a relatively large output resistance, which results in the pole associated with the output terminal moving to the low frequency and becoming the dominant pole, P 1 . The secondary pole P 2 is located at the output of the first stage because of the output resistance of the amplifier and the parasitic capacitance of the MP 1 gate. The poles' frequencies can be obtained by calculation as follows: Maintaining stability by only allowing one pole to exist within the bandwidth is necessary. When the OCL-LDO is operated under the minimum load current condition, the pole frequency located in the output is close to zero. Therefore, LDO has a very poor phase margin (PM) and must adopt a compensation structure to produce a zero point. The compensation is performed by connecting the compensation Miller capacitor C M between the output of the first-stage amplifier and V OUT . However, the traditional Miller compensation produces a zero point in the right half plane (RHP), which is converted to the left half plane (LHP) by adding the zeroing resistor r m . Therefore, the zero point Z 1 can be expressed as: Therefore, the transfer function of the two-stage structure can be expressed as: LG(s) = A 0 where A 0 is the DC gain under the condition of light load and can be calculated as: As shown in Figure 10, the LDO's open-loop frequency response and pole-zero distribution are plotted under the conditions of V I N = 0.6 V with I LOAD = 10 µA. Based on the simulation results, the PM is better than 45 • for the worst-case scenario with the smallest load current, and the overall circuit is stable.

Three-Stage Structure
During heavy load conditions, the output resistance of the circuit decreases, and the pole at the output becomes the secondary pole P 2 instead of the dominant pole P 1 . Since the MP 2 main power transistor has a large size, its parasitic capacitance is relatively large. Therefore, the pole existing on the gate of the main power transistor becomes the main pole P 1 . The poles under heavy load can be approximated as follows: Because the output capacitance and equivalent resistance of other nodes in the smallsignal diagram are small, other poles are outside the bandwidth, which will be canceled out by zeros and thus have no effect on the stability of the overall circuit.
Due to the relationship between the equivalent capacitance of the miller compensation and the gain of the amplifier, the zero frequency changes in response and moves to a higher frequency. This zero is given by: As a consequence, the three-stage structure has the following transfer function: LG(s) = A 0 1 + s where A 0 is the DC gain under the condition of heavy load, which can be calculated as: A 0 = g mEA g m12 g m14 g mp2 + g mb r oEA r o14 r o g m13 . Figure 11 depicts the specific poles and zeros with a bandwidth under the heavy load. The figure shows that the PM is 59 • , which is greater than 45 • , indicating that the circuit is stable overall.

Simulation Results and Discussion
The LDO proposed in this paper was implemented and verified in a 180 nm CMOS process, which supports 0.6-1.2 V supply voltage and 100 mV dropout voltage with a 10 mA maximum load current. The system can remain stable when C L ranges between 0 and 1000 pF with a 10 pF on-chip compensation capacitor. When I LOAD = 10 µA, V I N varies from 0.6 V to 1.2 V, and I Q changes from 226 nA to 219 nA. The devices' size and the most important parameter values for the proposed OCL-LDO are summarized in Table 1. Under the condition of V I N = 600 mV, I LOAD increases from 10 µA to 10 mA, I Q changes from 220 nA to 1.2 µA. The changing trend of I Q in the two cases is depicted in Figure 12. Only 1.2 µA of quiescent current is consumed when the load current is 10 mA; thus, it achieves a maximum current efficiency of 99.96% when the load current is 10 mA. The current efficiency of the LDO under full load conditions is presented in Figure 13. The current of MP 1 and MP 2 are also shown in Figure 14. From the result, when the system works as a two-stage, system the current of MP 2 is almost equal to zero and MP 1 increases with I LOAD . Once I LOAD > I ON , MP 2 is activated, its current increases with I LOAD while the current of MP 1 remains unchanged. Additionally, we simulated the relationship between PM and load current under a variety of loop conditions. As shown in Table 2, PM decreases with an increase in I LOAD when LDO works in a two-stage manner. However, PM in the three-stage is the opposite. The measured DC load regulation (LDR) is shown in Figure 15a; when the load current varies from 10 µA to 10 mA, the output voltage changes by 0.05857 mV. Therefore, the LDR of the LDO is 0.00585759 mV/mA. The simulation results depicted in Figure 15b indicate that the output voltage only changes to 0.292787 mV when the supply voltage changes linearly from 0.6 V to 1.2 V. According to the calculation formula, the DC line regulation (LNR) of LDO is 0.487978 mV/V.  Figure 16a,b show the measured transient response when the OCL-LDO supply voltage is set to 0.6 V and the load capacitor is set to 100 pF, respectively. For a 1 ns edge, the maximum transient response of V OUT is 230 mV, and the settling time is 5 µs. When the edge is 1 µs, the maximum V OUT is 140 mV, and the settling time is 3.5 µs, which represents a significant improvement. There is a minimum overshoot voltage of 95 mV and a undershoot voltage of 140 mV. However, the transient response is not entirely satisfactory. These results indicate that the circuit's performance is satisfactory and there is room for further improvement. Typically, an undershoot improvement circuit would be included to enhance the transient response. Nevertheless, due to the constraints of quiescent current, no improvement circuit has been incorporated. The trend of the PSR with frequency can be plotted by analyzing the PSR at multiple frequencies over the course of one measurement. The simulated PSR performance at 10 µA load current, 0-pF C L , and 100 mV dropout is shown in Figure 17. Hence, it can be seen that the minimum PSR is −51.40 dB, −49.17 dB at 1 Hz, and −43.97 dB at 1 k Hz. Simulations at different temperatures and process corners are conducted to demonstrate the robustness of the proposed design. The performance results, including minimum values of PM and GM, quiescent current, LDR, LNR, transient response, current efficiency, and PSR, are presented in Table 3. The minimum GM under different corners is greater than 50 dB, ensuring high regulation performance under different conditions. I Q is generally within 500 nA, with the lowest value being 139 nA at the SS corner of −20 • C; the current efficiency is at least 99.95%, and the maximum is 99.99%. There is an excellent transient response at the FF corner of 27 • C, a 2.7 µs recovery time, and a maximum undershoot voltage of 320 mV. The worst PSR within 50 kHz is −51.4 dB at the TT corner of 27 • C. This shows that the proposed design can work steadily and perform as expected, even under extreme conditions. These results predict that the proposed LDO will work reliably after fabrication, even in the worst-case temperature and process corner. A merit map (FoM) is introduced to reflect the overall performance of the LDO, which has the following formula: where I Q is the minimum quiescent current, and ∆V OUT is the maximum change in output during transient. Furthermore, K is the edge time ratio and defined by: K = ∆t used in the measurement the smallest ∆t among designs for comparison . (32) In this design, K = 1, bringing the above values into the calculation, the FoM value is 0.0506 ps. The comparison of the proposed LDO's performance with several state-of-the-art fully integrated LDOs is presented in Table 4 below. Based on the results of the analysis, the proposed LDO achieves the lowest dropout voltage, good load regulation, and lowest FoM.

Conclusions
In this paper, an nA-level and 100 mV dropout LDO, combined with bulk modulation and adaptive power transistors is proposed and simulated in the 0.18 µm CMOS process. The operation principle, circuit implementation, stability analysis, and simulation results have been presented in detail. Particular attention has been paid to obtaining a low dropout and low supply voltage by the bulk modulation technology, without an auxiliary amplifier.
Adaptive power transistors are proposed to switch under different load conditions to ensure circuit stability while reducing circuit power consumption. In addition, the adaptive bias mirroring the current from the amplifier itself with bounds is utilized to improve the transient response. Due to the superiority of ultra-low-power consumption, low supply voltage, and a fast response, the proposed OCL-LDO is suitable for use as a point-of-load regulator in energy harvesting.