Hole Injection Effect and Dynamic Characteristic Analysis of Normally Off p-GaN HEMT with AlGaN Cap Layer on Low-Resistivity SiC Substrate

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect.


Introduction
GaN power transistors have become key devices in high-power and high-efficiency power conversion systems, mainly because of their material properties, such as a wide band gap, high mobility, and strong electric breakdown field. Various approaches, such as the gate recessed structure [1][2][3], fluorine ion treatment [4], and a p-type GaN cap layer have been reported for giving these devices normally-off operation [5][6][7]. The other advantages of GaN power transistors are their high breakdown voltage, high switching speed, and low on-resistance. Therefore, p-GaN gate normally-off power devices have been considered as key devices in high power and high-frequency applications such as power conversion systems in hybrid or electric vehicles [8]. Normally-off operation is necessary for such applications because the current must be cut off in case of uncontrollable situations, such as short and open modes.
In commercial p-GaN HEMTs, device gates are either ohmic contacts or Schottky contacts. Compared with ohmic gates, such as gate injection transistors, Schottky gates have a lower forward gate leakage current, mainly due to a reverse Schottky diode at the junction of the metal and p-GaN. A Schottky gate p-GaN HEMT also exhibits a time-dependent gate breakdown voltage, but the gate's operating voltage is limited to 6-7 V. Therefore, many research groups are developing methods to increase this maximum value so that the device can be operated in a wider gate bias range [9]. Under positive bias, the gate breakdown of a p-GaN HEMT can be attributed to the strong electric field concentrated at the metal/p-GaN interface [10]. Different from the time-dependent dielectric breakdown performance of Si and SiC power MOSFETs, the time-dependent gate breakdown behavior of p-GaN HEMTs is usually positively correlated with the temperature coefficient which means that high-energy carriers are accelerated through impact ionization or hot electron bombardment in a strong electric field. Therefore, one of the methods for improving the reliability of a gate is to make structural or process changes at the metal/p-GaN junction. Conversely, many scholars have analyzed the physical mechanism of dynamic resistance change which is mainly due to hot electron injection on the surface and defects in the buffer layer. These defects have numerous forms, such as carrier vacancies, lattice dislocations, and impurities. Additionally, GaN devices are mostly operated under high frequency and power. Thus, the characteristics of the device during high-temperature operation are also critical. Two substrates are employed in p-GaN HEMTs, namely GaN-on-Si and GaN-on-SiC. Compared with a GaN-on-Si HEMT, a GaN-on-SiC HEMT should be a more favorable choice for high-power switching components because of its high thermal conductivity, low resistivity, and high-voltage capability. Another advantage of using a SiC substrate is its lower lattice mismatch of approximately 3% for GaN (that of Si is~17%). Therefore, a low-resistance and 0 • -angle SiC substrate not only has the aforementioned advantages of GaN-on-SiC but also has a lower cost than a high-resistivity SiC substrate. We previously employed an AlGaN cap layer and low-resistivity SiC substrate in a p-GaN HEMT [11,12].

Device Structure
In this study, an AlGaN/p-GaN/AlN/AlGaN/GaN HEMT was grown on a 6-inch low-resistivity SiC substrate through metalorganic chemical vapor deposition. The epitaxial structure is illustrated in Figure 1a. An undoped GaN channel layer with a thickness of 300 nm was grown on an undoped AlGaN/GaN buffer/transition layer with a thickness of 4 µm. Subsequently, an Al 0.25 Ga 0.75 N barrier layer with a thickness of 15 nm and a p-type GaN layer with a thickness of 100 nm were grown. of its high thermal conductivity, low resistivity, and high-voltage capability. Anot vantage of using a SiC substrate is its lower lattice mismatch of approximately 3% f (that of Si is ~17%). Therefore, a low-resistance and 0°-angle SiC substrate not only aforementioned advantages of GaN-on-SiC but also has a lower cost than a high-r ity SiC substrate. We previously employed an AlGaN cap layer and low-resistiv substrate in a p-GaN HEMT [11,12].

Device Structure
In this study, an AlGaN/p-GaN/AlN/AlGaN/GaN HEMT was grown on a 6-in resistivity SiC substrate through metalorganic chemical vapor deposition. The ep structure is illustrated in Figure 1a. An undoped GaN channel layer with a thick 300 nm was grown on an undoped AlGaN/GaN buffer/transition layer with a th of 4 μm. Subsequently, an Al0.25Ga0.75N barrier layer with a thickness of 15 nm an type GaN layer with a thickness of 100 nm were grown.
Finally, an Al0.2Ga0.8N layer of 10 nm thickness was grown on the p-GaN la the device fabrication, the p-GaN etching of Cl2/BCl3/SF6 was achieved using indu coupled plasma, and the AlN layer acted as an etching stop layer. The etching sto nique employed was similar to that used in the p-GaN etching process [13][14][15]. Th ing rate for p-GaN layer etching was approximately 31.5 nm/min. From 210 to 27 etching rate was reduced to less than 2 nm/min because of generation of the AlF (etching stop layer). This etching stop technique prevents overetching in the p-G moval process, as shown in Figure 1b. Ohmic contacts were prepared through e beam evaporation, and Ti, Al, Ni, and Au layers (thickness = 25, 120, 25, and 1 respectively) were stacked on the device sequentially. Both devices were then an using a rapid thermal annealing system at 875 °C for 30 s in ambient N2. Finally, a (25/120 nm) gate metal stack was deposited and a 100-nm SiO2 passivation layer w plied.  Finally, an Al 0.2 Ga 0.8 N layer of 10 nm thickness was grown on the p-GaN layer. In the device fabrication, the p-GaN etching of Cl 2 /BCl 3 /SF 6 was achieved using inductively coupled plasma, and the AlN layer acted as an etching stop layer. The etching stop technique employed was similar to that used in the p-GaN etching process [13][14][15]. The etching rate for p-GaN layer etching was approximately 31.5 nm/min. From 210 to 270 s, the etching rate was reduced to less than 2 nm/min because of generation of the AlF 3 layer (etching stop layer). This etching stop technique prevents overetching in the p-GaN removal process, as shown in Figure 1b. Ohmic contacts were prepared through electron beam evaporation, and Ti, Al, Ni, and Au layers (thickness = 25, 120, 25, and 150 nm, respectively) were stacked on the device sequentially. Both devices were then annealed using a rapid thermal annealing system at 875 • C for 30 s in ambient N 2 . Finally, a Ni/Au (25/120 nm) gate metal stack was deposited and a 100-nm SiO 2 passivation layer was applied. Figure 2a,b reveal the log-scale transfer (I DS -V GS ) and output (I DS -V DS ) characteristics of the device. As illustrated in Figure 2a, the off-state current was 5 × 10 −5 mA/mm at V GS = 0 V. Additionally, the threshold voltage V TH was 1.5 V which is defined at I DS = 1 mA/mm. The corresponding maximum drain current density I Dmax and Ron were 210 mA/mm and 20 Ω mm, respectively.

Experimental Result and Discussion
Micromachines 2022, 13, 807 3 of 8 Figure 2a,b reveal the log-scale transfer (IDS-VGS) and output (IDS-VDS) characteristics of the device. As illustrated in Figure 2a, the off-state current was 5 × 10 −5 mA/mm at VGS = 0 V. Additionally, the threshold voltage VTH was 1.5 V which is defined at IDS = 1 mA/mm. The corresponding maximum drain current density IDmax and Ron were 210 mA/mm and 20 Ω mm, respectively. To observe the hole injection effect during gate operation, IGS-VGS measurements were made [ Figure 3a]. The device exhibited a large gate operation voltage under forward bias, and the gate turn-on voltage VGS_ON was 18.5 V at IGS = 1 mA/mm. The device exhibited favorable gate behavior because of its higher barrier which effectively suppressed the carrier injection. As revealed by Figure 3b, the device exhibited a high off-state breakdown voltage of 763 V. We used pulse measurement to analyze the hole injection effect and dynamic characteristics of the device under various stress voltages VGSQ and durations. To evaluate the gate lag behavior we employed the AM-241 pulse measurement system [16,17]. The operation condition and gate lag measurement are illustrated in Figure 4a and 4b, respectively. Two bias conditions had to be considered: pulse voltage (VGSP and VDSP) and quiescent voltage (VGSQ and VDSQ). During the measurement, the pulse voltage switched rapidly to the quiescent voltage with a 2μs pulse width and 200 μs period, and VGSQ was swept from 0 to −15 V in increments of −5 V. The device exhibited dynamic Ron of 1.22 times at VGSQ = −15 V.

Experimental Result and Discussion
As indicated in Figure 5a, VTH shifted in the positive direction under VGSQ = 6 V when the stress duration was increased from 0.1 ms to 1, 10, and 20 ms. This was caused by an enhanced electron injection from the channel at a higher VGSQ and trapping at the p-GaN/AlN/AlGaN interfaces. Moreover, the VTH shifting could be plotted in the pulse measurement, as presented in Figure 5b. When VGSQ from 1 to 5 V was applied, holes may have accumulated at the p-GaN/AlGaN interface [ Figure 6a] or in trap states at the Al-GaN/GaN interface, temporarily increasing the density of the two-dimensional electron gas and causing a negative shift in VTH. When VGSQ from 5 to 15 V was applied, VTH shifted in the positive direction. This can be explained by some injected electrons being captured by the electron traps at the p-GaN/AlGaN interface, with the trapped electrons not being able to immediately escape [ Figure 6b]. Subsequently, the stress voltage was larger than 15 V, and the hole injection was turned on for injection of the p-GaN/AlGaN interface, leading to recombination of the trapped electrons [ Figure 6c]. Thus, the VTH shift was reversed again [18][19][20][21][22]. To observe the hole injection effect during gate operation, I GS -V GS measurements were made [ Figure 3a]. The device exhibited a large gate operation voltage under forward bias, and the gate turn-on voltage V GS_ON was 18.5 V at I GS = 1 mA/mm. The device exhibited favorable gate behavior because of its higher barrier which effectively suppressed the carrier injection. As revealed by Figure 3b, the device exhibited a high off-state breakdown voltage of 763 V. We used pulse measurement to analyze the hole injection effect and dynamic characteristics of the device under various stress voltages V GSQ and durations. To evaluate the gate lag behavior we employed the AM-241 pulse measurement system [16,17]. The operation condition and gate lag measurement are illustrated in Figure 4a     As indicated in Figure 5a, V TH shifted in the positive direction under V GSQ = 6 V when the stress duration was increased from 0.1 ms to 1, 10, and 20 ms. This was caused by an enhanced electron injection from the channel at a higher V GSQ and trapping at the p-GaN/AlN/AlGaN interfaces. Moreover, the V TH shifting could be plotted in the pulse measurement, as presented in Figure 5b. When V GSQ from 1 to 5 V was applied, holes may have accumulated at the p-GaN/AlGaN interface [ Figure 6a] or in trap states at the AlGaN/GaN interface, temporarily increasing the density of the two-dimensional electron gas and causing a negative shift in V TH . When V GSQ from 5 to 15 V was applied, V TH shifted in the positive direction. This can be explained by some injected electrons being captured by the electron traps at the p-GaN/AlGaN interface, with the trapped electrons not being able to immediately escape [ Figure 6b]. Subsequently, the stress voltage was larger than 15 V, and the hole injection was turned on for injection of the p-GaN/AlGaN interface, leading to recombination of the trapped electrons [ Figure 6c]. Thus, the V TH shift was reversed again [18][19][20][21][22].   To analyze the thermal characteristics of the device, its IDS-VGS characteristic was measured under 25 °C to 175 °C with a 50 °C step [ Figure 7a]. The device exhibited a VTH shift of less than 0.3 V and Ron increased to 1.28× at 175 °C [ Figure 7b]. Therefore, the p-GaN HEMT on a SiC substrate has high thermal stability because of its high thermal dissipation ability. Finally, the distributions of VTH and Ron characteristics for 30 devices were measured and are presented in Figure 8. The mean VTH and Ron were 1.5 V and 20 To analyze the thermal characteristics of the device, its I DS -V GS characteristic was measured under 25 • C to 175 • C with a 50 • C step [ Figure 7a]. The device exhibited a V TH shift of less than 0.3 V and Ron increased to 1.28× at 175 • C [ Figure 7b]. Therefore, the p-GaN HEMT on a SiC substrate has high thermal stability because of its high thermal dissipation ability. Finally, the distributions of V TH and Ron characteristics for 30 devices were measured and are presented in Figure 8. The mean V TH and Ron were 1.5 V and 20 Ω·mm, respectively.

Conclusions
In the device developed in this study, an AlGaN cap on the p-GaN layer reduced the hole injection effect and created a large gate operation range. It is hoped that the gate driver of traditional silicon devices can be shared and the operating safety voltage of the gate can be increased simultaneously. In addition, we grew a p-GaN HEMT with an AlGaN cap layer on a low-resistance SiC substrate, thus lowering the lattice defect density at the buffer layer position of the GaN-on-SiC structure. This improved the heat dissipation performance and lowered the cost of device production.

Conflicts of Interest:
The authors declare no conflict of interest.