A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.


Introduction
Temperature sensors are desirable for temperature sensing and compensation in modern applications, such as medical, environmental monitoring, thermal monitoring and wireless Internet-of-Things (IoT) platforms [1][2][3]. Most of such applications are battery powered for portability, durability or deployment flexibility [4,5], and put a strict power budget on temperature sensor which drives the power consumption to sub-µW and even to near-zero.
Resistor-based temperature sensors can achieve higher resolution and energy efficiency than BJT-based sensors. As discussed in Ref. [9], the authors use a temperature-dependent RC (Resistor and Capacitor) filter to extract the temperature information. In Ref. [10], the authors build a resistor based Wheatstone bridge whose voltage difference is proportional to the temperature. Both the temperature-dependent phase shift and voltage difference are sequentially digitized by Σ∆-ADCs. Σ∆-ADCs achieve high resolution at the cost of high power consumption and hardware cost from the decimation filter which normally are not mentioned in papers. Thus, the sacrifice of power consumption and hardware make BJT and resistor based temperature sensors not an optimal choice for battery powered applications. CMOS based temperature sensors are normally composed of digital delay cells. They are much more area efficient and easier to scale down with process. The authors in Ref. [13] demonstrate a VCO based temperature

Basics of CMOS Thyristor Based Delay Cell
CMOS thyristor was proposed to increase the delay [17,18]. As shown in Figure 1, M 2 and M 4 work as a thyristor. M 3 and M 5 receive the input signal V IP and V IN , respectively, while V IN is the complementary signal of V IP . Current source I BN is used to sink current from V ON via switch M 1 according to the status of V IP . C 0 is the total capacitance on node V ON . When V IP is low, M 5 /M 3 are conducted and M 1 is non-conducted, V ON and V OP are reset to VDD and GND, respectively. When V IP is changing to high, M 5 /M 3 switch off and M 1 switches on. Current source I BN starts sinking current from V ON which results in node voltage decreasing from VDD. Approximately, M 4 conducts when V IP reaches VDD-V thp , where V thp is the threshold voltage of M 4 . After that, V OP is charged from power supply VDD via M 4 and increased rapidly. Sequentially, M 2 conducts when V OP reaches V thn and discharges current from V ON together with I BN , where V thn is the threshold voltage of M 2 . It accelerates the node voltage decrease on V ON and constitutes a positive feedback loop between M 2 and M 4 . Once the positive feedback is built, V ON and V OP toggle to the opposite state in a short time. The corresponding delay value is calculated as [17] where the first term on the right is the delay contributed by discharging C 0 , the second term is the delay contributed by charging C 1 , and δt is the regeneration time of the CMOS thyristor. C 1 is the parasitic capacitance of V OP . In reality, because of the subthreshold effect, M 4 charges the C 1 simultaneously with M 2 discharging C 0 . The second term can be neglected. Comparing to the first term, the regeneration time δt is small and can be omitted. The delay value can be approximated as Both adopting a larger capacitor C 0 and reducing sink current I BN are effective to increase the delay value. Since C 0 generally adopts metal capacitor which is mostly temperature independent, the temperature coefficients are decided by the ratio of V thp /I BN . Micromachines 2020, 11,

Proposed CMOS Thyristor Based VCO
VCO is generally constituted by multiple stages (beyond three stages) to satisfy the desired frequency. The more stages it has, the more devices are required, which would consume more power and also deteriorate the wave performance. To simplify the circuit and reduce device counts, a twostage ring VCO is proposed and shown in Figure 2. The delay cell is composed of the CMOS thyristor based delay cell aforementioned. In the proposed architecture, the negative output VON1 of the first stage is connected to the negative input VIN of the second stage and VOP1 is connected to VIP. In this way, four-stage inversion is produced in the closed loop and thus makes it easy to satisfy the oscillation requirement of 360° phase shift. Referred to the delay value of CMOS thyristor based delay cell in Equation (1), the oscillation period of the proposed VCO is given by

Temperature Sensor Architecture
As shown in Figure 3, two types of VCO are adopted to constitute the proposed temperature sensor. At the top, P-type VCO is composed of Delay_Cell_Ps. The delay value of Delay_Cell_P is approximately the discharging time on VON via IREFN according to aforementioned analysis. Referring to Equation (3), the period of P-type VCO is given as

Proposed CMOS Thyristor Based VCO
VCO is generally constituted by multiple stages (beyond three stages) to satisfy the desired frequency. The more stages it has, the more devices are required, which would consume more power and also deteriorate the wave performance. To simplify the circuit and reduce device counts, a two-stage ring VCO is proposed and shown in Figure 2. The delay cell is composed of the CMOS thyristor based delay cell aforementioned. In the proposed architecture, the negative output V ON1 of the first stage is connected to the negative input V IN of the second stage and V OP1 is connected to V IP . In this way, four-stage inversion is produced in the closed loop and thus makes it easy to satisfy the oscillation requirement of 360 • phase shift.

Proposed CMOS Thyristor Based VCO
VCO is generally constituted by multiple stages (beyond three stages) to satisfy the desired frequency. The more stages it has, the more devices are required, which would consume more power and also deteriorate the wave performance. To simplify the circuit and reduce device counts, a twostage ring VCO is proposed and shown in Figure 2. The delay cell is composed of the CMOS thyristor based delay cell aforementioned. In the proposed architecture, the negative output VON1 of the first stage is connected to the negative input VIN of the second stage and VOP1 is connected to VIP. In this way, four-stage inversion is produced in the closed loop and thus makes it easy to satisfy the oscillation requirement of 360° phase shift. Referred to the delay value of CMOS thyristor based delay cell in Equation (1), the oscillation period of the proposed VCO is given by

Temperature Sensor Architecture
As shown in Figure 3, two types of VCO are adopted to constitute the proposed temperature sensor. At the top, P-type VCO is composed of Delay_Cell_Ps. The delay value of Delay_Cell_P is approximately the discharging time on VON via IREFN according to aforementioned analysis. Referring to Equation (3), the period of P-type VCO is given as Referred to the delay value of CMOS thyristor based delay cell in Equation (1), the oscillation period of the proposed VCO is given by

Temperature Sensor Architecture
As shown in Figure 3, two types of VCO are adopted to constitute the proposed temperature sensor. At the top, P-type VCO is composed of Delay_Cell_Ps. The delay value of Delay_Cell_P is approximately the discharging time on V ON via I REFN according to aforementioned analysis. Referring to Equation (3), the period of P-type VCO is given as Similarly, N-type VCO is composed of Delay_Cell_Ns. The delay value of Delay_Cell_N is approximately the charging time on VOP via IREFP according to aforementioned analysis. Referring to Equation (3), the period of N-type VCO is given as Based on Equation (4) and Equation (5), the ratio between TVCO_P and TVCO_N is calculated C0 and C3 are composed of metal capacitors, which are temperature independent. IREFP and IREFN come from the same current source and they will have the same temperature characteristics and value. Thus, the ratio can be updated as Because Vthp is temperature dependent to the first order [19], ratio_T is proportional to the temperature [13]. Thus, the ratio of the two-type VCO is used to detect temperature.
The complete block diagram of the proposed temperature sensor is shown in Figure 4. The left block is temperature sensor core which is composed of a P-type and a N-type VCO aforementioned. Bias current generator is used to provide the charging/discharging current IREFN/IREFP.  Similarly, N-type VCO is composed of Delay_Cell_Ns. The delay value of Delay_Cell_N is approximately the charging time on V OP via I REFP according to aforementioned analysis. Referring to Equation (3), the period of N-type VCO is given as Based on Equations (4) and (5), the ratio between T VCO_P and T VCO_N is calculated C 0 and C 3 are composed of metal capacitors, which are temperature independent. I REFP and I REFN come from the same current source and they will have the same temperature characteristics and value. Thus, the ratio can be updated as Because V thp is temperature dependent to the first order [19], ratio_T is proportional to the temperature [13]. Thus, the ratio of the two-type VCO is used to detect temperature.
The complete block diagram of the proposed temperature sensor is shown in Figure 4. The left block is temperature sensor core which is composed of a P-type and a N-type VCO aforementioned. Bias current generator is used to provide the charging/discharging current I REFN /I REFP .
Micromachines 2020, 11, x 4 of 11 Similarly, N-type VCO is composed of Delay_Cell_Ns. The delay value of Delay_Cell_N is approximately the charging time on VOP via IREFP according to aforementioned analysis. Referring to Equation (3), the period of N-type VCO is given as Based on Equation (4) and Equation (5), the ratio between TVCO_P and TVCO_N is calculated C0 and C3 are composed of metal capacitors, which are temperature independent. IREFP and IREFN come from the same current source and they will have the same temperature characteristics and value. Thus, the ratio can be updated as Because Vthp is temperature dependent to the first order [19], ratio_T is proportional to the temperature [13]. Thus, the ratio of the two-type VCO is used to detect temperature.
The complete block diagram of the proposed temperature sensor is shown in Figure 4. The left block is temperature sensor core which is composed of a P-type and a N-type VCO aforementioned. Bias current generator is used to provide the charging/discharging current IREFN/IREFP.  The right block calculates the ratio between periods and transfers temperature to digital codes via two counters. The working principle of the Temperature to Digital is as follows. After RST switches to low, both counters start counting simultaneously. Counter1 counts CLKP to a constant value M and generates a flag signal STOP. When receiving STOP signal, Counter2 ends counting CLKN with a value of P. The counting time of both counters are equal and it can be expressed as The ratio between periods can be obtained Since M is a constant value, P represents the ratio_T and thus is proportional to the temperature. Eventually, P is converted to digital code of Tcode and output for measurement.

Delay Cell
The detail of delay cell is shown in Figure 5. The bias current I REFP and I REFN are composed of NMOS and PMOS working in saturation region separately. The switches M 1 in both delay cells adopt thin-gate MOSFET to achieve fast switching and low conductive resistance. Considering the charging/discharging current of I REFP /I REFN on the magnitude of nA, all the others are thick-gate MOSFET to reduce influence of leakage current. Instead of just using C 0 and C 3 as what is shown in Figure 3, C 1 and C 2 are added to keep the load balance between Delay_Cell_P and Delay_Cell_N. MIM (Metal-Insulator-Meatal) capacitors are adopted for C 0 -C 3 to maintain process and temperature independence.  The right block calculates the ratio between periods and transfers temperature to digital codes via two counters. The working principle of the Temperature to Digital is as follows. After RST switches to low, both counters start counting simultaneously. Counter1 counts CLKP to a constant value M and generates a flag signal STOP. When receiving STOP signal, Counter2 ends counting CLKN with a value of P. The counting time of both counters are equal and it can be expressed as The ratio between periods can be obtained Since M is a constant value, P represents the ratio_T and thus is proportional to the temperature. Eventually, P is converted to digital code of Tcode and output for measurement.

Delay Cell
The detail of delay cell is shown in Figure 5. The bias current IREFP and IREFN are composed of NMOS and PMOS working in saturation region separately. The switches M1 in both delay cells adopt thin-gate MOSFET to achieve fast switching and low conductive resistance. Considering the charging/discharging current of IREFP/IREFN on the magnitude of nA, all the others are thick-gate MOSFET to reduce influence of leakage current. Instead of just using C0 and C3 as what is shown in Figure 3, C1 and C2 are added to keep the load balance between Delay_Cell_P and Delay_Cell_N. MIM (Metal-Insulator-Meatal) capacitors are adopted for C0-C3 to maintain process and temperature independence.

Bias Current Generator
Bias current could be designed with any kind of temperature characteristics, such as proportional, exponential, or independent [12,20]. It is hard to obtain a temperature dependent or independent current with outstanding linearity even at the cost of power or hardware. Instead of designing a high-linearity and temperature-dependent current generator, this paper adopted a simple current generator since the proposed temperature sensor is independent of IBN. Figure 6 shows the architecture of the bias current generator.

Bias Current Generator
Bias current could be designed with any kind of temperature characteristics, such as proportional, exponential, or independent [12,20]. It is hard to obtain a temperature dependent or independent current with outstanding linearity even at the cost of power or hardware. Instead of designing a high-linearity and temperature-dependent current generator, this paper adopted a simple current generator since the proposed temperature sensor is independent of I BN . Figure 6 shows the architecture of the bias current generator. Micromachines 2020, 11,  Figure 6. Bias current generator.
As described in Equation (6), IREFP and IREFN can be removed as long as they have the same temperature characteristics and magnitude. Thus, the bias current generator is simply composed of M1-M4. M1 and M3 work in sub-threshold region and provide the source current Iref.
where μ is mobility, Cox is oxide capacitance, W is transistor width, L is transistor length, m is subthreshold slop factor, VT is thermal voltage (kT/q), Vth is transistor threshold voltage and VDD is the power supply voltage. The source current is mirrored to Delay_Cell_P and Delay_Cell_N for IREFN and IREFP respectively. According to Equation (6) and Equation (7), IREFP and IREFN should be of equal magnitude. Current mismatch between IREFP and IREFN will deteriorate the temperature linearity. To maintain the same magnitude of IREFP and IREFN, the optimal matching among current mirrors (M1/M2/M6 and M4/M5) is required. Thus, the maximum length of 20 μm is adopted for the currentmirror MOSFETs. The current generator is of simple structure but suffers from the influence of the power supply. Thus, a stable and clean power supply is required. The counters consist of two cascaded dividers (divide by two) which are composed of quasistatic D-Flip Flop for low power consumption (shown in Figure 7). Note that no risk presents in the glitches. The D-Flip Flop adopts dual-feedback loop to remove the impact from leakage. When the counting value of Counter1 reaches M, the input clock is blocked, and all dividers in Counter1 and Counter2 stop working and hold the states. Counting value P in Counter2 is output as Tcode for measurement. As described in Equation (6), I REFP and I REFN can be removed as long as they have the same temperature characteristics and magnitude. Thus, the bias current generator is simply composed of M 1 -M 4 . M 1 and M 3 work in sub-threshold region and provide the source current I ref .

Simulation Results
where µ is mobility, C ox is oxide capacitance, W is transistor width, L is transistor length, m is subthreshold slop factor, V T is thermal voltage (kT/q), Vth is transistor threshold voltage and V DD is the power supply voltage. The source current is mirrored to Delay_Cell_P and Delay_Cell_N for I REFN and I REFP respectively. According to Equation (6) and Equation (7), I REFP and I REFN should be of equal magnitude. Current mismatch between I REFP and I REFN will deteriorate the temperature linearity. To maintain the same magnitude of I REFP and I REFN , the optimal matching among current mirrors (M 1 /M 2 /M 6 and M 4 /M 5 ) is required. Thus, the maximum length of 20 µm is adopted for the current-mirror MOSFETs. The current generator is of simple structure but suffers from the influence of the power supply. Thus, a stable and clean power supply is required.

Quasi-Static D-Flip Flop
The counters consist of two cascaded dividers (divide by two) which are composed of quasi-static D-Flip Flop for low power consumption (shown in Figure 7). Note that no risk presents in the glitches. The D-Flip Flop adopts dual-feedback loop to remove the impact from leakage. When the counting value of Counter1 reaches M, the input clock is blocked, and all dividers in Counter1 and Counter2 stop working and hold the states. Counting value P in Counter2 is output as Tcode for measurement. As described in Equation (6), IREFP and IREFN can be removed as long as they have the same temperature characteristics and magnitude. Thus, the bias current generator is simply composed of M1-M4. M1 and M3 work in sub-threshold region and provide the source current Iref.
where μ is mobility, Cox is oxide capacitance, W is transistor width, L is transistor length, m is subthreshold slop factor, VT is thermal voltage (kT/q), Vth is transistor threshold voltage and VDD is the power supply voltage. The source current is mirrored to Delay_Cell_P and Delay_Cell_N for IREFN and IREFP respectively. According to Equation (6) and Equation (7), IREFP and IREFN should be of equal magnitude. Current mismatch between IREFP and IREFN will deteriorate the temperature linearity. To maintain the same magnitude of IREFP and IREFN, the optimal matching among current mirrors (M1/M2/M6 and M4/M5) is required. Thus, the maximum length of 20 μm is adopted for the currentmirror MOSFETs. The current generator is of simple structure but suffers from the influence of the power supply. Thus, a stable and clean power supply is required. Figure 7. Quasi-static D-Flip Flop.

Quasi-static D-Flip Flop
The counters consist of two cascaded dividers (divide by two) which are composed of quasistatic D-Flip Flop for low power consumption (shown in Figure 7). Note that no risk presents in the glitches. The D-Flip Flop adopts dual-feedback loop to remove the impact from leakage. When the counting value of Counter1 reaches M, the input clock is blocked, and all dividers in Counter1 and Counter2 stop working and hold the states. Counting value P in Counter2 is output as Tcode for measurement.

Simulation Results
The proposed temperature sensor was designed in 130 nm CMOS process. It does not need external voltage, current and frequency reference. The layout is shown in Figure 8 and the active area is 0.065 mm 2 . The power supply voltage is 1 V to achieve low power consumption while keeping the bias current generator working properly under all corners and temperatures. The bias current was set to 6 nA with oscillation periods about 240 µs under typical corner and room temperature. The average power is 156 nW at 27 • C while VCO consumes 89%, as shown in Figure 9.
Micromachines 2020, 11, x 7 of 11 The proposed temperature sensor was designed in 130 nm CMOS process. It does not need external voltage, current and frequency reference. The layout is shown in Figure 8 and the active area is 0.065 mm 2 . The power supply voltage is 1 V to achieve low power consumption while keeping the bias current generator working properly under all corners and temperatures. The bias current was set to 6 nA with oscillation periods about 240 μs under typical corner and room temperature. The average power is 156 nW at 27 °C while VCO consumes 89%, as shown in Figure 9.

VCO Simulation
The proposed VCOs were designed and simulated. Figure 10 shows the simulated results. Since the bias generator works in sub-threshold region, the bias current has exponential relation to temperature. Accordingly, both VCO periods have exponential relation to temperature as shown in Figure 10a. Because of the threshold voltage difference between PMOS and NMOS, TVCO_P is larger than TVCO_N. ratio_T is shown in Figure 10b. It is inversely proportional to the temperature with an outstanding linearity which is in good accordance with the analysis in Equation (7). The proposed temperature sensor was designed in 130 nm CMOS process. It does not need external voltage, current and frequency reference. The layout is shown in Figure 8 and the active area is 0.065 mm 2 . The power supply voltage is 1 V to achieve low power consumption while keeping the bias current generator working properly under all corners and temperatures. The bias current was set to 6 nA with oscillation periods about 240 μs under typical corner and room temperature. The average power is 156 nW at 27 °C while VCO consumes 89%, as shown in Figure 9.

VCO Simulation
The proposed VCOs were designed and simulated. Figure 10 shows the simulated results. Since the bias generator works in sub-threshold region, the bias current has exponential relation to temperature. Accordingly, both VCO periods have exponential relation to temperature as shown in Figure 10a. Because of the threshold voltage difference between PMOS and NMOS, TVCO_P is larger than TVCO_N. ratio_T is shown in Figure 10b. It is inversely proportional to the temperature with an outstanding linearity which is in good accordance with the analysis in Equation (7).

VCO Simulation
The proposed VCOs were designed and simulated. Figure 10 shows the simulated results. Since the bias generator works in sub-threshold region, the bias current has exponential relation to temperature. Accordingly, both VCO periods have exponential relation to temperature as shown in Figure 10a. Because of the threshold voltage difference between PMOS and NMOS, T VCO_P is larger than T VCO_N . ratio_T is shown in Figure 10b. It is inversely proportional to the temperature with an outstanding linearity which is in good accordance with the analysis in Equation (7).

Temperature Sensor Simulation
As shown in Figure 10b, ratio_T changes slightly over the temperature range of 0 °C to 80 °C. To maintain a 10-bit level resolution, Counter1 is designed to be 14 bits. According to the Monte Carlo

Temperature Sensor Simulation
As shown in Figure 10b, ratio_T changes slightly over the temperature range of 0 • C to 80 • C. To maintain a 10-bit level resolution, Counter1 is designed to be 14 bits. According to the Monte Carlo simulations, ratio_T is always greater than 1 but less than 2, so Counter2 is set to be 15 bits. The proposed temperature sensor is simulated from 0 • C to 80 • C. Both MOSFET mismatches and MIM capacitor mismatch are taken into account and verified with 20 Monte Carlo runs. The standard deviation of the transistors' mismatch and MIM capacitors' mismatch are 0.3% and 0.03%, respectively, which are provided by the foundry. Figure 11a shows a temperature error of +1.65 • C /−1.84 • C after 1st order polyfit. Figure 11b shows a temperature error of +0.57 • C /−0.44 • C after 2nd order polyfit.
(a) (b) Figure 10 Simulated temperature performance of VCO (a) periods vs temperature (b) ratio_T vs temperature

Temperature Sensor Simulation
As shown in Figure 10b, ratio_T changes slightly over the temperature range of 0 °C to 80 °C. To maintain a 10-bit level resolution, Counter1 is designed to be 14 bits. According to the Monte Carlo simulations, ratio_T is always greater than 1 but less than 2, so Counter2 is set to be 15 bits. The proposed temperature sensor is simulated from 0 °C to 80 °C. Both MOSFET mismatches and MIM capacitor mismatch are taken into account and verified with 20 Monte Carlo runs. The standard deviation of the transistors' mismatch and MIM capacitors' mismatch are 0.3% and 0.03%, respectively, which are provided by the foundry. Figure 11a shows a temperature error of +1.65 °C /−1.84 °C after 1 st order polyfit. Figure 11b shows a temperature error of +0.57 °C /−0.44 °C after 2 nd order polyfit.
The proposed temperature sensor exhibits a systematic error profile dominated by the nonlinearity of ratio_T across the temperature range which is in good accordance with the analysis in Equation (7). After 1 st order polyfit and the nonlinearity removal (Figure 12a), a maximum temperature error of +0.37 °C/−0.32 °C was observed across a 0 °C to 80 °C temperature range. After 2 nd order polyfit and the nonlinearity removal (Figure 12b), a maximum temperature error of +0.17 °C/−0.19 °C was observed. The proposed temperature sensor exhibits a systematic error profile dominated by the nonlinearity of ratio_T across the temperature range which is in good accordance with the analysis in Equation (7). After 1st order polyfit and the nonlinearity removal (Figure 12a), a maximum temperature error of +0.37 • C/−0.32 • C was observed across a 0 • C to 80 • C temperature range. After 2nd order polyfit and the nonlinearity removal (Figure 12b), a maximum temperature error of +0.17 • C/−0.19 • C was observed.

Temperature Sensor Simulation
As shown in Figure 10b, ratio_T changes slightly over the temperature range of 0 °C to 80 °C. To maintain a 10-bit level resolution, Counter1 is designed to be 14 bits. According to the Monte Carlo simulations, ratio_T is always greater than 1 but less than 2, so Counter2 is set to be 15 bits. The proposed temperature sensor is simulated from 0 °C to 80 °C. Both MOSFET mismatches and MIM capacitor mismatch are taken into account and verified with 20 Monte Carlo runs. The standard deviation of the transistors' mismatch and MIM capacitors' mismatch are 0.3% and 0.03%, respectively, which are provided by the foundry. Figure 11a shows a temperature error of +1.65 °C /−1.84 °C after 1 st order polyfit. Figure 11b shows a temperature error of +0.57 °C /−0.44 °C after 2 nd order polyfit.
The proposed temperature sensor exhibits a systematic error profile dominated by the nonlinearity of ratio_T across the temperature range which is in good accordance with the analysis in Equation (7). After 1 st order polyfit and the nonlinearity removal (Figure 12a), a maximum temperature error of +0.37 °C/−0.32 °C was observed across a 0 °C to 80 °C temperature range. After 2 nd order polyfit and the nonlinearity removal (Figure 12b), a maximum temperature error of +0.17 °C/−0.19 °C was observed. The proposed temperature sensor was verified under corners. The results are shown in Figure 13. The SS corner shows the best performance while the worst performance can be observed in the FF (Fast-Fast) corner. This is because in the FF corner, the MOSFETs have the lowest threshold voltage. When we increase the reference current, the oscillation period reduces. That results in a worse approximation in Equation (2) and poor linearity.
The proposed temperature sensor was verified under corners. The results are shown in Figure  13. The SS corner shows the best performance while the worst performance can be observed in the FF (Fast-Fast) corner. This is because in the FF corner, the MOSFETs have the lowest threshold voltage. When we increase the reference current, the oscillation period reduces. That results in a worse approximation in Equation (2)

Conclusions
A CMOS thyristor based temperature sensor was proposed in this paper. Two VCOs composed of CMOS thyristor with different threshold voltage were exploited. The period ratio between two VCOs extracts the temperature information. The ratio calculation is simply realized by two counters where a constant-value counter stops another free running counter. Therefore, the external clock reference was avoided. A diode-connected bias current generator was exploited for its simplicity and little impact on the temperature extraction. The prototype was designed in 130 nm CMOS process and occupies an active area of 0.06 mm 2 . According to the post-layout simulation, it achieves an  Table 1 compares the proposed sensor with the state-of-the-art temperature sensors. The proposed sensor does not need any external clock references or voltage regulators. It is designed with simple current mirrors and CMOS thyristors, and it achieves a competitive inaccuracy of +0.37/−0.32 • C and low power consumption of 156 nW within a compact area of 0.06 mm 2 .

Conclusions
A CMOS thyristor based temperature sensor was proposed in this paper. Two VCOs composed of CMOS thyristor with different threshold voltage were exploited. The period ratio between two VCOs extracts the temperature information. The ratio calculation is simply realized by two counters where a constant-value counter stops another free running counter. Therefore, the external clock reference was avoided. A diode-connected bias current generator was exploited for its simplicity and little impact on the temperature extraction. The prototype was designed in 130 nm CMOS process and occupies an active area of 0.06 mm 2 . According to the post-layout simulation, it achieves an inaccuracy of +0.37/−0.32 • C from 0 • C to 80 • C after 1st order polyfit and nonlinearity removal with a power consumption of 156 nW.

Conflicts of Interest:
The authors declare no conflict of interest.