F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application

In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET.


Introduction
Tunnel field-effect transistor (TFET) has been regarded as a promising candidate to replace the metal-oxide-semiconductor FET (MOSFET) for a low power device because its subthreshold swing (SS) can be scaled less than 60 mV/dec [1][2][3][4][5][6][7][8]. However, Si-based TFET suffers from low-level on-state current (I ON ) due to its limited band-to-band tunneling (BTBT) rate. Furthermore, there are just a few reports which have demonstrated sub-60 mV/dec SS with the experimental devices. Several strategies have been proposed to address these issues [9][10][11][12][13][14][15][16][17][18][19]. Among them, L-shaped TFET has efficiently improved I ON and SS by increasing BTBT junction area and by decreasing BTBT barrier width (W TUN ) with the help of a novel structure [20]. In spite of these advantages, there is a drawback that turn-on voltage (V ON ), which is defined as gate voltage (V GS ) when BTBT starts to occur, becomes much higher than conventional TFET. It is contradictory to apply the low-power logic elements [21,22]. Therefore, in this manuscript, a new-structure TFET is proposed to address the technical issue of L-shaped TFET maintaining its advantages. Figure 1a shows a schematic structure of proposed device named 'F-shaped TFET' because the shape of source is similar to the fingers. It resembles an L-shaped TFET except the ultra-thin sources which are surrounded by intrinsic (or lightly doped) Si regions [20]. It is expected that the F-shaped TFET can reduce V ON with the help of electric field crowding effect as the thickness of source (T S ) gets thinner. In order to examine the electrical characteristics of F-shaped TFET, technology computer-aided design (TCAD) simulation is performed [23]. Nonlocal BTBT, Shockley-Read-Hall lightly doped to suppress ambipolar behavior.
This manuscript is composed as follows. First, the electrical performance of the F-shaped TFET with a single-source region (i.e., one finger) is examined (Figure 1b). Many parameters such as TS, lateral length of tunnel region (LT), and space above and below source (TE) have been set as variables. In Section 2, the influences of TS, LT, and TE have been discussed. In Section 3, feasibility for the better performance with F-shaped TFET is examined by adding one more source region (i.e., two fingers) and its design is optimized by adjusting the distance between two source regions (TI). In Section 4, the optimized design is compared with the conventional L-shaped TFET. In Section 5, an exemplary process flow for the fabrication of F-shaped TFET is proposed.   Figure 2 shows transfer characteristics as LT changes from 10 to 2 nm. It shows that VON increases as LT decreases. This is explained by the surface potential depending on LT with the help of  This manuscript is composed as follows. First, the electrical performance of the F-shaped TFET with a single-source region (i.e., one finger) is examined (Figure 1b). Many parameters such as T S , lateral length of tunnel region (L T ), and space above and below source (T E ) have been set as variables. In Section 2, the influences of T S , L T , and T E have been discussed. In Section 3, feasibility for the better performance with F-shaped TFET is examined by adding one more source region (i.e., two fingers) and its design is optimized by adjusting the distance between two source regions (T I ). In Section 4, the optimized design is compared with the conventional L-shaped TFET. In Section 5, an exemplary process flow for the fabrication of F-shaped TFET is proposed. Figure 2 shows transfer characteristics as L T changes from 10 to 2 nm. It shows that V ON increases as L T decreases. This is explained by the surface potential depending on L T with the help of the voltage division model in series-connected capacitors [24]. In detail, if L T decreases, the surface potential at the fixed V GS is reduced because the capacitance of the fully depleted Si tunnel region increases; results in a high V ON . On the other hand, the average SS (SS AVG ) decreases if L T decreases ( Figure 2 and its inset). It is attributed to the smaller W TUN (at V GS = V ON ) with the smaller L T [24]. Similarly, I on increases as L T decreases, because the W TUN at on-state decreases. The optimum L T is determined as 4 nm, since the increase of V ON is significant while the reduction of SS AVG is negligible as L T becomes less than 4 nm (inset of Figure 2).

Length of Tunnel Region (L T )
Micromachines 2019, 10, x 3 of 10 the voltage division model in series-connected capacitors [24]. In detail, if LT decreases, the surface potential at the fixed VGS is reduced because the capacitance of the fully depleted Si tunnel region increases; results in a high VON. On the other hand, the average SS (SSAVG) decreases if LT decreases ( Figure 2 and its inset). It is attributed to the smaller WTUN (at VGS = VON) with the smaller LT [24]. Similarly, ION increases as LT decreases, because the WTUN at on-state decreases. The optimum LT is determined as 4 nm, since the increase of VON is significant while the reduction of SSAVG is negligible as LT becomes less than 4 nm (inset of Figure 2).   Figure 3b, electric field at sharp source corner (ECOR) is much larger than that for flat source region (EFLAT) due to field crowding effect [25]. Because VON and ION of TFETs sensitively depend on electric field at source-to-channel junction, the source corner and the flat source regions can be regarded as different TFETs; FETCOR and FETFLAT. In other words, F-shaped TFET can be regarded as FETCOR and FETFLAT connected in parallel as shown in Figure 3g. If TS decreases, the FETCOR contributes more to ID than FETFLAT. As a result, the normalized ID by TS is increased because FETCOR has higher current than FETFLAT.

Source Thickness (TS)
Unlike to ION, VON is solely determined by FETCOR which is turned on first. Although TS decreases (i.e., the portion of FETCOR increases), the ECOR is unchanged. Therefore, VON is not affected by TS from 40 to 10 nm (Figure 3b-d). On the other hand, if TS becomes less than 10 nm, FETFLAT is completely disappeared and FETCOR at two corners starts to be merged (Figure 3e,f). As a result, the magnitude of electric field is increased further and VON starts to be decreased. Considering process capability, TS is optimized as 5 nm.  Figure 3b, electric field at sharp source corner (E COR ) is much larger than that for flat source region (E FLAT ) due to field crowding effect [25]. Because V ON and I ON of TFETs sensitively depend on electric field at source-to-channel junction, the source corner and the flat source regions can be regarded as different TFETs; FET COR and FET FLAT . In other words, F-shaped TFET can be regarded as FET COR and FET FLAT connected in parallel as shown in Figure 3g. If T S decreases, the FET COR contributes more to I D than FET FLAT . As a result, the normalized I D by T S is increased because FET COR has higher current than FET FLAT .
Unlike to I ON , V ON is solely determined by FET COR which is turned on first. Although T S decreases (i.e., the portion of FET COR increases), the E COR is unchanged. Therefore, V ON is not affected by T S from 40 to 10 nm (Figure 3b-d). On the other hand, if T S becomes less than 10 nm, FET FLAT is completely disappeared and FET COR at two corners starts to be merged (Figure 3e,f). As a result, the magnitude of electric field is increased further and V ON starts to be decreased. Considering process capability, T S is optimized as 5 nm.

Space Above and Below Source (TE)
As discussed in Figure 1, unlike the L-shaped TFET, the source of the F-shaped TFET is surrounded by lightly doped Si regions. Therefore, it is worthwhile to study about the influence of TE on electrical characteristics of F-shaped TFET because it can influence on electric field crowding. As shown in Figure 4, the VON slightly decreases as the TE increases due to the increase of electric

Space Above and Below Source (T E )
As discussed in Figure 1, unlike the L-shaped TFET, the source of the F-shaped TFET is surrounded by lightly doped Si regions. Therefore, it is worthwhile to study about the influence of T E on electrical characteristics of F-shaped TFET because it can influence on electric field crowding. As shown in Figure 4, the V ON slightly decreases as the T E increases due to the increase of electric field crowding effect. In other word, the number of electric field flux is increased since the tunnel junction is affected by the larger gate area. Consequently, band bending at tunnel junction becomes abrupt, and hence decreases V ON . However, large T E is contradictory to the process capability (i.e., abrupt etching profile). In addition, if T E increases more than 15 nm, the decrease of V ON is negligible as shown in the inset of Figure 4. Based on the above results, T E is optimized as 15 nm.
Micromachines 2019, 10, x 5 of 10 field crowding effect. In other word, the number of electric field flux is increased since the tunnel junction is affected by the larger gate area. Consequently, band bending at tunnel junction becomes abrupt, and hence decreases VON. However, large TE is contradictory to the process capability (i.e., abrupt etching profile). In addition, if TE increases more than 15 nm, the decrease of VON is negligible as shown in the inset of Figure 4. Based on the above results, TE is optimized as 15 nm.

Optimized F-Shaped TFET
In Section 2, the parameters (TS, LT, TE) which can influence on the electric field crowding effect have been optimized by several simulations. Although F-shaped TFET can achieve the higher normalized ID (i.e., current density) as TS decreases, the smaller BTBT junction area is problematic in terms of total current for its real application. It can be addressed by adding an additional source (i.e., figure) as shown in Figure 5a. From the previous results in Section 2.3, it can be expected that the electrical characteristic of F-shaped TFET with multiple source regions is sensitively affected by the distance between the two sources (TI). Therefore, the influences of TI on the electrical performance of F-shaped TFET are investigated to determine an optimum TI. Figure 5b,c shows the effect of TI on the magnitude of the electric field at source-to-channel junction. If TI gets smaller, the electric field of both sources start to become merged and each electric field at tunnel junction is decreased. As a result, VON is increased as shown in Figure 5d and its inset. The result is well corresponded to the phenomena discussed in Section 2.3. Considering the process capability and the influence of TI on the electrical performance, TI is optimized as 30 nm.

Optimized F-Shaped TFET
In Section 2, the parameters (T S, L T , T E ) which can influence on the electric field crowding effect have been optimized by several simulations. Although F-shaped TFET can achieve the higher normalized I D (i.e., current density) as T S decreases, the smaller BTBT junction area is problematic in terms of total current for its real application. It can be addressed by adding an additional source (i.e., figure) as shown in Figure 5a. From the previous results in Section 2.3, it can be expected that the electrical characteristic of F-shaped TFET with multiple source regions is sensitively affected by the distance between the two sources (T I ). Therefore, the influences of T I on the electrical performance of F-shaped TFET are investigated to determine an optimum T I . Figure 5b,c shows the effect of T I on the magnitude of the electric field at source-to-channel junction. If T I gets smaller, the electric field of both sources start to become merged and each electric field at tunnel junction is decreased. As a result, V ON is increased as shown in Figure 5d and its inset. The result is well corresponded to the phenomena discussed in Section 2.3. Considering the process capability and the influence of T I on the electrical performance, T I is optimized as 30 nm.   Figure 6a shows a schematic structure of L-shaped TFET studied in [24]. Most of design parameters such as L G , T OX , N S , N D , N B , W FN and W are the same as that for the F-shaped TFET. In case of L-shaped TFET, T S is set by 70 nm which is the same as T G in optimized F-shaped TFET; T S = 5 nm, T E = 15 nm, and T I = 30 nm, T G = 2T S + 2T E + T I (Figure 5a). On the other hand, L T is set as 4 nm or 6 nm to compare with F-shaped TFET in two points of view; the same dimension or V ON . TE = 15 nm, and TI = 30 nm, TG = 2TS + 2TE + TI (Figure 5a). On the other hand, LT is set as 4 nm or 6 nm to compare with F-shaped TFET in two points of view; the same dimension or VON.

Comparison with L-Shaped TFET
In case of 4 nm-LT, L-shaped TFET has the same dimension as the optimized F-shaped TFET discussed in Section 2.1. As shown in Figure 6b, it is clear that the VON of F-shaped TFET is about 0.4 V lower than that for L-shaped TFET in spite of the same dimension with the help of the electric field crowding effect. The inset of Figure 6b confirms that VON of F-shaped TFET is always smaller than that for L-shaped TFET with the same LT.
If the LT of L-shaped TFET is 6 nm, its VON becomes the same as that of an optimized F-shaped TFET (Figure 6b). Comparing both TFETs with the same VON, the ION, and SSAVG of F-shaped TFET are 4.8 times higher and 7 mV/dec lower than that for L-shaped TFET, respectively. The results are clearly attributed to the enhanced BTBT rate with the geometrical merits (i.e., field crowding), because F-shaped TFET has smaller BTBT junction area than L-shaped TFET. In case of 4 nm-L T , L-shaped TFET has the same dimension as the optimized F-shaped TFET discussed in Section 2.1. As shown in Figure 6b, it is clear that the V ON of F-shaped TFET is about 0.4 V lower than that for L-shaped TFET in spite of the same dimension with the help of the electric field crowding effect. The inset of Figure 6b confirms that V ON of F-shaped TFET is always smaller than that for L-shaped TFET with the same L T .
If the L T of L-shaped TFET is 6 nm, its V ON becomes the same as that of an optimized F-shaped TFET (Figure 6b). Comparing both TFETs with the same V ON , the I ON , and SS AVG of F-shaped TFET are 4.8 times higher and 7 mV/dec lower than that for L-shaped TFET, respectively. The results are clearly attributed to the enhanced BTBT rate with the geometrical merits (i.e., field crowding), because F-shaped TFET has smaller BTBT junction area than L-shaped TFET. Figure 7 summarizes an exemplary self-align process flow for F-shaped TFET with multiple source regions; fingers. (Figure 7a) P-type Si layers doped by 10 20 cm −3 and 10 15 cm −3 are alternately stacked on Si-on-insulator (SOI) wafer through epitaxial layer growth processes. After defining an active region, SiO 2 hard-mask is deposited by a chemical vapor deposition (CVD). This layer is also helpful to passivate active sidewall. (Figure 7b) Mesa patterning is followed by SiO 2 buffer layer deposition. (Figure 7c) After dummy gate formation by deposition and etch-back processes, drain region is defined by arsenic (As) ion implantation and rapid thermal annealing (RTA). (Figure 7d) SiO 2 deposition is followed by chemical-mechanical polishing (CMP) to expose the dummy gate. (Figure 7e) After selectively removing the dummy gate and SiO 2 buffer layer, selective epitaxial layer growth (SEG) is performed to form ultra-thin tunnel region. (Figure 7f) The gate stack is formed by high-k/metal gate atomic layer deposition (ALD) processes. The back-end-of-line process is not shown here.  Figure 7 summarizes an exemplary self-align process flow for F-shaped TFET with multiple source regions; fingers. (Figure 7a) P-type Si layers doped by 10 20 cm −3 and 10 15 cm −3 are alternately stacked on Si-on-insulator (SOI) wafer through epitaxial layer growth processes. After defining an active region, SiO2 hard-mask is deposited by a chemical vapor deposition (CVD). This layer is also helpful to passivate active sidewall. (Figure 7b) Mesa patterning is followed by SiO2 buffer layer deposition. (Figure 7c) After dummy gate formation by deposition and etch-back processes, drain region is defined by arsenic (As) ion implantation and rapid thermal annealing (RTA). (Figure 7d) SiO2 deposition is followed by chemical-mechanical polishing (CMP) to expose the dummy gate. (Figure 7e) After selectively removing the dummy gate and SiO2 buffer layer, selective epitaxial layer growth (SEG) is performed to form ultra-thin tunnel region. (Figure 7f) The gate stack is formed by high-k/metal gate atomic layer deposition (ALD) processes. The back-end-of-line process is not shown here.

Summary
A novel F-shaped TFET is proposed and its device physics and operating mechanisms are studied in detail by using two-dimensional TCAD simulations. The results confirm that it can achieve a relatively lower VON (~0.6 V) than that for L-shaped TFET (~1.0 V) with the same LT. In addition, the current drivability of F-shaped TFET can be further improved by adding additional sources (fingers). Last of all, F-shaped TFET is expected to be fabricated by self-aligned processes. Therefore, F-shaped TFET can be regarded as one of the promising candidates for low-power digital logic applications.

Summary
A novel F-shaped TFET is proposed and its device physics and operating mechanisms are studied in detail by using two-dimensional TCAD simulations. The results confirm that it can achieve a relatively lower V ON (~0.6 V) than that for L-shaped TFET (~1.0 V) with the same L T . In addition, the current drivability of F-shaped TFET can be further improved by adding additional sources (fingers). Last of all, F-shaped TFET is expected to be fabricated by self-aligned processes. Therefore, F-shaped TFET can be regarded as one of the promising candidates for low-power digital logic applications.