Multiple-output DC-DC converters with a reduced number of active and passive components

Multiple-output converters have been widely used where individual outputs are required. Compared with conventional separate converters, the advantage of multiple outputs is to have a lower number of active and passive components. In this paper, first, a pulse-width-modulation (PWM)-pulse-frequency-modulation (PFM) method is used for two-output converters that have only one coil and one active switch. Secondly, three-output converter topologies are proposed where the third output is controlled by phase delay (PD). These converters need only two coils and two active switches to regulate three outputs. How to obtain PD at different switching frequencies is discussed next, and a PWM-PFM-PD controlled five-output buck converter is presented. The proposed solution uses only two active switches and two magnetic cores to adjust five-output voltages independently. A modeling and digital control method are proposed in order to regulate the five output voltages. A prototype circuit with independent 15 V/1.5 A, 12 V/1.5 A, 5 V/0.8 A, −5 V/0.6 A and 3.3 V/0.45 A outputs is assembled to validate the analysis, and it was proved that it regulates the output voltages at different loads.


Introduction
The size and cost of a multiple output converter can be less than that of separate converters. However, one of the main drawbacks of a multiple output converter is its cross regulation. One way to obtain multiple outputs is to have a single power converter such as a flyback or forward converter with multiple secondary windings. Usually, these converters regulate only the output that is defined as the master one; the other outputs depend on the load conditions [1]. If there are no conduction losses and no leakage inductance, closed-loop regulation of the master output will regulates all the outputs in continuous conduction mode (CCM) [1]. However, perfect cross-regulation in real life may not be easy to achieve. Therefore, post regulators are applied to adjust the additional outputs [2,3].
The single-switch pulse-width modulation (PWM)-pulse-frequency modulation (PFM) converter uses PFM in order to regulate the second output voltage [4,5]. This converter has two separate inductors. One of the output circuits operates in CCM, while the other operates in discontinuous conduction mode (DCM). Both outputs can be controlled independently by orthogonally modulating both the duty cycle and the switching frequency of the single active switch. The work described in [6] is based on such a PWM-PFM method, however, instead of DCM, the second output is controlled in zero-current-switching (ZCS) quasi-resonant (QR) mode. A further PWM-phase delay (PD) control method produces a regulated third output [7,8]. In this case, two active switches are

PWM-PFM Controlled Two-Output Converters
The PWM-PFM method for two-output dc-dc converters with one active switch is introduced in [4]. In the paper, one output is controlled by PWM and the other by PFM. One of the inductors is designed for CCM, and the other for DCM. While the duty cycle of the switch determines both output voltages, its switching frequency only adjusts the output voltage in DCM. Hence both output voltages can be regulated independently, subject to DCM constraints.
Another way to obtain auxiliary outputs without using additional active switches is to place multiple windings onto the inductor of a buck converter [15,16]. The primary of the coupled inductor is used for the first output, and the secondary voltage is rectified and filtered to create a second output. This second output depends on the turns ratio of the coupled inductor, n. The polarity of the coupled inductor determines whether energy is transferred to the secondary in flyback or forward mode.
The first output is regulated by the PWM of the active switch, while a zener diode or a linear regulator is often included on the secondary side to regulate the second output voltage [2,3]. These methods reduce the efficiency of the converter.
PFM can be used as a control parameter to regulate the second output when it is operated in DCM. The magnetizing inductance of the coupled inductor is used for the PWM output, and the leakage inductance is used for the PFM output. The two-output buck converters that are shown in Figure 1a are explained in this chapter. Note that the exact same approach is possible for other dc-dc converters, e.g., the boost and buck-boost converters that are depicted in Figure 1b

Two-Output Fly-Buck Converter
Using a fly-buck converter ( Figure 1a) as a simple two-output converter is proposed in [17,18]. Only one of the outputs is controlled, causing severe cross-regulation issues for the second output. In order to remediate the cross-regulation problem, adding an active switch to the secondary of the coupled inductor was proposed in [19].
As an alternative to the conventional uncontrolled fly-buck converter, Figure 2a shows a two-output buck converter whose second output is obtained from a flyback type coupled inductor with magnetizing inductance L 1 and substantial leakage inductance L 2 . The steady-state equation of the first output voltage v 1 is the same as for the conventional buck converter. When the first switch Q 1 is off, energy is transferred to the secondary switch. The steady-state equation of the second output voltage v 2 is: where n is the turns ratio of the coupled inductor, V in is the input voltage, δ is the duty cycle of the switch Q 1 , and β is the normalized (t s ) demagnetizing interval of the leakage inductor L 2 (see Figure 2b). As shown in (1), the switching period t s is a possible control parameter of V 2 . This explains why the switching frequency, f s = 1/t s , can be used to restrain the cross-regulation problem without adding additional components. Figure 3 is constructed from (1) to show the regulation that is possible with the switching frequency. From Figure 3 it can be deduced that it is preferable to adjust the second output in the fly-buck mode when the duty cycle is higher than 50%. This is because more energy can be transferred during the switch-off period to support a wider range of load conditions.   Table 1. Results are obtained by using (1).

Design Criteria
L 2 's value depends on the turns ratio of the coupled inductor, n. However, n needs to be known to calculate L 2 . The minimum value of n is: and so n can be calculated from (1) by numerical iteration. If a higher L 2 inductance is needed, it can be increased by additional inverse windings [20] or by changing the overlap ratio of the secondary winding [21].
Inductor L 2 is needed to adjust the second output v 2 . L 2 's inductance should be relatively small compared to the magnetizing inductance in order to correctly operate this second output in DCM. Moreover, L 2 is also used to restrict the peak value of the inductor current i L2,pk . It follows that For the fly-buck converter, the peak current of ni L2 should be lower than the minimum current of i L1 if a conventional buck converter is used: where ∆i L1 is ripple of i L1 , as i L1 -ni L2 cannot be negative because of the diode D 1 . When this condition is false, i L1 decreases and the first output voltage drops. Instead of a diode, a MOSFET can be used to allow i L1 -ni L2 to become negative.

Experimental Results
A fly-buck converter whose output voltages are 15 V/1.5 A and 5 V/0.8 A was built. The parameters of the prototype are shown in Table 1. The 15 V output was chosen as the reference output because the available power from the reference output is higher than that from the second output. Table 1. Components of the fly-buck and forward-buck two-output prototypes.

Component
Value Model CD214B-B230LF Figure 4 shows that v 2 changes for different switching frequencies. The duty cycle δ is kept the same for both these plots. There is a small change in v 1 when f s changes because of cross-regulation. Figure 4 shows that the voltage range of the second output is slightly larger when δ is higher.  In Table 2, the control values and efficiencies of the circuit at different loads are given. When the first output current i 1 is changed from 0.75 A to 1.5 A, δ must be increased from 58.7% to 64.5%. Note that δ is the control parameter of v 2 . Therefore, it is possible to increase f s from 27 kHz to 84 kHz to keep v 1 at 5 V. Even if f s is not a control parameter of v 1 , δ is slightly changed from 64.5% to 64.2% when the second output current i 2 is changed from 0.8 A to 0.2 A. The reason for this slight change is again due to cross-regulation issue. An appropriate PWM-PFM method can keep the output voltages the same at both operating points.  15 As shown in Table 2, the minimum efficiency of the circuit is 91.4% when i 1 is at the minimum operating point. The more i 1 increases, the more the efficiency increases. The efficiency at the lower switching frequencies is generally lower than the efficiency at the higher switching frequencies. This is because the ripple of i L2 decreases when f s increases. The conduction losses also decrease because of this reason. Figure 5a shows a two-output forward-buck converter where the second output is obtained by introducing a forward-mode coupled inductor. The circuit is the same as for the fly-buck circuit, except that the polarity of the coupled inductor is reversed. When Q 1 is switched on, energy stored in magnetizing inductor is transferred to the secondary. The conversion ratio of the first output voltage M 1 is the same as for the conventional buck converter. The value for the second output voltage v 2 can be calculated by the following equation:

Two-Output Forward-Buck Converter
As shown in Figure 6 and (5), the switching frequency t s = 1/f s can be used to adjust the second output voltage. Also, Figure 6 shows that the conversion ratio range increases when the duty cycle δ decreases. This is the opposite situation to that of the fly-buck converter (see Figures 3 and 6). The polarity of the transformer can be selected, depending on δ as required by the application, to create the widest possible voltage range for the second output. In particular, if δ is less than 0.5, the forward-buck topology is selected, otherwise the fly-buck topology is more appropriate.   Table 1. Results are obtained by using (5).

Design Criteria
The minimum value of the turns ratio n is: The initial n-value can be computed from (5) by using numerical procedures.
A leakage inductance L 2 is needed to adjust the second output v 2 . The peak value of the inductor current i L2,pk is required for the selection process: For the forward-buck type, the average of the current i L2 must be lower than the minimum current of i L1 : This is because i L1 + ni L2 cannot be negative because of the diode D 1 . This is the same reasoning as applies to the fly-buck type.

Experimental Results
A forward-buck converter with outputs of 12 V/1.5 A and 5 V/0.6 A was designed and built. The parameters of the prototype, which were the same as for the fly-buck converter, are shown in Table 1. Figure 7 shows the experimental results of the change in v 2 versus f s , same as for the fly-buck converter. The change in f s from 50 kHz to 500 kHz causes (approximately) a 3.5 V drop in v 2 when δ = 0.42. v 1 changes only +0.4 V from 50 kHz to 500 kHz, because of cross-regulation issues. This is enough to control the two-outputs independently, as Table 3 shows. The control values and efficiency of the forward-buck converter under different load conditions are also shown in Table 3. The efficiency at lower switching frequencies is generally lower than that at higher switching frequencies, matching the behavior of the fly-buck converter.

PWM-PD Controlled Three-Output Converters
The PWM-PD method for non-isolated three-output dc-dc converters with two active switches is presented in [7,8]. It requires two square wave voltages and builds a third square voltage from them. The first and the second output voltage are controlled by δ 1 and δ 2 , respectively. The third output is adjusted by the duty cycle δ 3 , which is equal to the total of δ PD and δ 2 in [7,8]. This is why a third switch is not needed to obtain a third output; however, additional diodes and an extra magnetic core must be added [7,8].
A PWM-PD controlled three-output converter which needs only two inductors is shown in Figure 8. In order to obtain the third adjustable output, additional windings are added to the inductors L 1 and L 2 of the buck converters. To use this method, the switching frequencies of the active switches should be the same. The polarity of the windings can be chosen in two ways, and boost or buck-boost converters may be used instead of buck converters. The secondaries of the coupled inductors are connected in series so that the combined leakage inductance of the coupled inductors, L 3 , can be used to adjust the third output. This third output is adjusted by the duty cycle δ 3 , which is a function of the phase delay δ PD between the gate signals of Q 1 and Q 2 .

A PWM-PD Controlled Fly-Buck Type Three-Output Converter
The secondary windings of the coupled inductors of the two buck converters are connected in series. L 3 is equal to the total leakage inductance of the first and second coupled inductors. The polarity of the secondaries is similar to that of a flyback converter. When the voltage across both magnetizing inductors is negative, the energy is transferred to the secondary. The duty cycle δ 3 of this third output square wave is as shown in Figure 9a. The third output voltage v 3 of the fly-buck type converter can thus be calculated as:

Design Criteria
The minimum value of n is: The current passing through L 3 , i L3,pk , is formulated as: Figure 9. The gate voltage of the switches v G1 and v G2 , and the voltage waveform of the tertiary inductor, v L3 of (a) a fly-buck type converter and (b) a forward-buck type three-output converter.

Experimental Results
A fly-buck three-output converter was built to verify the preceding analysis. The parameters of the prototype were the same as for the two-output converters and are shown in Table 1. Figure 10 shows the experimental results for v 3 and how they change as a function of the phase delay. The first output, 15 V/1.5 A, and the second, 12 V/1.5 A, are kept the same for different third-output voltages. The cross-regulation at 50 kHz is 2-3 V for v 1 and v 2 as shown in Figure 10. Note that the change in v 1 and v 2 is only 0.2 V at higher frequencies.  Table 4 shows the operating points, control parameters and efficiencies of the converter for different loads. When δ PD or δ 3 is chosen as the control parameter for the third output, the output voltages can be kept the same at different loads. For example, when only the third load is changed in the first four rows, then the related control parameter, the phase delay, is able to keep the third output constant, i.e., 3.3 V.
The efficiency of the converter η is 94.4% at the rated load, and it can be even higher for other loads, as shown in Table 4. Table 4. Experimental results with a fly-buck type three-output converter (V in = 24 V and f s = 150 kHz). 15

A PWM-PD Controlled Forward-Buck Type Three-Output Converter
The forward-buck type three-output converter is the same as a fly-buck type three-output converter, except for the polarity of the secondary windings. The polarity of the secondaries is similar to that of a forward converter. When the voltage across both magnetizing inductors is positive, energy is transferred to the secondary.
The δ 3 of the forward-buck circuit is: as shown in Figure 9b. The third-output voltage v 3 can be calculated as: 3.

Design Criteria
The minimum value of n is: The current of L 3 , i L3,pk , is formulated as:

Experimental Results
The same components used for the fly-buck type were used to build a forward-buck three-output converter. Figure 11 shows the experimental results of v 3 , as a function of δ PD . Figure 11 shows that cross-regulation for the forward-buck converter at 50kHz is appreciably worse than at the other switching frequencies.
150kHz 300kHz Figure 11. Experimentally measured output voltages of the proposed forward-buck three-output converter depending on different phase delays δ PD (V in = 24 V, R 1 = 10 Ω, R 2 = 8 Ω and R 3 = 7.5 Ω). Table 5 shows the operating points, control parameters, and efficiencies of the forward-buck type converter for different loads. It can be seen that δ PD or δ 3 is a valid control parameter of the third output. The efficiency of the converter η is 94.4% at the rated load. The efficiency values of the converter are similar to those for the fly-buck type.
As is evident from (10) and (14), δ 3 is the obvious control parameter for the third output. The maximum range of δ 3 is 50% when δ 1 and δ 2 are 50%. Table 5. Experimental results for a forward-buck type three-output converter (V in = 24 V and f s = 150 kHz).

PWM-PFM-PD Controlled Five-Output Converters
In this section, the PWM-PFM controlled two-output and the PWM-PD controlled three-output converters are merged to obtain five independently controlled outputs. The resulting PWM-PFM-PD controlled five-output converter, which has only two coils and two active switches, is shown in Figure 12a. In order to obtain the extra three adjustable outputs, two additional windings are added to the inductors of the buck converters and flyback diodes are then connected to the secondaries of these coupled inductors to construct the third and the fourth output. The leakage inductors L 3 and L 4 are designed to control the third and the fourth output voltage in DCM. Therefore, the total of the leakage inductance of the coupled inductors L 5 , which is obtained by connecting the tertiaries of the coupled inductors in series with diodes, can be used to adjust the fifth output by PD.  In order to use the PD method with non-equal frequency waveforms, it is proposed that the second switch operates in "burst" mode. The second switching frequency f 2 is synchronized to the first switching frequency, f 1 = 1/t s . It is then possible to insert a PD between the starting points of the signals as shown in Figure 12b,c. Frequency f 2 can be represented by: The PWM signal is divided into segments depending on the required number of pulses, k. In burst mode, the turn-on time of the second signal is affected by the demagnetizing ratio of the fourth inductor β 2 as can be seen in Figure 12b,c. When the inductor current drops to zero, the next segment is triggered. The inductor voltage waveform of the fifth output for the fly-buck type converter v L5 is divided into k pulses as shown in Figure 12b. δ 3 in burst mode is: The range of δ 3 in burst mode is reduced by k and β 2 for the fly-buck type's fifth output. As shown in Figure 12c, instead of dividing the PWM signal into equal sub-pulses, there is a gap between the pulses in the case of a forward-buck type converter. This gap is needed for the demagnetizing duration of i L4 to operate the fourth output in DCM. In other words, the demagnetizing duration does not affect the range of δ 3 , and (13) can be used for the forward-buck type converter in burst mode. The forward-buck type converter for the fifth output is preferable to the burst mode as it has a wider effective range and operates with less adverse effects.

Topology Comparison
One method to reduce the size of a converter is to reduce the total number of components, e.g., by sharing common functionality as mentioned in the previous sections. Comparisons in this respect for the proposed five-output converter with similar research in [22][23][24][25] are summarized in Table 6. Figure 13 shows the reviewed multiple-output dc-dc converters, i.e., (a) the integrated multiple-output synchronous buck converter (IMOSBC) from [22]; (b) the multiple-output narrow-band resonant converter (MONBRC) from [23]; (c) the multiple-output two-transistor forward converter (MOTTFC) from [24] and (d) the single-input multiple-output dc-dc converter (SIMOC) from [25].  Figure 13. Multiple-output dc-dc converters from the literature: which are (a) an integrated multiple-output synchronous buck converter (IMOSBC) in [22]; (b) a multiple-output narrow-band resonant converter (MONBRC) in [23]; (c) a multiple-output two-transistor forward converter (MOTTFC) in [24] and (d) a single-input multiple-output dc-dc converter (SIMOC) in [25].
The IMOSBC uses fewer switches and diodes than those of its individual converters, but Figure 13a shows that it does not have less magnetic components. The MOTTFC from [24] and SIMOC from [25] are conceived to minimize cross-regulation, because the converters can not regulate all their outputs independently. Although the MONBRC regulates all outputs independently, it has more components than those of five individual converters, as shown in Figure 13b. As can be seen in Table 6, the proposed converter has the least number of components per output when compared to the others.
TMONBRC, MOTTFC and SIMOC are designed for high conversion ratios. However, the proposed topology can use forward converters instead of the buck converters for its first and second outputs, thereby also achieving high gain.

Design Criteria
The design rules for the PWM-PFM and PWM-PD converters can also be used for PWM-PFM-PD converters. As an example, the design of a five-output converter is shown in this subsection. The input voltage V in is 24 V, and the outputs are 15 V/1.5 A, 12/1.5 A, −5 V/0.8 A, 5 V/0.6 A and 3.3 V/0.45 A, respectively.
The first and second outputs are operated in CCM. Therefore, the heaviest loads, 15 V/1.5 A, 12/1-1.5 A, are selected for these outputs. The topology can be selected to be buck, boost or buck-boost depending on the input voltage. Moreover, δ 1 and δ 2 should be close to 0.5, depending on the δ 1 and δ 2 values, in order to ensure a wide δ 3 . In this chapter, the requirement is a buck converter; and so only the buck converter is analyzed.
The third and fourth outputs are operated in DCM, and a fly-buck or forward-buck type is selected according to the δ 1 and δ 2 values, because how the range of the fly-buck and forward-buck type converters changes depends on the δ 1 and δ 2 values.
Given these considerations, the 5 V and +5 V outputs are chosen for these outputs and the fly-buck topology is used because δ 1,2 ≥ 0.5. Accordingly, the turn ratios of the coupled inductors n 1 and n 2 are chosen to be 0.707.
The fifth output voltage is 3.3V. The forward-buck type in burst mode is selected to control this output by PD, as discussed before.
The design of this output is similar to that of the third and fourth output. The turns ratio of the coupled inductor's n 3 is calculated from (13), depending on the maximum and minimum load values. n 3 is selected to have the same value, 0.707, as n 1,2 .
The parameters of the five-output converter prototype are the same as for the two-output converter, and can be found in Table 7. Table 7. Components of the five-output converter prototypes.

Experimental Results with the Open-Loop Five-Output Prototype
After the design and the simulation were complete, a hardware prototype was built as shown in Figure 14, and tested in order to verify the analysis.
A two-channel waveform generator was used to generate all PWM signals. The second output of the waveform generator is a single signal, of which the duty cycle, phase delay, and number of pulses can be controlled independently, as shown in Figure 15. Tables 8 and 9 show the operating points, control parameters and efficiencies of the five-output converter for a number of different loads. The efficiency varied between 92.5% and 93.5%.

(V) v 2 (V) v 3 (V) v 4 (V) v 5 (V) i 1 (A) i 2 (A) i 3 (A) i 4 (A) i 5 (A)
Case 1 Table 9. The control parameters of a five-output converter at the operating points shown in Table 8.

Modeling
Models of dc-dc converters are required to design the controller. Therefore, many modeling researches for PWM converters, which are given either continuous or discrete-time modeling, have been made. However, the sequence of state variables to each other is important for discrete-time modeling. For instance, the demagnetizing time of i L3 , β 1 t s can be higher than the total of the phase shift time and the demagnetizing time of i L4 , β 2 t s at the five-output converter. Therefore, at least two models, with β 1 < β 2 and β 1 > β 2 , are required for this condition when using discrete-time modeling. In addition, the sequence of the state variables is independent to each other with state-space averaging. Moreover, the work in [26] shows that asymptotic stability of the averaged system model implies asymptotic stability of the actual system. Therefore, the controllers can replicate the design of these models.
In this section, two PWM signals are used in order to describe the PWM-PFM-PD control scheme. Therefore, five-output voltages can be regulated independently. First, state-space average (SSA) model is used for the multiple output converter. The large-signal models are nonlinear, and the models are linearized around a desired operating point by Taylor-expansion. After obtaining large and small models of the five-output converter, the models are compared by simulation to verify them. Depending on the small signal model, the dominant poles of the system are placed in the desired points at close-loop. Then, to decrease the steady-state error of the system, error cancellation algorithm is proposed. In the end, the experimental results of the prototype are given to verify the analyses.
All components of the converter are considered ideal. There are ten state variables, i L1 , v C1 , i L2 , v C2 , i L3 , v C3 , i L4 , v C4 , i L5 and v C5 , to model the converter. When burst mode is on (k > 1), the frequency of i L4 is different than the main frequency, f 1 . The state variables at the different switching frequencies for SSA is then explained. One of the advantages of SSA is that the state variables can be averaged independently from each other.

Averaging and Correcting
Suppose the dynamics of a state variable x l of a dc-dc converter can be described by a piecewise-linear state-space model as: where l is the number of state variables, q i is the switching function, i is the number of the switching stage (the sub-circuit), and a i are the state coefficients. Then state-space averaging (SSA) technique can be applied to a state variable that has multiple switching functions according to the following average model: ẋ l (t) = [q 1 a 1 + q 2 a 2 + . . . q i a i ] x l (t). (22) Generalizing this procedure, it was taken into account that a state variable may depend on all other state variables. For instance, state variable i L1 has two stages and each state equation is multiplied by the related switching interval in SSA. When these two stages are multiplied by the related switching interval δ 1 t s and (1 − δ 1 )t s , they become: And, after simplification: Now consider that all state variables Figure 12a are subjected to this averaging, then the differential equations that describe the multiple-output converter can be defined in vector notation as: (25) in which the state vector x and coefficient matrix A av are: where PWM converters that are operated in CCM have two switching intervals: the active switch is either on (q 1 ) or off (q 2 ). In CCM, the average of the derivatives of the inductor current is the same as the product of the averages; and SSA is equal to explicit averaging of the circuit equations. Contrary to CCM, DCM operation involves an additional interval where the inductor currents and therefore its average is zero, and the average of this third interval is zero. In addition, in DCM the average of the product terms [q 1 a 1 + q 2 a 2 + q 3 a 3 ]i L is not the same as the averaged product of the individual waveforms. The studies described in [27,28] explain this situation and offer a correction matrix. The difference between the actual average and SSA charging currents is shown, based on [27] in Table 10. The matrix M corrects mismatch of the inductor currents in DCM as follows: With this correction matrix, the modified SSA model in (25) becomes: Table 10. Charging capacitors over the entire period using an inductor operating in DCM.

SSA Equivalent Actual Equivalent Charging Current
Charging Current

Full-Order Averaged Models
It is possible to calculate what the average of the inductor currents is from the peak value of the inductor currents without requiring the demagnetizing duration ratios β 1 , β 2 and β 3 . The peak current of the inductor currents is defined as: The average of the inductor currents can then be written as: The demagnetizing duration ratios of the inductors operated in DCM can be found from the average value of the inductor currents, (36)-(38). Hence, the new demagnetizing constraints for the multiple output converter are: Substituting these magnetizing durations, (39)-(41), into (32) gives the following full-order averaged model for the converter: where and (45) The state matrix includes switching frequency information, as shown in (43)-(46). Therefore, the model is able to predict correctly even when the frequencies are different and the burst mode is active. In fact, the frequency information of i L4 is defined as t s /k in (45), and, depending on the value of k, the state variable i L4 changes correspondingly.

Linearization
The large-signal model is nonlinear since the state matrix A f in (43) changes for each operating point. The matrix can be rewritten in the following form: where the state variable and the input vectors are: The function in (49) is linearized by taking the first-order Taylor approximation around the operating point [u * , x * ], according to: where ∂F(x, u) ∂x x * ,u * = A(x * , u * ) is the Jacobian matrix of F(x, u) with respect to the x vector, and ∂F(x, u) ∂u matrix of F(x, u) with respect to the u vector.

Discretization
The obtained SSA models in (49) are continuous, and they need to be discretized to be applicable to digital control. The discrete model can be described as: where Φ = e At s (55) where I is the identity matrix, and t s is the sampling time of the discrete model. As t s is equal to the switching period of the converter, it is a variable.
The analog-to-digital converter (ADC) of the system microcontroller is triggered by this variable switching period, as depicted in Figure 16. The microcontroller captures the inputs with a sample-hold circuit, and the data is kept constant until the next sample. The microcontroller also holds the outputs after the starting point of the PWM sequence.

Digital Control of Multiple-Output Converters
In this section, the output voltage regulation of a multiple-output converter is studied. PID (proportional-integral-derivative) controllers are still very popular in many control applications thanks to their simple structure and performance. Integral action, which indicates infinite loop gain at steady-state, guarantees zero steady-state tracking error, and zero steady-state effect of constant output disturbances. In general, the excessive integral gain yields closed-loop instability. As state variables of multiple input-multiple output (MIMO) affect each other, oscillation is caused more critical than for single input-single output (SISO) systems [29]. This is the reason why regulating a multiple-output converter is complicated: there are interdependencies between the different outputs. To solve this kind of regulation problem, digital control provides many options. Sophisticated algorithms and accurate calculation can be implemented in microcontrollers or even field programmable gate arrays (FPGAs).

Pole Placement by Digital State Feedback
According to [30], the poles of a closed-loop system can be placed in any desired location by manipulating the state feedback gains. These techniques can be applied to a system of any order.
A multiple-output converter system controlled by a discrete-time control platform and having variable switching frequency is shown in Figure 16. A system which is regulated by a feedback vector -L is depicted in Figure 17a. All of the state variables u[t] are sampled by ADCs, and these variables are weighted by the state-feedback gains to result in the plant input vector u[l]. Next, these variables are transformed back to the analog domain using digital-to-analog converters (DACs). The ZOH equivalent of the plant is shown in Figure 17b, and it is described with (53). The equation for the feedback gain is: Substituting (53) into (57) gives: The vector of feedback gains L is calculated from (58), and the eigenvalues of the closed system set to their the desired values. The Matlab function "place" is used to calculate L [31].
(a) (b) Figure 17. (a) A regulation system using digital state feedback; (b) A zero-order hold (ZOH) design model for digital state feedback.

Choosing the Settling Interval
The speed of the controller is desired to be as fast as possible. The deadbeat control is one of the most popular control methods, as the steady-state error goes to zero in a finite number of switching periods [30]. This approach supplies a faster dynamic response than other control techniques.
If the poles of a continuous-time closed-loop system are moved far left in the s domain, the system response becomes faster. Using the fact that from the formula z = e st s it follows that s = −∞ maps to z = 0, the z-domain poles should be moved to the origin of the z plane in order to make the system as fast as possible. This method is called deadbeat control. According to the Cayley-Hamilton Theorem, "deadbeat" means that the eigenvalues of the (Φ[l]−LΓ[l]) matrix are made zero when: where d is the dimension of the system. Therefore, It follows from (60) that the regulator moves the poles to zero in order to settle d time steps. In theory, the settling time of the regulator therefore becomes dt s seconds. If the feedback gain is made higher than described by (60), a damped oscillation is observed at half the sampling frequency [32]. Moreover, parameter mismatches of the model, model uncertainties, and noise from the measurement signals can cause a steady-state error and reduce the settling time. One of the disadvantages of deadbeat controllers is that measurements are needed to adjust the feedback gains, using trial and error [33]. The component values of the converters, such as inductance, capacitance, and resistance, will vary, e.g., because of temperature effects and aging.
This causes variation in Φ[l] and Γ[l] and thus in the pole locations. Another drawback of the deadbeat technique is that, because the processor forces the control signal to match the state variables to the reference in dt s seconds, the control signal can saturate, and then the settling time becomes much longer than the expected dt s seconds.
As the settling time of buck converters operated at CCM (the 1st and 2nd outputs) is higher than those at DCM (the 3rd, 4th and 5th outputs), the maximum settling time can be analyzed depending on these CCM outputs.
A buck converter with an appropriate deadbeat controller was simulated in LTspice IV. The parameters of the buck converter are: inductor 150 µH, capacitor 40 µF, load 10 Ω, switching frequency 150 kHz, feedback gains 0.9 (for current) and 1.05 (for voltage). The duty cycle V δ1 settles in 2t s when the input voltage V in is changed from 23 V to 24 V. The maximum duty cycle settles at 0.9, and the duty cycle saturates, when the change of input voltage is increased substantially, such as from 19 V to 24 V. The settling time becomes 7t s instead of 2t s .
The settling time was chosen as 10t s to make the results robust against component variations and saturation effects. L was chosen depending on the settling time, and Bessel polynomials were used for the controller prototype [30].

Settling Time Detector
In Section 6.1, the steady-state error problem is mentioned. In order to detect this steady-state error, the system under control first needs to settle. Accordingly, a settling time detector is used to detect whether the system is in the steady-state, as shown in Figure 16a.
After the system reaches the steady-state, the change in the error is approximately zero. Following reference [34], an analog circuit is used to detect the settling time of a signal. To detect its change, a signal can be compared to a delayed copy of itself. The input signal and the delayed signal are therefore connected to two hysteresis comparators, as shown in Figure 18a.
The delayed error signal can be smaller or greater than the error signal during the transient. Therefore, two hysteresis comparators are used to cover both cases, as shown in Figure 18b. The threshold voltages V T1 and V T2 are selected to be close to the expected error signal V e , which is zero, as shown in Figure 18b. The comparators are designed with hysteresis to avoid oscillations at the comparator outputs [34]. Figure 18. (a) The block diagram of the detection circuit; (b) Output signals of the comparators and "and" gate as function of the delayed input signal.

Cancelation Algorithm
The system is modeled without considering the voltage drop of diodes, the losses caused by parasitic components or the uncertainties-and the nonlinear characteristics-of components. Therefore, the required control effort could be larger than the predicted one. In each period, errors are made in the control parameter calculations, and these ultimately cause a steady-state error. In order to compensate for this, an error cancelation scheme is introduced. This circuit becomes active when the controller error signal stops changing.
The required control parameters are calculated using the small-signal model. Because the calculation depends on ideal components, in practice cross-regulation issues cause offsets from the desired output values. This procedure is therefore repeated until such time that the output voltages are inside the requested tolerance band. Figure 19 shows the steady-state error cancelation algorithm for the first output voltage v 1 . As δ 1 is the control parameter of v 1 , δ 1 is decreased or increased, depending on the amount of error. The same algorithm is issued for the other output voltages.  Figure 19. Steady-state error(e) cancelation algorithm for the δ 1 control parameter.

Experimental Results with the Close-Loop Five-Output Prototype
As proof of concept, a five-output closed-loop converter was built. The schematic of the converter is depicted in Figure 12a. The same power circuit was used as in the previous chapter. A C2000 Delfino F28379D microcontroller functioned as a controller to measure the state variables and to generate all gate signals. A PWM module of the microcontroller was used for each pulse of the burst mode PWM signal. In total, five PWM modules were used and these five signals were connected to an OR gate. Measurements circuits were used between the microcontroller and the output voltages v 1 , v 2 , v 3 , v 4 and v 5 .
Experimental results for load and input voltage changes are shown in Figures 20 and 21. Initially the five-output converter is in steady-state. Each output current is changed one at a time, keeping the the other output currents constant. Finally, the input voltage is changed.
As shown in Figure 20a, at t = 0 s, the first output current i 1 is stepped down from 1.5 A to 0.75 A, and at t = 0.5 ms, i 1 is stepped up from 0.75 A to 1.5 A. The change at i 1 affects v 3 , because δ 1 is also a control parameter of v 3 . The controller adjusts f 1 from 82.4 kHz to 66.3 kHz in order to keep v 3 at the desired voltage.
Likewise, at t = 0 s, the second output current i 2 is stepped down from 1.5 A to 1 A, and at t = 0.5 ms, i 2 is stepped back up to 1.5 A, as shown in Figure 20b. The controller reduces δ 2 from 67.3% to 66.3% to keep v 2 at 12 V after the change at t = 0 s. Since δ 2 is a control parameter of v 4 , k increases from 3 to 5.
Furthermore, at t = 0 s, the third-output current i 3 is stepped down from 0.8 A to 0.5 A, and at t = 0.5 ms, i 3 is stepped back to 0.8 A, as shown in Figure 20c. As the main control parameter of v 3 is f 1 , the change of f 1 affects v 4 and v 5 . This happens because they are operated in DCM and are synchronized to f 1 . There is some hunting around of v 1 and v 2 , because of cross-regulation issues. However, the system eventually finds the steady-state operating points.
Next, at t = 0 s, the fourth output current i 4 is stepped down from 0.6 A to 0.4 A, and at t = 2.5 ms, i 4 is stepped back to 0.6 A as shown in Figure 20d. k is changed from 3 to 5 after the change at t = 0 s. This change affects other outputs, and accordingly f 1 decreases from 85.5 kHz to 69.7 kHz. This is why the settling time needed for the system to recover from this change is longer than for the previous changes.
The fifth output current i 5 is stepped down from 0.45 A to 0.33 A at t = 0 s, and i 6 is stepped back to 0.45 A as seen in Figure 21a at t = 0.5 ms. The phase delay ratio δ PD is the only control parameter of v 5 . Therefore, changes of only v 5 are observed, as shown Figure 21a, when δ PD is increased from 33.5% to 42.0%.
Lastly, the input voltage is changed from 21 V to 30 V at t = 0 s, and from 30 V to 21 V at t = 4 ms. This change affects all the outputs, so regulation is apparent at every output in Figure 21b.

Conclusions
This paper introduces methods to obtain additional outputs without increasing the number of switches and coils. After proposing new multiple output converters, modeling and a digital controller for multiple output converters are presented.
First, multiple output dc-dc converters with reduced number of active and passive components are presented. Two PWM-PFM controlled two-output topologies, fly-buck and forward-buck, are shown. These two-output converters have only one switch and one coupled inductor to regulate two outputs independently. Then, two topologies controlled by PWM-PD are shown. These three-output converters need only two switches and two coupled inductors to regulate three-outputs independently. The two-output and three-output converters were implemented, and experimental results were obtained to validate the analysis and design procedure. The procedure to obtain PD at the different frequencies is discussed, and then a PWM-PFM-PD method is shown that exploits the full control potential of the two signals. Also, this signal pattern is applied to a five-output converter which has only two switches and two coupled inductors to control five-outputs. The design criteria for this five-output converter are presented, and the analysis is verified experimentally.
Next, a discrete converter model and corresponding control method are proposed for multiple output converters. First, the SSA technique is used to describe the multiple output converter. The application of SSA modeling to a multiple output converter, wherein state variables operate at different frequencies, is also explained.
To verify the regulation, a pole-placement feedback method is applied to the small signal model of the converter after this model is discretized by variable sampling time ZOH. A tuning method is presented to reduce the steady-state error of all the independently regulated outputs.
Finally, a prototype of the close loop system is presented. The controller is implemented with a F28379D microcontroller, and the measurement results of the five-output converter show that the analyses are valid. Funding: This work is part of the research programme ASLS with project number 12759, which is partly financed by the Netherlands Organisation for Scientific Research (NWO). The authors also acknowledge the financial support of Philips Lighting (Signify, now).

Conflicts of Interest:
The authors declare no conflict of interest.