A Four-Phase High Voltage Conversion Ratio Bidirectional DC-DC Converter for Battery Applications

Abstract

This study presents a four-phase interleaved high voltage conversion ratio bidirectional DC-DC converter circuit based on coupled inductors and switched capacitors, which can eliminate the defects of conventional high voltage conversion ratio bidirectional DC-DC converters in terms of high-voltage/current stress, less efficiency and low-power limitation. Parallel channels are used to reduce current stress at the low-voltage side and series connected switched capacitors are used to enlarge voltage conversion ratio, reduce voltage stress and achieve auto current sharing. This paper proposes the operation principle, feature analysis and optimization design considerations. On this basis the objectives of high voltage conversion ratio, low voltage/current stress, high power density, high efficiency and high-power applications can be achieved. Some experimental results based on a 500 W prototype converter (24 V to 48 V at low-voltage side, 400 V at high-voltage side) are given to verify the theoretical analysis and the effectiveness of the proposed converter.

1. Introduction

Recently, the development of distributed renewable energy generation systems has become a foremost topic to save the fossil fuel consumption and protect the natural environment [1,2,3]. Energy storage elements (ESEs) are adopted to smooth and stabilize the output power and improve the dynamic response of the system. The bidirectional DC-DC converter (BDC) links the ESEs to the DC voltage bus. Unfortunately, the DC bus voltage could be as high as 800 V when the system includes three phase PWM inverters for high-power applications [3,4]. As the most developed and widely used energy storage devices [5,6], the battery energy storage system typically includes numerous low-voltage battery cells. Although a storage battery series string can provide high enough voltage, slight mismatches or temperature differences will cause a charge imbalance when the series string is charged as a unit [7]. Batteries arranged in parallel strings can enhance the power redundancy and alleviate the problems caused by storage battery series strings [8,9]. However, the output voltage still remains low (24 V–48 V) in this parallel connected configuration, thus an efficient BDC with high voltage conversion ratio (HVCR) is required [9].

Dual-active-bridge isolated bidirectional DC-DC converters (DAB-IBDCs) based on high frequency transformers are the most common topologies for conventional HVCR BDCs [10,11,12]. HVCR can be achieved by adjusting the transformer turns ratio. However, those topologies have some drawbacks such as: High voltage spike on the main switch devices, low efficiency due to the leakage-inductor, and only suitable for low-power applications. As shown in Figure 1, some isolated and bidirectional soft switching techniques are generally applied to improve conversion efficiency [13,14,15], such as LLC or CLLC resonant converter, full-bridge phase-shift converter and so on [16,17,18]. Unfortunately, those resonant topologies will increase circuit complexity, and usually need complex-structured transformers [19].

Figure 1. Bidirectional full-bridge CLLC resonant converter .

Figure 1. Bidirectional full-bridge CLLC resonant converter .

Many applications of HVCR BDCs do not require isolation [20], and non-isolated BDCs (NIBDCs) with HVCR have attracted much attention in order to simplify structure design, lower the cost and improve conversion efficiency.

To avoid the huge current spike, as shown in Figure 2, a category of SC-based resonant converters are proposed [21,22]. By adding a small series resonant inductor, the di/dt slew rate is efficiently suppressed, and high voltage ratio and zero-current switching (ZCS) can be achieved, but these topologies are only suitable for low-power applications due to the excessive input ripple current and too many components.

Figure 2. Triple-mode/trisection-mode ZCS SC QR BDC .

Figure 2. Triple-mode/trisection-mode ZCS SC QR BDC .

On the other hand, as shown in Figure 3, CI-BDCs are widely used in order to achieve HVCR with fewer components and reduce voltage stress at the same time [23,24]. Leakage inductance energy can alleviate the reverse-recovery problem of the rectifier diode. Furthermore, active clamp circuit or the passive counterpart is necessary to alleviate the turn-off voltage spike and achieve zero voltage switching (ZVS) even zero current switching (ZCS) of the switches [24,25]. In these converters, the voltage ratio can be easily extended by increasing the winding-ratio of the coupled-inductors. However, the current ripple at low voltage side (LVS) is also largely increased, which constrain their high-power applications.

Figure 3. Transformer-based bidirectional DC/DC topology.

Figure 3. Transformer-based bidirectional DC/DC topology.

To minimize the current ripple at LVS and extend power conversion ability, SC-BDCs and CI-BDCs based on interleaved structures are presented [26,27,28,29]. [19] and [26] present an multiphase quasi-resonant (QR) ZCS SC-BDC structure, and in [27], another ZCS SC-BDC topology is studied, these topologies extend the voltage conversion ratio (VCR) by adding an increased number of SCs and switches with a series connected resonant inductor to obtain voltage conversion ratios from the 2-ratio or 1/2 ratio to n-ratio or 1/n ratio, and enlarge the power conversion ability by adding interleaved cells, but there are too many switches and other power devices, system efficiency becomes low, converter structure becomes too complex and the controller will be overburdened. As shown in Figure 4, to reduce the number of the power devices, a ZVS BDC topology is proposed in [28]. However, the VCR of the ZVS BDC is still less than six, and phase-shift control goes against the topology extension.

Figure 4. Circuit diagram of the interleaved high step-up soft-switched BDC.

Figure 4. Circuit diagram of the interleaved high step-up soft-switched BDC.

Based on the above analysis, the NIBDC with HVCR and high efficiency that can be applied to high-power level has rarely been proposed. A novel 4-phase interleaved NIBDC with SCs and CIs is proposed in this work. The proposed BDC is optimized to further improve converter efficiency and power density, reduce device voltage and current stress, and increase VCR. Eight MOSFETs, two CIs, three SCs and no diode are used to achieve 4 times VCR (4/(1-D) or D/4, where D is the turn-on duty cycle of switch) compared to conventional Buck/Boost BDC. The key point about the proposed converter is how to reduce the current stress on LVS, voltage stress for all switches, and achieve high efficiency when the circuit operates under HVCR. A 4-phase parallel structure easily facilitates current stress and current ripple reduction, Moreover, auto current sharing (ACS) of parallel 4 channels can be obtained by the effect of SCs. Furthermore, CIs are used to guarantee very low current ripple when the inductance is small, thus fewer winding turns reduce the size, cost and power losses of the CIs. This paper is organized as follows: the operation principles and feature analyses are described in Section 2 and Section 3 respectively. Section 4 presents the circuit features and the design considerations, and Section 5 presents the experimental results for a 24 V–48 V LVS, 400 V high voltage side (HVS) and 500 W power output with 200 kHz switching frequency to validate the effectiveness of the proposed topology. Finally, conclusions are given in Section 6.

2. Coupling Mode Selection

Figure 5 shows the two different coupling patterns of the coupled inductor, and also their equivalent decoupling models [30]. As shown in Figure 5a, the direct coupling inductor with initial inductance L₁, L₂ can be modeled as one positive mutual inductance M at the common node, and two separate leakage inductors with inductance L₁ − M and L₂ − M, where M = kL. Correspondingly, the inverse coupling counterpart can be modeled as one negative mutual inductance -M at the common node, and two separate leakage inductors with inductance L₁+M and L₂+M as shown in Figure 5b. The voltages v_L1, v_L2 across L₁, L₂ now equal the summation of the voltage across mutual inductance and the leakage inductance.

Figure 5. Two different coupling patterns (a) Direct coupling; (b) Inverse coupling.

Figure 5. Two different coupling patterns (a) Direct coupling; (b) Inverse coupling.

In order to investigate how the CIs influence the channel inductor ripple and the dynamic processing, typical operation waveforms of two-phase interleaved continuous current mode (CCM) Boost (TPICB) are shown in Figure 6.

Figure 6. Current curves when duty cycle is larger than 0.5 (a) Inverse coupling, (b) Direct coupling.

Figure 6. Current curves when duty cycle is larger than 0.5 (a) Inverse coupling, (b) Direct coupling.

Figure 6a displays the current waveforms in inverse coupling mode, the dotted line represents the current waveforms of i_L1, i_L2 without coupling. Compared with the uncoupled counterpart, the current rising slope of i_L2 in phase b-c is slower, due to the effect of the CI. At interval T₁ and T₃, the rising slope of the coupled inductors is greater. However, in TPICB circuits, the overlap time that the corresponding switches both on is short, so the total effect of the CI is to reduce the inductor current ripple. Moreover, in transient response phase, when output power increases, the ON time of switches will be increased and T₁, T₃ last longer, which will lead to fast dynamic response. This is another advantage by choosing the inverse coupling mode. Correspondingly, the current waveforms with direct coupling condition are shown in Figure 6b. The channel inductor ripple will be enlarged. Although above conclusions are obtained when D > 0.5, the same conclusion can be obtained when D < 0.5:

$$\{\begin{array}{l}{v}_{L1}=v_{L1-M}+v_M\\ v_{L2}=v_{L2-M}+v_M\end{array}\hspace{1em}\text{and}\hspace{1em}\{\begin{array}{l}{v}_{L1}=v_{L1+M}+v_{-M}\\ v_{L2}=v_{L2+M}+v_{-M}\end{array}$$

(1)

For quantitative analysis, taking inverse coupling for example, some expressions will be given [30]. During phase T₁, MOSFETs of channel 1 and 2 are turned on, voltages across L₁, L₂ are v_L1 = v_L2 = V_L, therefore, the equivalent inductances for channel 1 and channel 2 are obtained:

$$\{\begin{array}{l}{V}_L=\left(L_1+M\right)\cdot \text{d}{i}_{L1}/\text{d}t-M\cdot \text{d}\left(i_{L1}+i_{L2}\right)/\text{d}t\\ V_L=\left(L_2+M\right)\cdot \text{d}{i}_{L2}/\text{d}t-M\cdot \text{d}\left(i_{L1}+i_{L2}\right)/\text{d}t\end{array}$$

(2)

$$L_{T-EQ1A}=L-M$$

(3)

$$L_{T-EQ2A}=L-M$$

(4)

During T₂ period, MOSFET of channel 1 is turned off, and MOSFET of channel 2 is turned on. Voltages across L₁, L₂ are v_L1 = V_L − V_H, v_L2 = V_L. Therefore, the equivalent inductance for channel 1 and channel 2 are calculated as:

$$L_{T-EQ1B}=\frac{L^2-M^2}{L-\frac{1-D}{D}M}$$

(5)

$$L_{T-EQ2B}=\frac{L^2-M^2}{L-\frac{D}{1-D}M}$$

(6)

During T₃ period, MOSFETs of channel 1 and 2 are turned on. It’s the same as in time interval T₁.

During T₄ period, MOSFET of channel 1 is turned on, and MOSFET of channel 2 is turned off. It’s symmetry of the situation during T₂:

$$L_{T-EQ1D}=\frac{L^2-M^2}{L-\frac{D}{1-D}M}$$

(7)

$$L_{T-EQ2D}=\frac{L^2-M^2}{L-\frac{1-D}{D}M}$$

(8)

Based on above analyses, to decrease the current ripple of low voltage input side, accelerate the auto current sharing process of switch capacitors, inverse coupling mode is selected in this paper.

3. Proposed Topologies and Operation Principles

3.1. Proposed Topologies

Figure 7 shows the proposed HVCR BDC circuit after inductor decoupling. There are four parallel inductors at V_L side, to reduce inductance and mitigate channel ripple current effectively, phases 1 and 2, as well as phases 3 and 4, share an inverse coupled inductor with a turn ratio of N_p:N_s = 1:1. The coupling coefficient is denoted by k (0 < k < 1). In addition, there are three SCs connected in series in the circuit, SCs named C₁, C₂ and C₃ are used in the circuit to realize HVCR, furthermore, with attendance of the SCs, the channel inductors can achieve auto current sharing (ACS) feature.

The PWM drive signal of the proposed circuit is very simple. Phases 1 and 3, as well as phases 2 and 4, share the same gate PWM signal. When the circuit works in Boost stage, energy flows from V_L to V_H; the duty cycle D_up of gate drive signals for S₁, S₂, S₃ and S₄ should be larger than 0.5 in order to eliminate circulating current during the turn-off of all ground-connected MOSFETs; and Q₁, Q₂, Q₃ and Q₄ are working in synchronous rectification (SR) mode during this time. Correspondingly, when the circuit works in Buck stage, energy flows from V_H to V_L; the duty cycle D_down of PWM for Q₁, Q₂, Q₃ and Q₄ should be less than 0.5; and S₁, S₂, S₃ and S₄ are working in SR mode during this period.

Figure 7. Schematic of the proposed four-phase HVCR BDC.

Figure 7. Schematic of the proposed four-phase HVCR BDC.

During the following theoretical analyses and calculation process, the component parameters are regarded as identical, and the following three conditions are assumed:

(1)

All switches are treated as ideal.

(2)

L₁ = L₂ = L₃ = L₄ = L and C₁ = C₂ = C₃ = C.

(3)

Capacitors C₁, C₂ and C₃ are large enough that V_C1, V_C2 and V_C3 are considered to be constant in a switching period.

(4)

The coupling coefficient k and the mutual inductance M of the CIs are equal, k = M/L, and the turn ratio of the CIs is equal to 1.

3.2. CCM Boost Stage

Figure 8 shows the major operating waveforms of the proposed HVCR BDC in CCM Boost stage. Figure 9 shows the equivalent circuits. In this mode, LVS energy flows from V_L to V_H. Switches S₁, S₂, S₃ and S₄ are operating in active switching with duty cycles of D_up and switches Q₁, Q₂, Q₃ and Q₄ are operated in SR mode, as shown in Figure 8. The operation of the CCM Boost stage can be divided into four intervals.

Figure 8. Operating waveforms for the CCM Boost stage.

Figure 8. Operating waveforms for the CCM Boost stage.

Figure 9. Equivalent circuits in CCM Boost stage (a) interval 1; (b) interval 2; (c) interval 3; (d) interval 4.

Figure 9. Equivalent circuits in CCM Boost stage (a) interval 1; (b) interval 2; (c) interval 3; (d) interval 4.

Interval 1 [t₀ ~ t₁]: Power switches S₁, S₃ are on, and S₂, S₄ turn off. Inductor L₁ are charged by V_L, and inductor current i_L1 goes up linearly. Inductor L₂ is series-connected with C₁ to charge capacitor C₂, with inductor current i_L2 going down linearly. Inductor L₃ is charged by V_L, and inductor current i_L3 goes up linearly. Inductors L₄ and C₃ are series-connected to charge capacitor C_H and the load, and inductor current i_L4 goes down linearly. The voltage equations across inductors are obtained:

$$\{\begin{array}{l}{V}_L=L_1\cdot \text{d}{i}_{L1}/\text{d}t-M\cdot \text{d}{i}_{L2}/\text{d}t\\ V_L+V_{C1}-V_{C2}=L_2\cdot \text{d}{i}_{L2}/\text{d}t-M\cdot \text{d}{i}_{L1}/\text{d}t\\ V_L=L_3\cdot \text{d}{i}_{L3}/\text{d}t-M\cdot \text{d}{i}_{L4}/dt\\ V_L+V_{C3}-V_H=L_4\cdot \text{d}{i}_{L4}/\text{d}t-M\cdot \text{d}{i}_{L3}/\text{d}t\end{array}$$

(9)

$$\{\begin{array}{l}\frac{\text{d}{i}_{\text{L1}}}{\text{d}t}=\frac{L{V}_{\text{L}}+M(V_{\text{L}}+V_{\text{C1}}-V_{\text{C2}})}{L^2-M^2}\hfill \\ \frac{\text{d}{i}_{\text{L3}}}{\text{d}t}=\frac{L{V}_{\text{L}}+M(V_{\text{L}}+V_{\text{C3}}-V_{\text{H}})}{L^2-M^2}\hfill \end{array}$$

(10)

Interval 2 [t₁ ~ t₂]: Power switches S₁, S₂, S₃ and S₄ are turned on, and the corresponding SR switches Q₁, Q₂, Q₃ and Q₄ are turned off. Inductors L₁, L₂, L₃ and L₄ are charged by V_L. Inductor currents i_L1, i_L2, i_L3 and i_L4 go up linearly. The load absorbs energy from C_H. The voltage relationship of each inductor can be written as follows:

$$\{\begin{array}{l}{V}_L=L_1\cdot \text{d}{i}_{L1}/\text{d}t-M\cdot \text{d}{i}_{L2}/\text{d}t\\ V_L=L_2\cdot \text{d}{i}_{L2}/\text{d}t-M\cdot \text{d}{i}_{L1}/\text{d}t\\ V_L=L_3\cdot \text{d}{i}_{L3}/\text{d}t-M\cdot \text{d}{i}_{L4}/\text{d}t\\ V_L=L_4\cdot \text{d}{i}_{L4}/\text{d}t-M\cdot \text{d}{i}_{L3}/\text{d}t\end{array}$$

(11)

$$\frac{\text{d}{i}_{L1}}{\text{d}t}=\frac{\text{d}{i}_{L3}}{\text{d}t}=\frac{V_L}{L-M}$$

(12)

Interval 3 [t₂ ~ t₃]: Switches S₁, S₃ and Q₂, Q₄ are turned off, switches S₂, S₄ and Q₁, Q₃ are turned on. Inductor L₁ release energy to C₁ through Q₁, with inductor current i_L1 going down linearly. Inductor L₂ is charged through V_L, S₂ path, and inductor current i_L2 goes up in a linear way. Similarly, series-connected L₃, V_L, and C₂ charge energy to C₃ through Q₃. Current i_L3 goes down in a linear way. Inductors L₄ are linearly charged by V_L. The load is charged by C_H. The voltage equations across inductors L₁, L₂, L₃ and L₄ are listed as following:

$$\{\begin{array}{l}{V}_L-V_{C1}=L_1\cdot \text{d}{i}_{L1}/\text{d}t-M\cdot \text{d}{i}_{L2}/\text{d}t\\ V_L=L_2\cdot \text{d}{i}_{L2}/\text{d}t-M\cdot \text{d}{i}_{L1}/\text{d}t\\ V_L+V_{C2}-V_{C3}=L_3\cdot \text{d}{i}_{L3}/\text{d}t-M\cdot \text{d}{i}_{L4}/\text{d}t\\ V_L=L_4\cdot \text{d}{i}_{L4}/\text{d}t-M\cdot \text{d}{i}_{L3}/\text{d}t\end{array}$$

(13)

$$\{\begin{array}{l}\frac{\text{d}{i}_{\text{L1}}}{\text{d}t}=\frac{(V_{\text{L}}-V_{\text{C1}})L+M{V}_{\text{L}}}{L^2-M^2}\hfill \\ \frac{\text{d}{i}_{\text{L3}}}{\text{d}t}=\frac{(V_{\text{L}}+V_{\text{C2}}-V_{\text{C3}})L+M{V}_{\text{L}}}{L^2-M^2}\hfill \end{array}$$

(14)

Interval 4 [t₃ ~ t₄]: As the state of mode 2, S₁, S₂, S₃ and S₄ are all turned on, and Q₁, Q₂, Q₃ and Q₄ are switched off. Inductors L₁, L₂, L₃ and L₄ are all linearly charged by V_L.

3.3. CCM Buck Stage

Figure 10 and Figure 11 show the key waveforms and equivalent circuits in the CCM Buck stage, respectively.

Figure 10. Operating waveforms for the CCM Buck stage.

Figure 10. Operating waveforms for the CCM Buck stage.

Figure 11. Equivalent circuits in CCM Buck stage (a) interval 1; (b) interval 2; (c) interval 3; (d) interval 4.

Figure 11. Equivalent circuits in CCM Buck stage (a) interval 1; (b) interval 2; (c) interval 3; (d) interval 4.

In this mode, HVS energy flows from V_H to V_L. Switches Q₁, Q₂, Q₃ and Q₄ are operating in active switching with duty cycles of D_down and switches S₁, S₂, S₃ and S₄ are conducting in SR mode, as shown in Figure 10. The operation of the CCM Buck stage can be divided into four intervals.

Interval 1 [t₀ ~ t₁]: The switches Q₂, Q₄ and S₁, S₃ are turned on, while switches Q₁, Q₃ and S₂, S₄ are turned off. The inductor L₄ and capacitor C₃ are linearly charged by V_H through Q₄, C₃, L₄ and V_L. Inductor current i_L4 goes up linearly. The series-connected L₂ and C₁ are charged by C₂, with linearly increasing inductor current i_L2. Inductors L₃, L₁ linearly discharge energy to V_L through S₃ and S₁ respectively. The voltage equations across each inductor are written as follows:

$$\{\begin{array}{l}-V_L=L_1\cdot \text{d}{i}_{\text{L1}}/\text{d}t-M\cdot \text{d}{i}_{\text{L2}}/\text{d}t\\ V_{\text{C2}}-V_{\text{L}}-V_{\text{C1}}=L_2\cdot \text{d}{i}_{\text{L2}}/\text{d}t-M\cdot \text{d}{i}_{\text{L1}}/\text{d}t\\ -V_{\text{L}}=L_3\cdot \text{d}{i}_{\text{L3}}/\text{d}t-M\cdot \text{d}{i}_{\text{L4}}/dt\\ V_{\text{H}}-V_{\text{L}}-V_{\text{C3}}=L_4\cdot \text{d}{i}_{\text{L4}}/\text{d}t-M\cdot \text{d}{i}_{\text{L3}}/\text{d}t\end{array}$$

(15)

Interval 2 [t₁ ~ t₂]: The power switches Q₁, Q₂, Q₃ and Q₄ are turned off, and S₁, S₂, S₃ and S₄ are turned on to reduce conductive losses. In this time period, the inductors L₁, L₂, L₃ and L₄ release energy to V_L through S₁, S₂, S₃ and S₄ respectively. The voltage of SCs stay the same, with no current flowing (i_C1 = i_C2 = i_C3 = 0). Therefore, the following relationships are derived:

$$\{\begin{array}{l}-V_L=L_1\cdot \text{d}{i}_{\text{L1}}/\text{d}t-M\cdot \text{d}{i}_{\text{L2}}/\text{d}t\\ -V_L=L_2\cdot \text{d}{i}_{\text{L2}}/\text{d}t-M\cdot \text{d}{i}_{\text{L1}}/\text{d}t\\ -V_{\text{L}}=L_3\cdot \text{d}{i}_{\text{L3}}/\text{d}t-M\cdot \text{d}{i}_{\text{L4}}/dt\\ -V_L=L_4\cdot \text{d}{i}_{\text{L4}}/\text{d}t-M\cdot \text{d}{i}_{\text{L3}}/\text{d}t\end{array}$$

(16)

Interval 3 [t₂ ~ t₃]: The power switches Q₁, Q₃ and S₂, S₄ are turned on, while Q₂, Q₄ and S₁, S₃ are turned off. Inductor L₁ is linearly charged by C₁ with linearly increasing current i_L1. Inductor L₂ releases energy to V_L with linearly decreasing i_L2. Similarly, inductor L₃ and capacitor C₂ are charged by C₃ through Q₃. Inductor current i_L3 goes up linearly. At the same time, inductor L₄ discharges energy to V_L through switch S₄. Inductor current i_L3 goes up linearly. The V_L is charged by the summation of inductor currents i_L1, i_L2, i_L3, i_L4. The voltage equations across each inductor are written as follows:

$$\{\begin{array}{l}{V}_{\text{C1}}-V_L=L_1\cdot \text{d}{i}_{\text{L1}}/\text{d}t-M\cdot \text{d}{i}_{\text{L2}}/\text{d}t\\ -V_{\text{L}}=L_2\cdot \text{d}{i}_{\text{L2}}/\text{d}t-M\cdot \text{d}{i}_{\text{L1}}/\text{d}t\\ V_{\text{C2}}-V_{\text{L}}-V_{\text{C1}}=L_3\cdot \text{d}{i}_{\text{L3}}/\text{d}t-M\cdot \text{d}{i}_{\text{L4}}/dt\\ -V_{\text{L}}=L_4\cdot \text{d}{i}_{\text{L4}}/\text{d}t-M\cdot \text{d}{i}_{\text{L3}}/\text{d}t\end{array}$$

(17)

Interval 4 [t₃ ~ t₄]: It’s the same as Interval 2. The power switches Q₁, Q₂, Q₃ and Q₄ are turned off, and S₁, S₂, S₃ and S₄ are turned on to reduce conductive losses. In this time period, the inductors all release energy to V_L through the corresponding current paths as shown in Figure 11d. Meanwhile, the voltage of switched-capacitors remain unchanged, i_C1 = i_C2 = i_C3 = 0.

3.4. Discontinuous Current Mode (DCM) Boost Stage

Figure 12 shows the major operating waveforms of the proposed HVCR BDC in DCM Boost stage. In this mode, relative faint energy flows from V_L to V_H. Switches S₁, S₂, S₃ and S₄ are conducting in active switching with duty cycles of D_up and switches Q₁, Q₂, Q₃ and Q₄ are operating in SR mode, as shown in Figure 12. The operation of the DCM Boost stage can be divided into six intervals.

Figure 12. Operating waveforms for the DCM Boost stage.

Figure 12. Operating waveforms for the DCM Boost stage.

Interval 1 [t₀ ~ t₁]: The same as interval 1 in CCM Boost mode: S₁, S₃ are on, and S₂, S₄ turn off. Inductor L₁ is charged by V_L, and inductor current i_L1 goes up linearly. Inductor L₂ is series-connected with C₁ to charge capacitor C₂, and inductor current i_L2 goes down linearly. Inductor L₃ is charged by V_L, and inductor current i_L3 goes up linearly. Inductor L₄ and C₃ are series-connected to charge capacitor C_H and the load, and inductor current i_L4 goes down linearly.

Interval 2 [t₁ ~ t₂]: The state of S₁ and S₃ are unchanged, but Q₂ and Q₄ are turned off. L₁, L₃ are charged by V_L, with i_L1, i_L3 increasing linearly. Unlike interval 1, the current of C₂ is zero, the output parasitic capacitors of S₂ and S₄ are resonant with channel inductors respectively. i_L2, i_L4 will increase firstly and then decrease positively, and their peak values are related with the value of output parasitic capacitances. When i_L2 and i_L4 reach zero, ZVS turn-on of S₂ and S₄ can be achieved at this time, and if S₂ and S₄ still not be turned on, i_L2 and i_L4 will begin the oscillation of positive phase.

Interval 3 [t₂ ~ t₃]: The same as interval 2 in CCM Boost mode, power switches S₁, S₂, S₃ and S₄ are turned on, and Q₁, Q₂, Q₃ and Q₄ are turned off. Inductors L₁, L₂, L₃ and L₄ are charged by V_L. Inductor currents i_L1, i_L2, i_L3 and i_L4 go up linearly. The load absorbs energy from C_H.

Interval 4 [t₃ ~ t₄]: The same as interval 3 in CCM Boost mode, switches S₁, S₃ and Q₂, Q₄ are turned off, while switches S₂, S₄ and Q₁, Q₃ are turned on. Inductor L₁ releases energy to C₁ through Q₁, and inductor current i_L1 goes down linearly. Inductor L₂ is charged through V_L, S₂ path, and inductor current i_L2 goes up in a linear way. Similarly, series-connected L₃, V_L and C₂ charge energy to C₃ through Q₃. Current i_L3 goes down in a linear way. Inductor L₄ is linearly charged by V_L. The load is charged by C_H.

Interval 5 [t₄ ~ t₅]: This interval is the continuation of interval 4. Switches S₁, S₃ and Q₂, Q₄ are turned off, switches S₂, S₄ are turned on when i_L2 and i_L4 decrease to zero. During this interval, i_L2, i_L4 increase linearly. Similar to interval 2, the current of C₁ and C₃ is zero, and the output parasitic capacitors of S₁ and S₃ are resonant with channel inductors respectively. i_L1, i_L3 will increase firstly and then decrease positively, and their peak values are related to the value of output parasitic capacitances of selected MOSFETs. When i_L1 and i_L3 reach zero, ZVS turn-on of S₁ and S₃ can be achieved at this time, and if S₁ and S₃ still not be turned on, i_L1 and i_L3 will begin the oscillation of positive phase.

Interval 6 [t₅ ~ t₆]: As the state of interval 3, S₁, S₂, S₃ and S₄ are all turned on, and Q₁, Q₂, Q₃ and Q₄ are switched off. Inductors L₁, L₂, L₃ and L₄ are all linearly charged by V_L.

Based on the above analyses, it can be seen that, channel inductor will resonant with the output parasitic capacitor of the corresponding MOSFET in DCM mode, which will lead to negative oscillation of the inductor current other than constant zero. Moreover, the negative oscillation peak is determined by the value of output parasitic capacitor for the selected MOSFET. In this paper, silicon carbide (SiC) MOSFETs are selected due to their very tiny output parasitic capacitor. Furthermore, ZVS turn-on of the relevant MOSFET can be achieved in turning on the switch during the negative oscillation of the inductor current, which will improve the circuit light-load efficiency further.

4. Feature Analysis and Design Considerations

4.1. Voltage Gain and Duty Ratio

By adopting energy conservation method for L₁, the following express can be obtained:

$$\Delta E=L_1\cdot {i_{\text{L1}}}^2(t_4)/2-L_1\cdot {i_{\text{L1}}}^2(t_0)/2=0$$

(18)

This indicates the total inductor current increment is zero in a switching period, as in Equation (19), with the time periods of each mode listed in Equation (20):

$$\{\begin{array}{l}{\displaystyle {\int }_{\text{MODE1}}\text{d}{i}_{\text{L1}}}+2{\displaystyle {\int }_{\text{MODE2}}\text{d}{i}_{\text{L1}}}+{\displaystyle {\int }_{\text{MODE3}}\text{d}{i}_{\text{L1}}}=0\hfill \\ {\displaystyle {\int }_{\text{MODE1}}\text{d}{i}_{\text{L3}}}+2{\displaystyle {\int }_{\text{MODE2}}\text{d}{i}_{\text{L3}}}+{\displaystyle {\int }_{\text{MODE3}}\text{d}{i}_{\text{L3}}}=0\hfill \end{array}$$

(19)

$$\{\begin{array}{l}{T}_{\text{MODE1}}=T_{\text{MODE3}}=(1-D_{up})T_s\hfill \\ T_{\text{MODE2}}=T_{\text{MODE4}}=(D_{up}-1/2)T_s\hfill \end{array}$$

(20)

where t_MODE1, t_MODE2, t_MODE3 and t_MODE4 are the duration time of each corresponding mode.

Substitute Equations (10), (12) and (14) in (19), following equations are therefore deduced:

$$\{\begin{array}{l}L\cdot [V_{\text{L}}-(1-D_{up})V_{\text{C1}}]+M\cdot [V_{\text{L}}+(1-D_{up})(V_{\text{C1}}-V_{\text{C2}})]=0\hfill \\ L\cdot [V_{\text{L}}+(1-D_{up})(V_{\text{C2}}-V_{\text{C3}})]+M\cdot [V_{\text{L}}+(1-D_{up})(V_{\text{C3}}-V_{\text{H}})]=0\hfill \end{array}$$

(21)

Due to the effect of voltage doubling cells based on SCs, V_H = 4V_C3/3 = 4V_C2/2 = 4V_C1/1. Then solving Equation (21), we get:

$$\{\begin{array}{l}\begin{array}{l}{V}_{\text{L}}-(1-D_{up})V_{\text{C1}}=0\\ V_{\text{L}}+(1-D_{up})(V_{\text{C1}}-V_{\text{C2}})=0\end{array}\hfill \\ \begin{array}{l}{V}_{\text{L}}+(1-D_{up})(V_{\text{C2}}-V_{\text{C3}})=0\\ V_{\text{L}}+(1-D_{up})(V_{\text{C3}}-V_{\text{H}})=0\end{array}\hfill \end{array}$$

(22)

In consequence, voltage gain for the proposed 4-phase BDC topology in CCM Boost stage can be obtained:

$$M_{\text{H}}=V_{\text{H}}/V_{\text{L}}=4/(1-D_{\text{up}})$$

(23)

Similarly, the voltage gain in CCM Buck stage is deduced as:

$$M_{\text{L}}=V_{\text{L}}/V_{\text{H}}=D_{\text{down}}/4$$

(24)

The relationship between the voltage ratio and duty ratio of the proposed 4-phase BDC is sketched in Figure 13.

Figure 13. Duty cycles versus voltage gain (a) CCM Boost operation; (b) CCM Buck operation.

Figure 13. Duty cycles versus voltage gain (a) CCM Boost operation; (b) CCM Buck operation.

(1)

The voltage ratio of the proposed BDC is extended significantly, with duty cycle D varies from 0.5 to 0.9 (D_up) or 0.1 to 0.5 (D_down), the voltage ratio can achieve 8 - 40 in CCM Boost operation, and 0.025 - 0.125 in CCM Buck operation.

(2)

Within the whole working scope, the voltage gain varies evenly when the duty cycle is changing, which is conductive to the design of the closed-loop digital controller.

4.2. Auto Current Sharing

As mentioned above, due to the effects of the series SCs between the four channels, the ACS mechanism of the proposed BDCs is different from traditional parallel circuits. In theory, for static current sharing, even with different inductor values, the proposed BDCs can achieve ACS, if the same duty cycle of each channel MOSFET is fulfilled. Based on Figure 8 and above analysis, a case study of CCM Boost stage will be given. The current expressions for SCs can be obtained as:

$$\{\begin{array}{l}{i}_{\text{C1}}=(1-S_1\cdot S_3)\cdot i_{\text{L1}}-(1-S_2\cdot S_4)\cdot i_{\text{L2}}\hfill \\ i_{\text{C2}}=(1-S_2\cdot S_4)\cdot i_{\text{L2}}-(1-S_1\cdot S_3)\cdot i_{\text{L3}}\hfill \\ i_{\text{C3}}=(1-S_1\cdot S_3)\cdot i_{\text{L3}}-(1-S_2\cdot S_4)\cdot i_{\text{L4}}\hfill \end{array}$$

(25)

where S₁, S₂, S₃ and S₄ = “0” or “1” are the switching state of the corresponding power switches. The Ampere-second balance equation can be expressed as follows:

$$\{\begin{array}{l}-I_{\text{L2}}(t_1-t_0)+I_{\text{L1}}(t_3-t_2)=0\hfill \\ I_{\text{L2}}(t_1-t_0)-I_{\text{L3}}(t_3-t_2)=0\hfill \\ -I_{\text{L4}}(t_1-t_0)+I_{\text{L3}}(t_3-t_2)=0\hfill \end{array}$$

(26)

where I_L1, I_L2, I_L3 and I_L4 represent the mean value of corresponding inductor current during time interval [t₂, t₃] or [t₀, t₁]. The time-period of t₃–t₂ equals to t₁–t₀ when S₁, S₂, S₃ and S₄ with the same duty cycle D_up, and therefore I_L2 = I_L1 is obtained. In the same way, I_L2 = I_L3, I_L3 = I_L4 are derived. Based on above analysis, ACS among each inductor can be achieved if the switches S₁, S₂, S₃ and S₄ share the same turn-on duty cycle.

Capability of ACS is a significant advantage for the proposed 4-phase BDC, which can simplify the design of CIs and the digital controller. Unfortunately, the regulation process of ACS leads to current pulsation, and even instability of the whole system. To solve this negative effect, a sufficiently small inductance value and a relatively large SC value should be selected based on the above optimization methods. A small inductance is used to shorten the ACS process, and a large SC is used to minimize the voltage fluctuation between SC and input/output capacitors. Besides, a carful designed digital control loop is used to guarantee the stability of the proposed BDC, as shown in Figure 14. With the control loop compensation, low-frequency gain is enlarged, several resonant peaks caused by SCs are weakened, and the cut off frequency of the current loop is decreased to 35.8 kHz and the system is stable with good phase margin (PM) and gain margin (GM).

Figure 14. Bode diagram with and without the loop compensation.

Figure 14. Bode diagram with and without the loop compensation.

4.3. Design Considerations

4.3.1. Optimal Design of the CIs

In this section, the following analyses are mainly aim to optimize the coupling coefficient of the CIs to minimize inductor current ripple on the premise that the inductance and inductor volume are small enough. Under uncoupled mode, assumes that the inductor ripple current of the design target is less than 1 A, and its value can be calculated by the following expressions in Boost mode:

$$L=\frac{D_{up}\cdot V_L}{\Delta i_L\cdot f_s}$$

(27)

where Δi_L = 1 A is the expected inductor current ripple, and V_C3 is the average voltage of C₃. And finally the minimum inductance under uncoupled mode L_min = 125 µH is calculated.

As mentioned above, small inductance can accelerate the ACS process, increase system stability. What’s more, smaller inductance can reduce the volume of coupled-inductors as well as increase power density. Thus, without considering the inductor current ripple, winding losses and phase cross-over frequency, smaller inductance should be adopted. However, considering smaller inductors will lead to larger ripple current and inductor losses, CIs are used to reduce the current ripple further, on the premise that with the same initial inductance L_min. Take CCM Boost stage for example, Figure 8 shows that the inductor ripple current equals to the current decrement of L₁ during time interval [t₂–t₃], which is proportional to the equivalent inductance L_EQ1 within the same period:

$$\frac{\text{d}{i}_{\text{L1}}}{\text{d}t}=\frac{L(V_{\text{L}}-V_{\text{C1}})+M{V}_{\text{L}}}{L^2-M^2}$$

(28)

where V_c1 = 4V_L/(1 − D_up), and M = kL. Then:

$$\frac{\text{d}{i}_{\text{L1}}}{\text{d}t}=\frac{V_{\text{L}}(1-\frac{1}{1-D_{\text{up}}}+k)}{(1-k^2)L}$$

(29)

$$\{\begin{array}{l}\frac{\partial }{\partial D}(\frac{\text{d}{i}_{\text{L1}}}{\text{d}t})=\frac{D_{\text{up}}-1-V_{\text{L}}}{{(1-D_{\text{up}})}^2(1-k^2)L}\hfill \\ \frac{\partial }{\partial k}(\frac{\text{d}{i}_{\text{L1}}}{\text{d}t})=\frac{V_{\text{L}}(1-k^2)L+2V_{\text{L}}(1-\frac{1}{1-D_{\text{up}}}+k)kL}{{(1-k^2)}^2{L}^2}\hfill \\ \frac{\partial }{\partial L}(\frac{\text{d}{i}_{\text{L1}}}{\text{d}t})=\frac{(1-k^2)L-V_{\text{L}}(1-\frac{1}{1-D_{\text{up}}}+k)(1-k^2)}{{(1-k^2)}^2{L}^2}\hfill \end{array}$$

(30)

Equation (30) describes the relationship between L_EQ1, D_up, k and L₁. When Equation (30) equals to zero, the relevant maximum equivalent inductance will be obtained. Thus, with the same inductance and different coupling coefficients, the ripple current can be minimized if the equivalent inductance L_EQ1 reaches a maximum:

$$k=\left(D_{up}-\sqrt{2D_{up}-1}\right)/\left(1-D_{up}\right)$$

(31)

In the same way, the optimal k value corresponding to the global maximum L_EQ2 in CCM Buck stage can be obtained:

$$k=\left(1-D_{down}-\sqrt{1-2D_{down}}\right)/\left(D_{down}\right)$$

(32)

Based on the expression Equations (30)–(32), Figure 15 can be obtained, and we can see that:

(1)

With a smaller initial channel inductance, a more tiny variation of the equivalent inductance with changing D_up/D_down will be obtained, which indicates a smaller input ripple current in the range of any load condition;

(2)

The maximum equivalent inductance is related to duty cycle D_up or D_down, for example, if rated D_up equals to 0.64 or D_down equals to 0.36, then the optimized coupling coefficient is k = 0.3. It is obviously that the optimized k value in CCM Boost operation and CCM Buck operation is equal, when rated V_L and V_H are given.

Figure 15. Equivalent inductance curves versus k and D (a) CCM Boost; (b) CCM Buck.

Figure 15. Equivalent inductance curves versus k and D (a) CCM Boost; (b) CCM Buck.

According to the above two conclusions and the L_min under uncoupled mode, finally, L = 120 µH and k = 0.3 can be selected, where k = 0.3 is the optimum solution of the coupling coefficient under rated load condition.

4.3.2. Optimal Design of SCs

According to the assumed conditions in Section 3.1, to facilitate the circuit analyses and calculations, voltage ripple across SCs has been ignored. However quantitative analysis of the ripple voltage across SCs is necessary to guarantee the feasibility of the assumed conditions. It is generally known that the voltage ripple across switched-capacitors C₁, C₂ and C₃ can be expressed as:

$$\Delta U_{\text{C}}=\frac{I_{\text{C}}(1-D_{\text{up}})}{f_{\text{S}}\cdot C}$$

(33)

where I_C is the mean value of the SCs current i_C during a switching period T_s:

$$I_{\text{C}}=\frac{P_o}{V_{\text{H}}(1-D_{\text{up}})}$$

(34)

Assume that the voltage ripple of each SC is lower than 0.5 V, according to above expression, C_min = 21 µF can be calculated. Considering the ripple voltage caused by ESR, parasitic inductance and thermal effect of capacitors in applications, 40 µF/500 V metalized-polyester film capacitors are selected. Because of its excellent characteristics like the high frequency performance, low ESR, low dielectric dissipation factor and high di/dt or du/dt capabilities. Its ESR is only about 5 m Ohm, and RMS current is about 19 A at 10 kHz, which is exactly suitable for the proposed high-frequency and large-current switching capacitor application.

4.3.3. Selection of Power MOSFETs

According to operation analysis in Section 3.2 and Section 3.3, the voltage stress of the power switches S₁ - S₄ and Q₄ is V_H/4, while for Q₁, Q₂ and Q₃, the voltage stress is V_H/2 in either CCM Boost or CCM Buck stage. Furthermore, when the circuit works in discontinuous current mode (DCM), all switches S₁ - S₄ and Q₁ - Q₄ will suffer V_H/2 voltage stress. In all of the normal states, the voltage stress of power switches only relate to the value of V_H, no matter with duty cycle, value of V_L or load variations. From Figure 8 we can see that the voltage gain in Boost/Buck stage is 4 times of the conventional Boost/Buck converter, while the voltage stress is only one half.

The maximum current through S₂, S₃ and S₄ occurs at their turn off instant, superimposed by two inductor currents, which is calculated as:

$$i_S=\frac{2P_o}{V_{\text{H}}(1-D_{\text{up}})}+\frac{V_{\text{L}}(D_{\text{up}}-0.5)}{L_{\text{EQ2D}}\cdot f_{\text{S}}}$$

(35)

where L_EQ2D represents the equivalent inductance of channel 2 in Mode 4, which can be easily obtained with the method given in Section 2. Similarly, the maximum currents through Q₁, Q₂, Q₃ and Q₄ occur at their turn on instant, given as:

$$i_Q=\frac{P_o}{V_{\text{H}}(1-D_{\text{up}})}+\frac{(V_{\text{H}}/4-V_{\text{L}})(1-D_{\text{up}})}{2L_{\text{EQ2A}}\cdot f_{\text{S}}}$$

(36)

where L_EQ2A represents the equivalent inductance of channel 2 in Mode 1. In addition, the above expression is also suitable for switch S₁, because when S₁ turns off, the current i_L1 all transfer from S₁ to Q₁. It indicates the current stress for S₁ is smaller compared to S₂, S₃ and S₄, owing to only one inductor current i_L1 flowing through.

According to Equations (35), (36) and the analysis above, the maximum current through S₁ - S₄ and Q₁ - Q₄ and the maximum voltage stress can be obtained easily. Moreover, in order to minimize the parasitic output capacitance and decrease the negative resonant current peak in DCM mode, increase the operating frequency as well as the power density and guarantee the conversion efficiency, SiC Power MOSFETs have been selected.

4.4. Losses Distribution

4.4.1. Conduction Losses on MOSFETs

For MOSFET S₁, the average current during its ON state is mean inductor current I_L1, so the conduction losses of S₁ can be calculated based on the Joule principle as follows:

$$P_{CM-S1}={I_{\text{L1}}}^2{R}_{\text{ds-on}}{D}_{up}$$

(37)

where R_ds-on is the MOSFET conduction resister, and D_up is the conduction time of S₁ in one switching period. In a similar way, the heat losses of Q₁ is obtained as:

$$P_{CM-Q1}={I_{\text{L1}}}^2{R}_{\text{ds-on}}(1-D_{up})$$

(38)

where (1 − D_up) is the conduction time of Q₁ in one switching period. Furthermore, it can obtained that: I_L1 = I_L2 = I_L3 = I_L4 = I_L/4, with precondition: D₁ = D₂ = D₃ = D₄ = D_up. Thus the above expression is also suitable for Q₂, Q₃ and Q₄.

In reference to switches S₂, S₃ and S₄, the current flowing through is larger than S₁ due to two inductor currents superimposed. For switch S₂, the heat losses result from average inductor current I_L1 and I_L2 according to analyses in Section 3.2. In Mode 2, S₂ and S₁ are ON (duration of time: (D_up − 0.5)·T_s), the current through S₂ is just i_L2 according to steady state waveforms shown in Figure 8, thus the average current in Mode 2 is calculated as:

$$I_{\text{S2-M2}}=I_{\text{L2}}+\frac{V_L-V_{C1}}{2L_{EQ2A}}(1-D_{up})T_s+\frac{V_L(D_{up}-0.5)T_s}{2L_{EQ2B}}$$

(39)

where L_EQ2A and L_EQ2B are the equivalent inductance for channel 2 in Mode 2 and Mode 4 respectively. In Mode 3, S₂ ON and S₁ OFF (Duration of time: (1 − D_up)·T_s), the current through S₂ is the sum of i_L1 and i_L2. That is:

$$I_{\text{S2-M3}}=I_{\text{L1}}+I_{\text{L2}}=\frac{I_{\text{L}}}{2}$$

(40)

In Mode 4, S₂ ON, S₁ OFF (Duration of time: (Dup − 0.5)·T_s), the current i_L1 is removed from S₂. Therefore, the average current through S₂ in Mode 4 is calculated based on waveforms in Figure 8:

$$I_{\text{S2-M4}}=I_{\text{L2}}-\frac{V_L-V_{C1}}{2L_{EQ2A}}(1-D_{up})T_s-\frac{V_L(D_{up}-0.5)T_s}{2L_{EQ2B}}$$

(41)

Combine Equations (40)–(42), and the total conduction losses of S₂ is expressed as:

$$P_{CM-S2}={I_{\text{S2-M2}}}^2{R}_{\text{ds-on}}(D_{up}-0.5)+{I_{\text{S2-M3}}}^2{R}_{\text{ds-on}}(1-D_{up})+{I_{\text{S2-M4}}}^2{R}_{\text{ds-on}}(D_{up}-0.5)$$

(42)

Due to the circuit symmetry, the conduction losses of S₃, S₄ are equal to Equation (42).

4.4.2. Switching Losses of MOSFETs

The switching losses are composed of turn-on, turn-off losses and the free-wheel diode (FWD) losses. PWD losses is ignored considering that the mechanism of SR mode. According to reference [31,32,33], the calculation expression of turn-on and turn-off losses are obtained as:

$$\{\begin{array}{l}{P}_{\text{SW-ON}}=\frac{1}{2}\Delta U_{on}\cdot i_{on}\cdot T_{sw-on}\cdot f_s\\ P_{\text{SW-OFF}}=\frac{1}{2}\Delta U_{off}\cdot i_{off}\cdot T_{sw-off}\cdot f_s\end{array}$$

(43)

where ΔU_off represents the voltage level altering value before/after turn-off transient, and for each MOSFET, ΔU_off = 100 V is always right. T_sw-off is the turn-off crossing time. ΔU_on is also about 100 V for each switch, which is obtained from Figure 8. And T_sw-on is the turn-on overlap time.

In a same switching point, the instantaneous current value of S₁, S₂, S₃ and S₄ at turn-off moment i_off-S is equal to the instantaneous current value of Q₁, Q₂, Q₃ and Q₄ at turn-on moment i_on-Q, and then:

$$i_{off-S}=i_{on-Q}=I_{L1}+\frac{(V_{C1}-V_L)(1-D_{up})}{2L_{EQ1C}{f}_s}$$

(44)

In a similar way:

$$i_{on-S}=i_{off-Q}=I_{L1}-\frac{(V_{C1}-V_L)(1-D_{up})}{2L_{EQ1C}{f}_s}$$

(45)

Based on Equations (43)–(45), the switching losses of all MOSFETs can be obtained.

4.4.3. Capacitor ESR Losses

The power losses on capacitors is proportional to ripple current and total dissipation resistor ESR. And the equation for switching capacitor C₁ is given as:

$$P_{SC1}=\Delta {i_{\text{L1}}}^2{R}_{C-ESR}\cdot (1-D_{up})$$

(46)

In reference to SCs C₁, C₂, C₃, the ripple current is just the inductor current ripple Δi_L. While for filter capacitors, the ripple current refer to input/output current ripple.

4.4.4. ESR Losses of CIs

The heat consumption on each inductor is proportional to its average current and the parasitic resistor. That is:

$$P_{L-ESR}={I_{\text{L}}}^2{R}_{L-ESR}$$

(47)

4.4.5. Magnetic Losses of CIs

The magnetic losses of coupled inductors can be calculated as [34]:

$$P_{L-CORE}=p_w\cdot W_{tFe}$$

(48)

where W_tFe is the total weight of the selected core, and p_w is the losses on unit weight, the unit is: mW/g, and the p_w can be found out from datasheet.

5. Experimental Results

The experiments are performed under voltage and current closed-loop conditions. The output/input voltage acquisition is simply achieved by voltage-splitter resistances, and the inductor current acquisition utilizes a LAH 25-NP current transducer. According to the analysis in Section 4.2, the average inductor currents are identical to each other i.e., I_L1 = I_L2 = I_L3 = I_L4, assuming that D₁ = D₂ = D₃ = D₄ = D_up. Based on this fact, channel current transducers can be reduced to just one. The experimental results of channel current comparison shown in the following figures are just the results with the effect of ACS fulfilled by SCs, there is no other additional current-sharing controller. This would dramatically reduce circuit complexity, cost and controller design.

As illustrated in Figure 16, a 500 W prototype converter is built in the laboratory. It can be seen that each of the CIs is constituted with two separated leakage inductors and a strong coupling (k = 0.95) transformer, which is used to reduce the difficulty of CIs construction (k = 0.3). Moreover, with limited selectable types, S₁ to S₄ as well as Q₁ to Q₄ are the same type of SiC MOSFET: C2M0080120D. In addition, isolated driver circuit based on pulse transformer is used as the driver circuit of those MOSFETs. S₁ and Q₁ (the same as S₂ and Q₂, or S₃ and Q₃, or S₄ and Q₄) share a drive circuit, and complementary symmetrical PWM driving signals will be supplied to S₁ and Q₁ (the same as S₂ and Q₂, or S₃ and Q₃, or S₄ and Q₄) respectively. In this way only four identical drive circuits are needed, which can effectively reduce the complexity of the driving circuits.

Figure 16. Picture of the laboratory setup.

Figure 16. Picture of the laboratory setup.

Based on above analyses and optimization methods, the optimized parameters are shown in Table 1.

Table 1. Specifications of the prototype circuit.

Parameters and components	Values (units)
Rated power Pn	500 W
Low side input DC voltage VL	24–48 V
High side input DC voltage VH	400 V
Operating frequency (fS)	200 kHz
Power MOSFETs	C2M0080120D
Switched capacitors (C1, C2, C3)	40 μF
Input/Output Capacitors (CL, CH)	80 μF
ESR (C1, C2, C3, CL, CH)	5 m Ohm
Inductance of channel 1 (L1)	122 μH
Inductance of channel 2 (L2)	128 μH
Inductance of channel 3 (L3)	124 μH
Inductance of channel 4 (L4)	126 μH
Coupling coefficient (k)	0.3
Weight of magnetic core	25.2 g
Core loss per unit weight	20 mW/g
Length of magnetic path	8.95 cm
Number of turns	48
ESR (L1, L2, L3, L4)	30 m Ohm

Table 1. Specifications of the prototype circuit.

Parameters and components	Values (units)
Rated power Pn	500 W
Low side input DC voltage VL	24–48 V
High side input DC voltage VH	400 V
Operating frequency (fS)	200 kHz
Power MOSFETs	C2M0080120D
Switched capacitors (C1, C2, C3)	40 μF
Input/Output Capacitors (CL, CH)	80 μF
ESR (C1, C2, C3, CL, CH)	5 m Ohm
Inductance of channel 1 (L1)	122 μH
Inductance of channel 2 (L2)	128 μH
Inductance of channel 3 (L3)	124 μH
Inductance of channel 4 (L4)	126 μH
Coupling coefficient (k)	0.3
Weight of magnetic core	25.2 g
Core loss per unit weight	20 mW/g
Length of magnetic path	8.95 cm
Number of turns	48
ESR (L1, L2, L3, L4)	30 m Ohm

Figure 17a,c,d show the input and output voltages, channel 1 inductor current, and drain-source voltage of Q₁ in CCM Boost mode under different input voltages (24 V to 48 V). It can be seen that inductor current ripples are less than 1 A in the entire input voltage range, and voltage stress across Q₁ is about 200 V. When V_L side voltage varies from 24 V to 48 V, output voltage V_H fluctuates between 395 V and 405 V. As shown in Figure 17c, when V_L = 23.2 V, each channel average inductor current is about 5.5 A, and peak value is about 6 A. Figure 17b shows channel 1 and channel 2 inductor current waveforms, drain-source and gate-source voltages of S₁ in rated CCM Boost mode. Combine this figure with the inductances given in Table 1, it can be seen that when inductance deviation among L₁, L₂, L₃ and L₄ are less than ±5%, the coefficient of ACS executed by SCs will be greater than 0.95 (Just the effect of ACS fulfilled by SCs, without extra current-sharing control). Furthermore, voltage stress across S₁ is about 100 V.

Figure 17. Experimental waveforms under CCM Boost mode (a) and (b) 36 V to 400 V; (c) 24 V to 400 V; (d) 48 V to 400 V.

Figure 17. Experimental waveforms under CCM Boost mode (a) and (b) 36 V to 400 V; (c) 24 V to 400 V; (d) 48 V to 400 V.

Figure 18 displays the experimental results obtained in CCM Buck stage under 400 V (or 300 V) input and 36 V output. Figure 18a gives the input and output voltages, channel 1 inductor current, and drain-source voltage of Q₁. It can be seen that inductor current ripples remain less than 1 A when the output voltage V_L = 36 V. Voltage stress across Q₁ is still approximately 200 V. Figure 18b shows the channel 1 and channel 2 inductor currents, input and output voltages, it can be seen that the coefficient of ACS is still larger than 0.95.

Figure 18. Experimental waveforms under CCM Buck stage (a) 400 V to 36 V (b) 300 V to 36 V.

Figure 18. Experimental waveforms under CCM Buck stage (a) 400 V to 36 V (b) 300 V to 36 V.

Figure 19 shows the experimental waveforms of the input and output voltages, channel 1 inductor current, and drain-source voltage of Q₁ under light-load conditions. Figure 19a is the waveforms of Boost mode with 15.7 W output power, and Figure 19b shows the waveforms of Buck mode with 13 W output power. Therefore, the proposed BDC can achieve quasi-critical inductor currents even under tiny load conditions. Moreover, as shown in Figure 19, ZVS turn-on for each switch is achieved under light-load conditions, which is beneficial to the light-load efficiency optimization.

Figure 19. Experimental results in light-load condition (a) 36 V input and 400 V/10 k Ohm output; (b) 400 V input and 36 V/100 Ohm output.

Figure 19. Experimental results in light-load condition (a) 36 V input and 400 V/10 k Ohm output; (b) 400 V input and 36 V/100 Ohm output.

Figure 20 gives the dynamic response of the proposed BDC against load variation. Figure 20a shows the input and output voltages, channel 1 and channel 2 current waveforms with 34.6 V input and 394 V output. During this time period, load resistance is changed between 10 k Ohm and 320 Ohm. It can be seen that output voltage variation is less than 15 V. Figure 20b shows the input and output voltages, channel 1 and channel 2 current waveforms when input is 300 V and output 36.5 V. At this time, load resistance is changed between 100 Ohm and 2.5 Ohm. It can be seen that output voltage variation is less than 10 V. Therefore, fast and stabilized dynamic responses are achieved.

Figure 20. Dynamic response of the proposed BDC against load variation (a) load resistance variation between 10 k Ohm and 320 Ohm; (b) load resistance variation between 100 Ohm and 2.5 Ohm.

Figure 20. Dynamic response of the proposed BDC against load variation (a) load resistance variation between 10 k Ohm and 320 Ohm; (b) load resistance variation between 100 Ohm and 2.5 Ohm.

The measured efficiency of the proposed BDC is depicted in Figure 21a, and the test result is based on YOKOGAWA WT3000 data, with a basic power accuracy of ±0.02% of reading, DC and 0.1 Hz–1 MHz measurement bandwidths. When the output power is 500 W, the efficiency under CCM Boost stage and CCM Buck stage are about 96.1% and 94.8% respectively. Benefit from the margin of the selected devices and heat sink, during the experiment, the maximum output power of the proposed converter has been raised to 1 kW, the efficiency under 1 kW Boost stage and 1 kW Buck stage are about 95.8% and 94.5% respectively. Moreover, due to the achievement of the ZVS and SR features under light-load conditions, the fluctuation of the system efficiency curve is relatively small.

In order to clarify the actual efficiency further, the dissipated power has been calculated and shown in Figure 21b, based on equations in Section 4.4 and parameters in Table 1. From Figure 21b we can see that the total power losses is 19 W, accounting for 3.8% in rated condition. This matches the measured efficiency (96.1% at 500 W Boost stage) well. Also, the heat losses induced by parasitic ESR of inductors is about 1.4 W with magnetic counterpart 2.9 W. The capacitor ESR caused extremely low energy losses. However, the power dissipated in MOSFETs is relatively high, with switching losses and conduction losses 7.4 W and 7 W, respectively.

Figure 21. (a) Measured efficiency. (b) Calculated losses breakdown.

Figure 21. (a) Measured efficiency. (b) Calculated losses breakdown.

6. Conclusions

This paper proposed a 4-phase interleaved HVCR BDC topology with SCs and CIs, which can prominently reduce the current/voltage stress of the power devices, and only needs a simple PWM control method. With an optimized design of the coupled inductors and switched capacitors, it can further reduce the inductance and inductor volume, lower the channel ripple current, and improve the dynamic performance of ACS. A 500 W prototype converter is built in the laboratory for experimental verification of the proposed topology. The maximum voltage stress of each MOSFET is about VH/2. Under different working conditions, inductor current ripples remain less than 1 A and the coefficient of ACS is greater than 0.95. The prototype converter efficiency achieves 96.1% in CCM Boost stage and 94.8% in CCM Buck stage at rated load.

Furthermore, the proposed circuit can be extended into n-mode/1/n-mode (n is a positive even number: 2, 4 … n) HVCR BDC shown in Figure 22. Higher VCR and lower current/voltage stress characteristics can be obtained by extending structure, and the relationship between V_H and V_L can be derived by:

M_nH = V_H/V_L = n/(1 − D_up)

(49)

M_nL = V_L/V_H = D_down/n

(50)

Figure 22. Extensible circuits based on the proposed topology.

Figure 22. Extensible circuits based on the proposed topology.