A Family of 5-Level Boost-Active Neutral-Point-Clamped (5L-BANPC) Inverters with Full DC-Link Voltage Utilization Designed Using Half-Bridges

: Conventional 5-level active neutral-point-clamped (5L-ANPC) topology and state-of-the-art 5-level hybrid active neutral-point-clamped (5L-HANPC) topology are popular for inverter applications. However, their dc-link voltage utilization is limited to only 50%. With the maximum voltage level generated by only half dc-link voltage, these inverters are not capable of boosting voltage in their ac output. To resolve these drawbacks, this paper proposes a family of four novel 5-level boost-active neutral-point-clamped (5L-BANPC) inverters. Without requiring any flying capacitors, the proposed topologies can generate five voltage levels by effectively using the dc-link capacitors. The dc-link voltage utilization of the proposed 5L-BANPC inverters is twice that of the 5L-ANPC and 5L-HANPC topologies. While generating the five-level ac output voltage, natural voltage balancing of both dc-link capacitors and voltage boosting are achieved. Ease of implementation is another noteworthy merit of the proposed 5L-BANPC inverters because they can be implemented using six widely available commercial half-bridge modules without requiring a dedicated circuit design. The operation of the proposed topologies is analyzed. Experimental results are presented for verification.


Introduction
In 1979, Nabae, Takahashi, and Akagi invented the first neutral-point-clamped (NPC) inverter [1,2].By using two clamping diodes, the inverter leg is clamped to the midpoint of the dc-link to extend the number of voltage levels from two to three.This 3-level NPC (3L-NPC) inverter has revolutionized dc-ac power conversion technology and sparked significant research in the design of modern multilevel inverter topologies [3].Many multilevel inverters have been commercialized for renewable energy-related, grid-connected, and industrial applications [4,5].Despite the maturity of the conventional topologies, multilevel inverters are still a hot research topic in both academia and industry for the purpose of further improvements.
To reduce conduction losses, the clamping diodes of the 3L-NPC inverter can be replaced by power switches such as MOSFETs that have a lower on-state voltage drop.As the clamping switches can be actively controlled, this improved topology has been termed an active NPC (ANPC) inverter [6].Another major advantage of the 3L-ANPC inverter is its ease of implementation through the use of three commercial half-bridge modules with built-in deadtime protection.By adding more dc-link capacitors and cascading more half-bridges, the number of voltage levels can be extended.Figure 1a shows a 5L-ANPC inverter that consists of ten half-bridges and four dc-link capacitors [7].As the number of dc-link capacitors for generating five voltage levels is double that of the three-level counterpart, balancing the voltage of dc-link capacitors is a major challenge [8].Hybrid topologies that integrate a flying capacitor into ANPC inverters have also been explored.The first 5-level hybrid ANPC (5L-HANPC) inverter introduced in [9] is very attractive in terms of switch count.As shown in Figure 1, the 5L-HANPC inverter saves 12 switches compared to the conventional 5L-ANPC inverter.A further reduction in switch count is attempted in [10,11] by introducing two diodes into the circuit structure.
Despite a significant reduction in switch count, the implementation of the 5L-HANPC inverter is more complicated, or difficult, compared to the 5L-ANPC inverter.It requires a dedicated power circuit design because there are two switches that cannot be implemented using the widely available commercial half-bridge modules, as shown in Figure 1b.Although the two switches on the top or bottom of the flying capacitor are connected in series, they are not operating in a complementary mode and do not fulfil the operation of a half-bridge module that has a built-in deadtime protection.
Similarly to the conventional 5L-ANPC inverter, the 5L-HANPC inverter also requires a controller for balancing the voltage of dc-link capacitors [12].In [13], an additional voltage-balancing circuit, that consists of power switches, inductors, and capacitors, is presented for balancing the dc-link capacitors' voltage.The 5L-HANPC inverter that uses only two dc-link capacitors instead of the four used in the conventional 5L-ANPC topology has an advantage of deploying the balancing circuit more effectively.For example, a front-end dual-boost converter as depicted in Figure 1b can be used to concurrently balance and boost the voltage across dc-link capacitors.Therefore, the voltage gain of the inverter can be boosted to accommodate a low dc source voltage for applications such as PV and battery energy storage systems.However, the flying capacitor of the 5L-HANPC inverter still requires a voltage-balancing controller.
Recently, the concept of a switched-capacitor (SC) circuit has been deployed for naturally balancing the voltage of all capacitors while achieving voltage boosting.SC-based ANPC topologies that can generate five voltage levels are presented in [14][15][16].The integration of more SCs for extending the number of voltage levels is also attempted in [17][18][19].However, they have several drawbacks inherited from the SC circuit.The natural voltage balancing of SCs is achieved by directly charging them in parallel with the dc-link capacitors that cause current spikes [20].Although voltage boosting is possible, the voltage across each SC is fixed and cannot be dynamically controlled for controlling the voltage gain.
In this paper, four novel topologies that combine the best features of the 5L-ANPC and 5L-HANPC inverters, with significant improvements in the dc-link voltage utilization Hybrid topologies that integrate a flying capacitor into ANPC inverters have also been explored.The first 5-level hybrid ANPC (5L-HANPC) inverter introduced in [9] is very attractive in terms of switch count.As shown in Figure 1, the 5L-HANPC inverter saves 12 switches compared to the conventional 5L-ANPC inverter.A further reduction in switch count is attempted in [10,11] by introducing two diodes into the circuit structure.
Despite a significant reduction in switch count, the implementation of the 5L-HANPC inverter is more complicated, or difficult, compared to the 5L-ANPC inverter.It requires a dedicated power circuit design because there are two switches that cannot be implemented using the widely available commercial half-bridge modules, as shown in Figure 1b.Although the two switches on the top or bottom of the flying capacitor are connected in series, they are not operating in a complementary mode and do not fulfil the operation of a half-bridge module that has a built-in deadtime protection.
Similarly to the conventional 5L-ANPC inverter, the 5L-HANPC inverter also requires a controller for balancing the voltage of dc-link capacitors [12].In [13], an additional voltage-balancing circuit, that consists of power switches, inductors, and capacitors, is presented for balancing the dc-link capacitors' voltage.The 5L-HANPC inverter that uses only two dc-link capacitors instead of the four used in the conventional 5L-ANPC topology has an advantage of deploying the balancing circuit more effectively.For example, a frontend dual-boost converter as depicted in Figure 1b can be used to concurrently balance and boost the voltage across dc-link capacitors.Therefore, the voltage gain of the inverter can be boosted to accommodate a low dc source voltage for applications such as PV and battery energy storage systems.However, the flying capacitor of the 5L-HANPC inverter still requires a voltage-balancing controller.
Recently, the concept of a switched-capacitor (SC) circuit has been deployed for naturally balancing the voltage of all capacitors while achieving voltage boosting.SC-based ANPC topologies that can generate five voltage levels are presented in [14][15][16].The integration of more SCs for extending the number of voltage levels is also attempted in [17][18][19].However, they have several drawbacks inherited from the SC circuit.The natural voltage balancing of SCs is achieved by directly charging them in parallel with the dc-link capacitors that cause current spikes [20].Although voltage boosting is possible, the voltage across each SC is fixed and cannot be dynamically controlled for controlling the voltage gain.
In this paper, four novel topologies that combine the best features of the 5L-ANPC and 5L-HANPC inverters, with significant improvements in the dc-link voltage utilization and voltage gain, are proposed.The contributions of the proposed 5L-BANPC inverters are as follows: (1) Only two dc-link capacitors are sufficient for generating five voltage levels without requiring any flying capacitors.(2) The voltage across dc-link capacitors is naturally balanced without requiring any controllers or sensors.(3) Full dc-link voltage utilization with the maximum voltage level is generated by the entire dc-link voltage 2V C which is double that of the existing 5L-ANPC and 5L-HANPC topologies.(4) The proposed topologies achieved dynamic voltage boosting using only 12 switches.
They can be easily implemented using six commercial half-bridge cells/modules without requiring a dedicated power circuit design.(5) All benefits are achieved without using the concept of an SC circuit; therefore, they resolve the issues associated with the existing SC-based ANPC inverters, such as current spikes.
The rest of this paper is organized as follows.The operating principle, analysis, and pulse-width modulation (PWM) scheme of the proposed 5L-BANPC inverters are discussed in Section 2. Section 3 presents the experimental results.Concluding remarks are summarized in Section 4.

Operating Principle
Figure 2 shows the proposed 5L-BANPC inverters.Each topology consists of two boost inductors, two dc-link capacitors, and six half-bridges.The dc-link capacitors are effectively utilized for generating five ac voltage levels.The middle voltage level in the positive half cycle and the negative half cycle is generated by the top capacitor C 1 and the bottom capacitor C 2 , respectively.The maximum voltage level V max is generated by discharging both capacitors in series and is equal to the entire dc-link voltage.Therefore, the dc-link voltage utilization of the proposed topologies is double that of the conventional 5L-ANPC and 5L-HANPC inverters depicted in Figure 1.
Energies 2024, 17, x FOR PEER REVIEW 3 of 15 and voltage gain, are proposed.The contributions of the proposed 5L-BANPC inverters are as follows: (1) Only two dc-link capacitors are sufficient for generating five voltage levels without requiring any flying capacitors.(2) The voltage across dc-link capacitors is naturally balanced without requiring any controllers or sensors.(3) Full dc-link voltage utilization with the maximum voltage level is generated by the entire dc-link voltage 2VC which is double that of the existing 5L-ANPC and 5L-HANPC topologies.(4) The proposed topologies achieved dynamic voltage boosting using only 12 switches.
They can be easily implemented using six commercial half-bridge cells/modules without requiring a dedicated power circuit design.(5) All benefits are achieved without using the concept of an SC circuit; therefore, they resolve the issues associated with the existing SC-based ANPC inverters, such as current spikes.
The rest of this paper is organized as follows.The operating principle, analysis, and pulse-width modulation (PWM) scheme of the proposed 5L-BANPC inverters are discussed in Section 2. Section 3 presents the experimental results.Concluding remarks are summarized in Section 4.

Operating Principle
Figure 2 shows the proposed 5L-BANPC inverters.Each topology consists of two boost inductors, two dc-link capacitors, and six half-bridges.The dc-link capacitors are effectively utilized for generating five ac voltage levels.The middle voltage level in the positive half cycle and the negative half cycle is generated by the top capacitor C1 and the bottom capacitor C2, respectively.The maximum voltage level Vmax is generated by discharging both capacitors in series and is equal to the entire dc-link voltage.Therefore, the dc-link voltage utilization of the proposed topologies is double that of the conventional 5L-ANPC and 5L-HANPC inverters depicted in Figure 1.    1 summarize the switching states of the proposed 5L-BANPC inverters.The dc-link capacitors C 1 and C 2 can be charged by the inductors L 1 and L 2 , respectively, at the 0, +1, and −1 levels.Therefore, the voltage of both dc-link capacitors is naturally balanced.In addition, the voltage of dc-link capacitors can be boosted from the dc source by controlling the charging duty cycle of the inductors L 1 and L 2 .As shown in Figures 4 and 5, L 1 and L 2 are charged by the dc source with a constant duty cycle: where V cons,ref and Vtri denote the constant reference and the peak-to-peak amplitude of each triangular carrier, respectively.By considering the volt-second balance of each inductor in steady state, the voltage across each dc-link capacitor is Energies 2024, 17, x FOR PEER REVIEW 5 of 15   Here, 1 = on and 0 = off.
The generation of five-level ac voltage is controlled by a level-shifted PWM.Considering a sinusoidal reference v sine,ref with 0 • phase shift, the fundamental component of ac voltage can be written as Energies 2024, 17, 2798 5 of 14 where Vo,1 denotes the amplitude that can be controlled by the modulation index M: and Vsin e is the amplitude of the sinusoidal reference.To simplify the PWM controller, minimum constant reference can be considered, i.e., V cons,ref = Vsin e .By substituting ( 5) into (1), the minimum duty cycle can be written as a function of the modulation index:         The voltage gain of the proposed 5L-BANPC inverters can be written as a function of M by substituting ( 6) into (4), and considering the ratio between the fundamental ac voltage amplitude and the input voltage: As shown in (7), the proposed 5L-BANPC inverters provide voltage boosting where their voltage gain can be dynamically controlled by controlling the modulation index.Figure 6 shows the improvement of voltage gain achieved by the proposed topologies, as compared to the 5L-ANPC and 5L-HANPC inverters.Here, 1 = on and 0 = off.

Ripple Analysis
To analyze the capacitor voltage ripple and inductor current ripple, key waveforms that assume the worst-case scenario depicted in Figure 5 are considered.They consist of low-frequency and high-frequency components due to ac load and PWM, respectively.Fourier analysis is used to obtain the dc component ' where o f and ,1 ˆo I denote the ac output frequency and the output current amplitude, respectively.
In steady state, the dc component of the capacitor current is zero.Therefore, the dc components of '

Ripple Analysis
To analyze the capacitor voltage ripple and inductor current ripple, key waveforms that assume the worst-case scenario depicted in Figure 5 where f o and Îo,1 denote the ac output frequency and the output current amplitude, respectively.In steady state, the dc component of the capacitor current is zero.Therefore, the dc components of i where f s denotes the frequency of the triangular carriers.
Assuming the dc source voltage is purely dc without ripples, the amplitude of lowfrequency voltage VL,LF across the inductor L can be written as a function of the capacitor voltage ripple ∆V C,LF : The low-frequency current ripple ∆I L,LF of the inductor L is Energies 2024, 17, 2798 7 of 14 derive the high-frequency current ripple ∆I L,HF , the charging state of the inductor L depicted in Figure 4 is considered:

Current Stress Analysis
In the proposed 5L-BANPC inverters, the current stress of the power switches in the first two half-bridges, i.e., S1 − S1 and S2 − S2, is given by each boost inductor's current.Although the boost inductors' currents also flow through other power switches, their directions are opposite and cancel each other out.To demonstrate this, state [0|D] of 5L-BANPC-I, as shown in Figure 7, is taken as an example.Inductors' currents i L1 and i L2 flow through S3 and S4 in the opposite direction.As i L1 = i L2 , the resultant current in these switches is zero.Therefore, the current stress of the power switches in S3 − S3, S4 − S4, S5 − S5, and S6 − S6 half-bridges is given by the ac output or the current load.
( ) The low-frequency current ripple To the high-frequency current ripple

Voltage Stress Analysis
Table 2 summarizes the power switch voltage stress of the proposed 5L-BANPC inverters.The total standing voltage (TSV) when considering the sum of voltage stress across every power switch is 16VC.The required dc-link capacitor voltage VC as a function of the voltage gain G is analyzed.For comparison, the 5L-HANPC inverter with a frontend dual-boost converter is also considered.As shown in Figure 8a, the proposed topologies achieve the same boosting gain with significantly lower VC.This is a significant advantage due to the full dc-link voltage utilization in the proposed 5L-BANPC inverters.Therefore, voltage stress reduction is achieved by the proposed inverters, with a more apparent improvement observed at a higher voltage gain, as depicted in Figure 8b.

Voltage Stress Analysis
Table 2 summarizes the power switch voltage stress of the proposed 5L-BANPC inverters.The total standing voltage (TSV) when considering the sum of voltage stress across every power switch is 16V C .The required dc-link capacitor voltage V C as a function of the voltage gain G is analyzed.For comparison, the 5L-HANPC inverter with a front-end dual-boost converter is also considered.As shown in Figure 8a, the proposed topologies achieve the same boosting gain with significantly lower V C .This is a significant advantage due to the full dc-link voltage utilization in the proposed 5L-BANPC inverters.Therefore, voltage stress reduction is achieved by the proposed inverters, with a more apparent improvement observed at a higher voltage gain, as depicted in Figure 8b.

Comparison with the Latest 5-Level ANPC Topologies
Table 3 summarizes the comparison of the proposed 5L-BANPC inverters wit state-of-the-art 5-level ANPC topologies.The 5L-HANPC inverter depicted in Figu is also considered as the benchmark.
The topology presented in [15] inserts an SC cell into the conventional three-NPC inverter to extend the number of voltage levels to five while achieving natural age balancing and reducing the switch count compared to the conventional 5-level A inverter.In addition to these advantages, refs.[16,21] use the SC concept to furthe hance the utilization of dc-link voltage.Their maximum voltage level is equal to th dc-link voltage, which is double that of the conventional 5-level ANPC inverter and shown in [15].By combining the concept of SC and the flying capacitor, the same u voltage gain is achieved by [22] while simplifying the inverter design using half-brid Although the charging of SCs by switching them to parallel balances the capac voltage naturally, it causes current spikes which can damage power devices and i duces an EMI issue.In addition, the voltage gain of the aforementioned topologies is ited to the buck range.To achieve voltage boosting, a front-end boost convert

Comparison with the Latest 5-Level ANPC Topologies
Table 3 summarizes the comparison of the proposed 5L-BANPC inverters with the state-of-the-art 5-level ANPC topologies.The 5L-HANPC inverter depicted in Figure 1b is also considered as the benchmark.
Table 3.Comparison between the proposed 5L-BANPC inverters and the latest 5-level ANPC topologies.The topology presented in [15] inserts an SC cell into the conventional three-level NPC inverter to extend the number of voltage levels to five while achieving natural voltage balancing and reducing the switch count compared to the conventional 5-level ANPC inverter.In addition to these advantages, refs.[16,21] use the SC concept to further enhance the utilization of dc-link voltage.Their maximum voltage level is equal to the full dc-link voltage, which is double that of the conventional 5-level ANPC inverter and that shown in [15].By combining the concept of SC and the flying capacitor, the same unity voltage gain is achieved by [22] while simplifying the inverter design using half-bridges.

Topology
Although the charging of SCs by switching them to parallel balances the capacitors' voltage naturally, it causes current spikes which can damage power devices and introduces an EMI issue.In addition, the voltage gain of the aforementioned topologies is limited to the buck range.To achieve voltage boosting, a front-end boost converter is required.To this end, the 5L-HANPC inverter depicted in Figure 1b is an attractive solution, considering its dynamic voltage-boosting capability without the current spikes issue.While retaining the advantages of the 5L-HANPC inverter (Figure 1b), the proposed family of 5L-BANPC inverters is an alternative that further extends the voltage gain from 0.5M/(1 − D) to M/(1 − D).The proposed topologies can generate five voltage levels without the need for the flying capacitor required in the 5L-HANPC inverter.Both dc-link capacitors in the Energies 2024, 17, 2798 9 of 14 proposed 5L-BANPC inverters are self-balanced, thus eliminating the voltage-balancing controller and sensors of the 5L-HANPC topology.By generating the maximum voltage level using capacitors, the proposed also enhance dc-link voltage utilization, which results in a reduction in voltage stress, as presented in 8.
The proposed 5L-BANPC inverters stand out due to their notable feature of employing a straightforward design utilizing six half-bridges, setting them apart from the 5L-HANPC topology.The half-bridge is a widely used block in industrial applications, making it highly advantageous for inverter design.Not only is it a pivotal circuit in reference designs, but also serves as an evaluation board actively developed by power semiconductor manufacturers to validate their power switches.As a result, the proposed topologies require minimal design effort, they can readily leverage the latest half-bridges, including those utilizing wide bandgap semiconductors.

Results
A 300 W experimental prototype, depicted in Figure 9, was tested for verification.Considering that all the proposed topologies operate with the same concept, implementing the first topology (5L-BANPC-I) is sufficient.The parameters of the experimental setup are summarized in Table 4.The part numbers of components and equipment are summarized in Table 5.
semiconductor manufacturers to validate their next-generation power switches.As a result, the proposed topologies require minimal design effort, as they can readily leverage the latest half-bridges, including those utilizing wide bandgap semiconductors.

Results
A 300 W experimental prototype, depicted in Figure 9, was tested for verification.Considering that all the proposed topologies operate with the same concept, implementing the first topology (5L-BANPC-I) is sufficient.The parameters of the experimental setup are summarized in Table 4.The part numbers of components and equipment are summarized in Table 5.To generate a boosting gain of 4.5, M and D are set to 0.9 and 0.8, respectively.The measured waveforms for steady-state response are summarized in 10.The curinductors L 1 and L 2 is continuous.In switching cycle, they are charged by 0.5V dc = 25 V for 80 µs and discharge for the remaining period to boost the voltage across dc-link capacitors.Consequently, the voltage across the dc-link capacitors C 1 and C 2 experiences a significant reaching 125 V each.The maximum voltage level in the ac output is generated by the sum of the voltage across both capacitors, which is 250 V. Five symmetric voltage levels are observed between 250 V and −250 V.The fundamental component of the output voltage obtained from Fast Fourier Transform (FFT) analysis is approximately 155 V (RMS).Therefore, the peak output voltage at fundamental frequency can be calculated as Vo,1 = √ 2 × 155 = 219 V, which is slightly less than the theoretical value of 225 V.The measured current of capacitors C 1 and C 2 shows that the proposed inverters are free from the current spike issue suffered by the existing SC topologies.To generate a boosting gain of 4.5, M and D are set to 0.9 and 0.8, respectively.The measured waveforms for steady-state response are summarized in Figure 10.The current of inductors L1 and L2 is continuous.In each switching cycle, they are charged by 0.5Vdc = 25 V for 80 µs and discharge for the remaining period to boost the voltage across dc-link capacitors.Consequently, the voltage across the dc-link capacitors C1 and C2 experiences a significant boost, reaching 125 V each.The maximum voltage level in the ac output is generated by the sum of the voltage across both capacitors, which is 250 V. Five symmetric voltage levels are observed between 250 V and −250 V.The fundamental component of the output voltage obtained from Fast Fourier Transform (FFT) analysis is approximately 155 V (RMS).Therefore, the peak output voltage at fundamental frequency can be calculated   The transient response of the experimental prototype was also measured, as shown in Figure 11.The output current changes instantaneously during the step changes in load without deteriorating the quality of output voltage.Additionally, it is worth noting that the voltage across both capacitors unaffected during these dynamic load changes.
Experiments were repeated for a lower voltage gain of 2 by decreasing M and D to 0.8 and 0.6, respectively.The measured waveforms summarized in Figure 12, have a similar profile to those presented in Figures 10 and 11, with a reduction in their magnitudes.The voltage across capacitors (C 1 and C 2 ) is recorded at 62.5 V while the maximum voltage level in the output voltage is 125 All results are good agreement the theoretical analysis.Experiments were repeated for a lower voltage gain of 2 by decreasing M and D to 0.8 and 0.6, respectively.The measured waveforms summarized in Figure 12, have a similar profile to those presented in Figures 10 and 11, with a reduction in their magnitudes.The voltage across capacitors (C1 and C2) is recorded at 62.5 V while the maximum voltage level in the output voltage is 125 V.All results are in good agreement with the theoretical analysis.To measure efficiency, power analysis is applied using oscilloscope measurements, as shown in Figure 10.Based on the first principle, the average power P can be computed as where v(t) and i(t) are the instantaneous voltage and current, respectively.The input power Pin when considering a constant dc source voltage Vdc is where is the average dc source current.For a purely resistive R load, the output power Pout of the multilevel inverter can be written by substituting the instantaneous output current io(t) and instantaneous output voltage vo(t) = io(t)R into (13), which gives where without deteriorating the quality of output voltage.Additionally, it is worth noting that the voltage across both capacitors remains unaffected during these dynamic load changes.Experiments were repeated for a lower voltage gain of 2 by decreasing M and D to 0.8 and 0.6, respectively.The measured waveforms summarized in Figure 12, have a similar profile to those presented in Figures 10 and 11, with a reduction in their magnitudes.The voltage across capacitors (C1 and C2) is recorded at 62.5 V while the maximum voltage level in the output voltage is 125 V.All results are in good agreement with the theoretical analysis.To measure efficiency, power analysis is applied using oscilloscope measurements, as shown in Figure 10.Based on the first principle, the average power P can be computed as where v(t) and i(t) are the instantaneous voltage and current, respectively.The input power Pin when considering a constant dc source voltage Vdc is where is the average dc source current.For a purely resistive R load, the output power Pout of the multilevel inverter can be written by substituting the instantaneous output current io(t) and instantaneous output voltage vo(t) = io(t)R into (13), which gives where  To measure efficiency, power analysis is applied using oscilloscope measurements, as shown in Figure 10.Based on the first principle, the average power P can be computed as where v(t) and i(t) are the instantaneous voltage and current, respectively.The input power P in when considering a constant dc source voltage V dc is where I dc = 1 T t+T t i(t)dt is the average dc source current.For a purely resistive R load, the output power P out of the multilevel inverter can be written by substituting the instantaneous output current i o (t) and instantaneous output voltage v o (t) = i o (t)R into (13), which gives where is the RMS value of the output current and V o,rms is the RMS value of the output voltage.The average output power can be simplified by substituting R into (15), resulting in Therefore, the efficiency evaluation of the experimental prototype can be conducted through measurements of key parameters, including the RMS value of output voltage V o,rms , the RMS value of output current I o,rms , the input voltage V dc , and the average input current I dc .Based on these measurements, the efficiency of the prototype is calculated to be approximately 97.68% when operating at a power level of 285 W. Since this efficiency is measured using an oscilloscope rather than a power analyzer, the measurement accuracy is influenced by the tolerances of the oscilloscope, voltage probes, and current probes.The exact efficiency be up to lower.For further efficiency the experimental prototype was also modeled in simulation to investigate the efficiency and power-loss distribution, as shown Figure 13a,b, respectively.To verify the operation of the proposed topology under a non-linear load, a full-wave diode rectifier was considered in the simulation.As shown in Figure 14, the voltage of both capacitors C 1 and C 2 is naturally balanced at 125 V.The output voltage waveform exhibits five levels, similar to the case with a linear load.(16) Therefore, the efficiency evaluation of the experimental prototype can be conducted through measurements of key parameters, including the RMS value of output voltage Vo,rms, the RMS value of output current Io,rms, the input voltage Vdc, and the average input current Idc.Based on these measurements, the efficiency of the prototype is calculated to be approximately 97.68% when operating at a power level of 285 W. Since this efficiency is measured using an oscilloscope rather than a power analyzer, the measurement accuracy is influenced by the tolerances of the oscilloscope, voltage probes, and current probes.The exact efficiency could be up to 5% lower.For further efficiency studies, the experimental prototype was also modeled in simulation to investigate the efficiency and powerloss distribution, as shown in Figure 13a,b, respectively.To verify the operation of the proposed topology under a non-linear load, a full-wave diode rectifier was considered in the simulation.As shown in Figure 14, the voltage of both capacitors C1 and C2 is naturally balanced at 125 V.The output voltage waveform exhibits five levels, similar to the case with a linear load.

Conclusions
A novel family of four 5L-BANPC inverters is introduced in this paper.The operating principle of these inverters has been thoroughly analyzed and through experimental results.The proposed 5L-BANPC inverters are capable of five-level boosted voltage using only two self-balanced dc-link capacitors.From a design perspective, these inverters exhibit simplicity, making them easily implementable using existing half-bridge modules without the need for a dedicated power circuit design.Compared to the existing 5L-ANPC topologies, the proposed 5L-BANPC inverters offer an attractive alternative that facilitates single-stage voltage boosting with significantly enhanced voltage gain.
Funding: This research received no external funding.

Figure 3
Figure3and Table1summarize the switching states of the proposed 5L-BANPC inverters.The dc-link capacitors C 1 and C 2 can be charged by the inductors L 1 and L 2 , respectively, at the 0, +1, and −1 levels.Therefore, the voltage of both dc-link capacitors is naturally balanced.In addition, the voltage of dc-link capacitors can be boosted from the dc source by controlling the charging duty cycle of the inductors L 1 and L 2 .As shown in Figures4 and 5, L 1 and L 2 are charged by the dc source with a constant duty cycle:
low-frequency voltage ripple , C LF V Δ of the capacitor C can be derived by finding the peak-to-peak voltage due to ,

=
. The high-frequency voltage ripple , C HF V Δ of the capacitor C can be derived by finding the area of , C HF i during DTs:
are considered.They consist of low-frequency and high-frequency components due to ac load and PWM, respectively.Fourier analysis is used to obtain the dc component I ′ o and the fundamental component i C,LF of the i ′ o .The low-frequency voltage ripple ∆V C,LF of the capacitor C can be derived by finding the peak-to-peak voltage due to i C,LF :

′
L and i ′ o are equal, i.e., I ′ L = I ′ o .The high-frequency voltage ripple ∆V C,HF of the capacitor C can be derived by finding the area of i C,HF during DT s :

3 .
Current Stress AnalysisIn the proposed 5L-BANPC inverters, the current stress of the power switches in the first two half-bridges, i.e., S1 S1 − and S2 S2 − , is given by each boost inductor's current.Although the boost inductors' currents also flow through other power switches, their directions are opposite and cancel each other out.To demonstrate this, state [0|D] of 5L-BANPC-I, as shown in Figure7, is taken as an example.Inductors' currents 1 through S3 and S4 in the opposite direction.As 1 current in these switches is zero.Therefore, the current stress of the power switches in S3 S3− , is given by the ac output or the current load.

Figure 8 .
Figure 8. Voltage stress analysis of the proposed 5L-BANPC inverters: (a) normalized dc-lin pacitors' voltage as a function of voltage gain; (b) normalized total standing voltage (TSV) as a tion of voltage gain.

Figure 8 .
Figure 8. Voltage stress analysis of the proposed 5L-BANPC inverters: (a) normalized dc-link capacitors' voltage as a function of voltage gain; (b) normalized total standing voltage (TSV) as a function of voltage gain.
All power switches of the inverter can be implemented using half-bridge modules without a dedicated power circuit design.(b) Number of switches.(c) Number of diodes.(d) Number of capacitors.(e) Number of inductors.(f) Full dc-link voltage utilization with the maximum voltage level equal to the entire dc-link voltage.(g) Voltage gain.(h) Achieves dynamic voltage boosting by controlling a boosting duty cycle D.
All power switches of the inverter can be implemented using half-bridge modules without a dedicated power circuit design.(b) Number of switches.(c) Number of diodes.(d) Number of capacitors.(e) Number of inductors.(f) Full dc-link voltage utilization with the maximum voltage level equal to the entire dc-link voltage.(g) Voltage gain.(h) Achieves dynamic voltage boosting by controlling a boosting duty cycle D.
slightly less than the theoretical value of 225 V.The measured current of capacitors C1 and C2 shows that the proposed inverters are free from the current spike issue suffered by the existing SC topologies.

Figure 10 .
Figure 10.Steady-state response at G = 4.5.The transient response of the experimental prototype was also measured, as shown in Figure11.The output current changes instantaneously during the step changes in load

Energies 2024 ,
17, x FOR PEER REVIEW 11 of 15deteriorating the quality of output voltage.Additionally, it is worth noting that the voltage across both capacitors remains unaffected during these dynamic load changes.


Figure Transient response at G = 4.5.
of the output voltage.The average output power can be simplified by substituting R into(15), resulting in

Table 1 .
Summary of switching states.

Table 1 .
Summary of switching states.

Table 3 .
Comparison between the proposed 5L-BANPC inverters and the latest 5-level ANPC topologies.

Table 4 .
Parameters of the experimental setup.

Table 5 .
Components and equipment of the experimental setup.

Table 4 .
Parameters of the experimental setup.