Analysis and Verification of a Wide Input Voltage PWM Converter with Variable Windings

Abstract

A three-leg pulse-width modulation converter with auxiliary windings is provided and investigated to realize wide voltage operation and zero voltage switching characteristics on power switches. The presented converter has three converter legs on the input-side and two sets of winding turns on the output-side. Owing to the on/off states of the three converter legs and the two sets of secondary winding turns, the proposed converter can be operated under three different equivalent circuits to have wide input voltage operation from 30V ~ 240V (V_in,max = 8V_in,min). Compared with the multi-stage converters to realize wide input voltage operation, the proposed circuit topology has fewer circuit components and a simple control algorithm. Conventional duty cycle control with phase-shift between each converter leg is adopted to regulate load voltage and also accomplish zero voltage switching on active switches. The presented three-leg converter is tested with a laboratory circuit. Finally, experiments testify to the performance and validity of the presented converter.

1. Introduction

Renewable energy sources are widely developed and investigated to lessen fossil fuel demand and reduce air pollution. From many renewable power sources, solar or wind power is more attractive due to the cost effectiveness. Power electronics play a more and more important role to convert the unstable input voltage from solar panels and wind generators to a stable direct-current (DC) or alternative-current (AC) voltage. Power electronics have been developed for low power (such as personal computer power units, battery chargers, consumer electronics, and solid-state lighting systems) and medium power applications (such as server power units, DC micro grid power conversion, and renewable energy power conversion). Due to the wide deviation of wind speed or solar intensity, the output voltage of wind generators or photovoltaic panels is not constant. The maximum output voltage versus minimum output voltage of the solar panels may be greater than 4:1. Conventional DC converters with wide voltage operation [1,2,3,4,5,6,7] for wind and solar power conversion are based on the circuit topologies of series-parallel connection or multi-stage conversion. However, the multi-stage circuit structure will result in low circuit efficiency and reliability. The wide voltage DC converters were studied in [8,9,10,11,12] to have soft switching operation and high efficiency. However, the complicated control scheme is the main drawback for these circuit topologies. The series and parallel resonant converters have been developed for lighting and industry applications [13,14]. The switching frequency of the resonant converters are dependent on the load conditions. The power switches turn on under zero voltage. Therefore, the switching losses are improved under high frequency operation. Compared with series or parallel resonant converters, the LLC (inductor-inductor-capacitor) resonant converters [15,16,17,18] are more attractive in consumer and industry applications such as server power and power units in personal computers and plug-in hybrid electric vehicles. Unfortunately, the narrow voltage range and wide switching frequency range are the main drawbacks of the LLC converters. For photovoltaic and fuel cell power applications, the solar panel or fuel cell output is a variable voltage that is related to the solar intensity. The low power units of railway systems, the input voltage of DC converters for motor drive controllers, lighting systems, electric door systems, and braking systems may be variated from 24 V to 110 V. For hybrid electric vehicle or electric vehicle systems, the output voltage of battery chargers is varied between 200 V and 450 V. Therefore, the wide voltage DC converters [19,20,21] have been developed as the interface circuits to convert the solar power to electric power. In [21], the PWM converter was presented with two transformers and one alternating current switch to achieve 4:1 (V_in,max = 4V_in,min) input voltage operation capability. Four operating circuits can be controlled [21] to realize wide voltage operation. However, the control algorithm in [21] was not easy to implement with the commercial analog integrated circuit. For remote control demand in stand-alone solar power systems, the wide voltage DC converter is needed to supply the necessary power for the control system, and the input voltage range of power units for controller demand is normally more than 4:1 (V_in,max ≥ 4V_in,min). Therefore, the circuit topologies in [19,20,21] cannot achieve this wide voltage demand.

This paper proposes a three-leg DC converter with auxiliary winding turns to accomplish low switching loss and wide voltage operation (30 V ~ 240 V). According to the different winding turns, there are three sub-circuits in the present converter to obtain three different voltage gains. Thus, the wide voltage operation is achieved in the presented pulse width modulation (PWM) converter. Three converter legs are used on the high voltage side to achieve 4:1 voltage range operation, and two secondary winding sets are used on the low voltage side to realize the other 2:1 voltage range operation. Two voltage comparators are employed in the control circuit to select the different primary and secondary turns and voltage gains. The reference voltages of the two voltage comparators are designed at 60 V and 120 V. Therefore, the presented converter can achieve 8:1 (30 V ~ 240V) wide voltage operation. Compared with the former wide voltage DC converter, the presented converter has a wider voltage range operation and is easier to implement with an analog or digital control circuit. The description of the presented circuit is discussed in Section 2. Three operation ranges of the presented circuit are provided in Section 3. The circuit characteristics and design procedures of the studied converter are demonstrated in Section 4. Experimental verifications are demonstrated in Section 5. Finally, the conclusions are discussed in Section 6.

2. Description of the Presented Converter

The proposed circuit topology is provided in Figure 1. As can be noted, three converter legs and one AC switch (two MOSFETs (metal–oxide–semiconductor field-effect transistor) connected by a back-to-back structure) are used on the input-side, and two sets of secondary winding turns and two AC switches are used on the output-side. The magnetic transformer with two primary turns n_p and two different secondary turns n_s1 and n_s2 is used in the proposed circuit topology. Switch S₁ is on or off to select the full-bridge circuit with the larger primary turns 2n_p (S₁ on, Q₃ and Q₄ off) or less primary turns n_p (S₁, Q₅, and Q₆ off) on the input-side. Two AC switches S₂ and S₃ are on/off on the output-side to select the secondary turns n_s1 or n_s1+n_s2 connected to the output inductor. According to the on/off states of S₁~S₃ and Q₁~Q₆, the presented three-leg PWM converter has three different equivalent circuits (Figure 2) under three voltage ranges: low voltage range (V_in,min–2V_in,min), medium voltage range (2V_in,min–4V_in,min), and high voltage range (4V_in,min–8V_in,min). For low voltage operation, the equivalent circuit is given in Figure 2a. It can be seen that switches S₁, S₂, Q₅, and Q₆ are off and S₃ is on. Since the phase-shift PWM scheme is adopted to generate the PWM signals of Q₁ ~ Q₄, the equivalent full-bridge converter (Q₁~Q₄, L_r1, T, D₃, D₄, L_o, and C_o) with transformer turns-ratio N_L = n_p/(n_s1 + n_s2) is operated to achieve high voltage gain G_L = V_o/V_in.L = 2d_eff/N_L, where V_in.L denotes V_in in the low input voltage range and d_eff is the effective duty cycle of the full-bridge converter. Figure 2b gives the equivalent circuit of the proposed converter under the medium input voltage range V_in.M = 2V_in,min–4V_in,min. Q₃, Q₄, and S₂ are in the off-state, and S₁ and S₃ are in the on-state. The equivalent circuit with components Q₁, Q₂, Q₅, Q₆, L_r1, L_r2, D₃, D₄, L_o, C_o, and T with turns-ratio N_M = 2n_p/(n_s1+n_s2) is adopted for the medium voltage range to achieve the low voltage gain G_M = V_o/V_in.M = 2d_eff/N_M. Figure 2c provides the equivalent circuit for high voltage range operation (V_in,H = 4V_in,min–8V_in,min). The switches Q₃, Q₄, and S₃ are in the off-state, and S₁ and S₂ are in the on-state. The equivalent circuit shown in Figure 2c has voltage gain G_H = V_o/V_in.H = 2d_eff/N_H, where N_H = 2n_p/n_s1. According to the above discussion, the proposed converter can be operated at three different input voltage ranges by proper selection of the on/off states of Q₁–Q₆ and S₁–S₃ to achieve wide voltage operation from V_in,min to 8V_in,min.

3. The Principle of Operation

3.1. Low Voltage Operation (S₃ on; Q₅, Q₆, S₁, S₂ off)

When V_in,min ≤ V_in < 2V_in,min, the active switches Q₅, Q₆, S₁, and S₂ are off and S₃ is on. The proposed converter has n_p primary winding turns and n_s1 + n_s2 secondary winding turns in Figure 2a. In the presented circuit, it is assumed that L_m1 and L_m2 ≫ L_r1 and L_r2, C_Q1 = … = C_Q6 = C_oss, and n_s1 = n_s2. Figure 3a demonstrates the main voltage and current waveforms under low voltage operation. The voltage gain of the presented converter for low voltage operation is G_L = 2d_eff/N_L = 4n_s1d_eff/n_p. There are ten operation modes in every one switching period. Figure 3b–k gives these ten equivalent operating circuits. Since the PWM waveforms are symmetrical between Modes 1–5 and Modes 6–10, only the circuit operations of Modes 1–5 are examined in the following discussion.

Mode 1 [t₀, t₁]: Mode 1 begins at t = t₀ when Q₁ and Q₄ (Q₂ and Q₃) are active (inactive) on the input-side and D₃ conducts on the output-side. The input current flows through the components Q₁, T, L_r1, and Q₄, and the output current flows through the components T, D₃, L_o, and C_o. The magnetizing voltage v_Lm1 ≈ V_in (due to L_m1 ≫ L_r1) and v_Lo ≈ V_in/N_L − V_o. Thus, i_Lr1 and i_Lo are calculated as:

$$i_{Lr1}\left(t\right)=i_{Lr1}\left(t_0\right)+\left(V_{in}-N_L{V}_o\right)\left(t-t_0\right)/\left(N_L^2{L}_o\right)$$

(1)

$$i_{Lo}\left(t\right)=i_{Lo}\left(t_0\right)+(V_{in}/N_L-V_o)\left(t-t_0\right)/L_o$$

(2)

Therefore, i_Lr1 and i_Lo increase in Mode 1, and v_CQ2 = v_CQ3 = V_in and v_D4 = 2V_in/N_L.

Mode 2 [t₁, t₂]: Mode 2 begins at t₁ when Q₁ turns off. The primary current i_Lr1 at time t₁ is positive. Therefore, the output capacitors C_Q1 and C_Q2 of switches Q₁ and Q₂ charge from 0 V and discharged from V_in, respectively. If the inductor energy $\left(L_{r1}+N_L^2{L}_o\right)i_{Lr1}^2\left(t_1\right)$ is greater than the capacitor energy 2$C_{oss}{V}_{in}^2$, then the capacitor C_Q2 is discharged to zero voltage at t = t₂. The time interval of this mode is given in Equation (3).

$$\Delta t_{12}=2C_{oss}{V}_{in}/i_{Lr1}\left(t_1\right)\approx 2N_L{C}_{oss}{V}_{in}/i_{Lo}\left(t_1\right)$$

(3)

The dead time t_d between the PWM signals of Q₁ and Q₂ must be greater than Δt₁₂ to accomplish the soft switching turn-on of Q₂.

Mode 3 [t₂, t₃]: The inductor current i_Lr1 > 0, and v_CQ2 = 0 at t₂. The body diode D_Q2 of switch Q₂ is conducting, and Q₂ can be turned on after time t₂ to achieve soft switching turn-on. The primary current i_Lr1 is flowing the components Q₂, T, L_r1, and Q₄, and v_Lm1 = 0. The secondary-side diodes D₃ and D₄ are both conducting, v_Lo = −V_o, and i_Lo decreases in this mode. The inductor currents are given as:

$$i_{Lr1}\left(t\right)\approx i_{Lr1}\left(t_2\right)-\left(V_{Q2,drop}+V_{Q4,drop}\right)\left(t-t_2\right)/L_{r1}$$

(4)

$$i_{Lo}\left(t\right)=i_{Lo}\left(t_2\right)-(V_o)\left(t-t_2\right)/L_o$$

(5)

where V_Q2,drop and V_Q4,drop are the voltage drop on switches Q₂ and Q₄, respectively. The diode currents i_D3 (i_D4) decrease (increase), and the slopes of the diode currents are calculated as:

$$d{i}_{D4}\left(t\right)/dt=-d{i}_{D3}\left(t\right)/dt=N_L\left(V_{Q2,drop}+V_{Q4,drop}\right)/2L_{r1}$$

(6)

Mode 4 [t₃, t₄]: Mode 4 starts at time t₃ when the lagging switch Q₄ turns off. The primary current i_Lr1 at time t₃ is positive. Therefore, the output capacitor C_Q3 (C_Q4) of switch Q₃ (Q₄) is discharged (charged) from V_in (0V). Due to D₃ and D₄ conducting in Mode 4, it can obtain v_Lm1 = 0. If the inductor energy $L_{r1}{i}_{Lr1}^2\left(t_3\right)$ is greater than the energy 2$C_{oss}{V}_{in}^2$, then it can obtain v_CQ3(t₄) = 0. The time interval of this mode is given in Equation (7).

$$\Delta t_{34}=2C_{oss}{V}_{in}/i_{Lr1}\left(t_3\right)$$

(7)

The dead time t_d between the PWM signals of Q₃ and Q₄ must be greater than Δt₃₄ to accomplish soft switching turn-on of Q₃.

Mode 5 [t₄, t₅]: At t = t₄, i_Lr1 > 0, and v_CQ3 = 0. The body diode D_Q3 of the lagging-leg switch Q₃ is forward biased. After time t₄, Q₃ turns on under zero voltage. The D₃ and D₄ are still conducting in this mode. The leg voltage v_ab = −V_in and the inductor voltage v_Lr1 ≈ −V_in, so that i_Lr1 decreases. In Mode 5, i_D3 (i_D4) decreases (increases). The slopes of i_D3 and i_D4 are expressed as:

$$d{i}_{D4}\left(t\right)/dt=-d{i}_{D3}\left(t\right)/dt\approx N_L{V}_{in}/2L_{r1}$$

(8)

The diode current i_D3 is decreased to zero at time t₅, and the time duration of Mode 5 is calculated as:

$$\Delta t_{45}=2L_{r1}{I}_o/\left(N_L{V}_{in}\right)$$

(9)

The duty cycle loss in this mode is obtained as:

$$d_{loss,5}=\Delta t_{45}/T_{sw}=2L_{r1}{I}_o/\left(N_L{V}_{in}{T}_{sw}\right)$$

(10)

where T_sw is the switching period of PWM waveforms. After the time t₅, the converter operation goes to the next half switching period.

3.2. Medium Voltage Operation (S₁, S₃ on; Q₃, Q₄, S₂ off)

When V_in is in the medium voltage range (2V_in,min ≤ V_in < 4V_in,min), S₁ and S₃ are in the on-state and Q₃, Q₄, and S₂ are in the off-state (Figure 2b). The proposed converter has 2n_p primary winding turns and n_s1 + n_s2 secondary winding turns in Figure 2b. The voltage gain for medium voltage operation is G_M = 2d_eff/N_M = 2n_s1d_eff/n_p. Comparing the voltage gains G_L and G_M, it can be noted that G_L = 2G_M. Figure 4a demonstrates the main voltage and current waveforms under medium voltage operation. There are ten operation modes in every one switching period. Figure 4b–k gives these ten equivalent operating circuits. Since the PWM waveforms are symmetrical for each half switching cycle, only the circuit operations of Modes 1–5 are discussed in the following.

Mode 1 [t₀, t₁]: Q₁, Q₆, and D₃ conduct at time t₀. The input current flows through Q₁, T, L_r1, L_r2, and Q₆, and the output current flows through T, D₃, L_o, and C_o. The magnetizing voltage v_Lm1 + v_Lm2 ≈ V_in due to L_m1 + L_m2 ≫ L_r1 + L_r2. Since v_Lo ≈ V_in/N_M − V_o > 0, i_Lr1 and i_Lo both increase linearly, and i_Lr1(t) = i_Lr2(t) ≈ i_Lo(t)/N_M. The drain-to-source voltages of Q₂ and Q₅ are equal to V_in, and the diode voltage v_D4 = 2V_in/N_M.

Mode 2 [t₁, t₂]: At time t = t₁, the leading-leg switch Q₁ is turned off. i_Lr1 is positive, and C_Q2 is discharged from V_in. If the inductor energy $\left(L_{r1}+L_{r2}+N_M^2{L}_o\right)i_{Lr1}^2$ at time t₁ is greater than the capacitor energy 2$C_{oss}{V}_{in}^2$, then C_Q2 can be discharged to zero voltage at time t₂.

Mode 3 [t₂, t₃]: Since v_CQ2(t₂) = 0 and i_Lr1(t₂) > 0, the body diode D_Q2 conducts, and the leading-leg switch Q₂ can be turned on under zero voltage. The leg voltage v_ac = 0 and the primary-side and secondary-side voltages of transformer T are zero voltage. Thus, D₃ and D₄ both conduct. Therefore, v_Lo equals −V_o, and i_Lo is decreasing.

Mode 4 [t₃, t₄]: Since Q₆ is turned off at time t₃ and i_Lr1(t₃) > 0, C_Q5 is discharged. The magnetizing voltages v_Lm1 = v_Lm2 = 0. If the inductor energy $\left(L_{r1}+L_{r2}\right)i_{Lr1}^2\left(t_3\right)$ > $2C_{oss}{V}_{in}^2$, then v_CQ5 will reach zero voltage at time t₄.

Mode 5 [t₄, t₅]: Since v_CQ5(t₄) = 0 and i_Lr1(t₄) > 0, the body diode D_Q5 conducts, and Q₅ can turn on at t₄ under zero voltage. In this mode, v_ac = −V_in and v_Lm1 = v_Lm2 = 0 due to D₃ and D₄ conducting. v_Lr1 + v_Lr2 = −V_in, and i_Lr1 decreases. At time t₅, i_D3 is decreased to zero. Then, the converter operation goes to the next half switching period.

3.3. High Voltage Operation (S₁, S₂ on; Q₃, Q₄, S₃ off)

When 4V_in,min < V_in < 8V_in,min, S₁ and S₂ are turned on and Q₃, Q₄ and S₃ are turned off (Figure 2c). This equivalent circuit has 2n_p primary turns and n_s1 secondary turns, and the voltage gain G_H = 2d_eff/N_H = n_s1d_eff/n_p. Comparing the voltage gains G_L, G_M, and G_H, it can be noted that G_L > G_M > G_H. Figure 5a demonstrates the main voltage and current waveforms under high voltage operation. Figure 5b–k gives these ten equivalent operating circuits. Since the PWM waveforms are symmetrical for each half switching cycle, only the circuit operations of Modes 1–5 are discussed in the following.

Mode 1 [t₀, t₁]: At t = t₁, D₁, Q₁ and Q₆ conduct. i_Lr1 flows through Q₁, T, L_r1, L_r2, and Q₆ on the primary-side of transformer T. i_Lo flows through D₁, L_o, and C_o on the secondary-side of T. Since v_Lo ≈ V_in/N_H − V_o > 0, i_Lr1 and i_Lo both increase linearly in this mode. The drain-to-source voltages v_CQ2 = v_CQ5 = V_in, and the diode voltage v_D2 = 2V_in/N_H.

Mode 2 [t₁, t₂]: Q₁ turns off at time t₁. Due to i_Lr1 being positive, i_Lr1 discharges C_Q2 from V_in. If the inductor energy $\left(L_{r1}+L_{r2}+N_H^2{L}_o\right)i_{Lr1}^2$ at t₁ is greater than the capacitor energy 2$C_{oss}{V}_{in}^2$, then v_CQ2 will be decreased to zero voltage at t₂.

Mode 3 [t₂, t₃]: Since v_CQ2(t₂) = 0 and i_Lr1(t₂) > 0, the body diode D_Q2 is forward biased. Thus, the leading-leg switch Q₂ turns on at time t₂ under zero voltage. In this mode, v_ac = 0, and the primary winding and secondary winding voltages equal zero voltage. The diodes D₁ and D₂ both conduct so that v_Lo equals −V_o and i_Lo is decreased.

Mode 4 [t₃, t₄]: At time t₃, the lagging-leg switch Q₆ turns off. i_Lr1(t₃) discharges C_Q5 from V_in. Since D₃ and D₄ still conduct, it can obtain v_Lm1 = v_Lm2 = 0. If the energy $\left(L_{r1}+L_{r2}\right)i_{Lr1}^2\left(t_3\right)$ > $2C_{oss}{V}_{in}^2$, then V_CQ5 = 0 at the end of this mode.

Mode 5 [t₄, t₅]: At time t₄, v_CQ5 = 0. i_Lr1(t₄) > 0, and the body diode D_Q5 conducts. The lagging-leg switch Q₅ can be turned on at time t₄ under zero voltage. Since v_ac = −V_in and v_Lm1 = v_Lm2 = 0, i_Lr1 is decreased. At t₅, i_D1 = 0. Then, the converter operation goes to the next half switching period.

4. Converter Characteristics and Design Considerations

According to the different turns-ratio of the transformer, the presented converter has three equivalent circuits. Three back-to-back MOSFETs are used in the presented circuit to have wide input voltage operation. Based on the flux balance on the output inductor, the load voltage is calculated in Equation (11).

$$V_o=\{\begin{array}{l}2d_{eff}{V}_{in}\left(n_{s1}+n_{s2}\right)/n_p=4d_{eff}{V}_{in}{n}_{s1}/n_p, V_{in,min}<V_{in}<2V_{in,min}\\ d_{eff}{V}_{in}\left(n_{s1}+n_{s2}\right)/n_p=2d_{eff}{V}_{in}{n}_{s1}/n_p, 2V_{in,min}<V_{in}<4V_{in,min} \\ d_{eff}{V}_{in}{n}_{s1}/n_p, 4V_{in,min}<V_{in}<8V_{in,min}\end{array}$$

(11)

The average diode currents I_D1 = … = I_D4 = I_o/2. The voltage ratings of D₁ ~ D₄ are V_D1,rating = V_D2,rating = (V_in,maxn_s1)/n_p and V_D3,rating = V_D4,rating = V_in,max(n_s1 + n_s2)/n_p. The voltage ratings of Q₁ ~ Q₆ and S₁ ~ S₃ are V_Q1,rating = … = V_Q6,rating = V_in,max, V_S1,rating = V_in,maxn_s2/(2n_p), and V_S2,rating = V_S3,rating = V_in,maxn_s2/(2n_p). The average switch currents I_S2,av = I_S2,av = I_o. If the maximum duty cycle loss in Equation (10) is given, then the maximum primary inductances L_r1 and L_r2 are derived as:

$$L_{r1}=L_{r2}<n_p{V}_{in,min}{d}_{loss,5,max}{T}_{sw}/4n_{s1}{I}_o$$

(12)

The inductance L_o is derived in Equation (13) under the maximum input voltage and minimum effective duty cycle.

$$L_o=\left(V_{in,max}/N_H-V_o\right)d_{e,min}{T}_{sw}/\Delta i_{Lo}=V_o\left(0.5-d_{e,min}\right)T_{sw}/\Delta i_{Lo}$$

(13)

A 420 W prototype is illustrated as a design example to obtain the circuit parameters. The operating low input voltage range V_in,L is from 30 V to 60 V; the medium input voltage range V_in,M is from 60 V to 120 V; and the high voltage range V_in,H is from 120 V to 240 V. The output voltage V_o is 12 V. The PWM switching frequency of Q₁–Q₆ is 100 kHz. If 30 V ≤ V_in < 60 V, S₁, S₂, Q₅, and Q₆ are off and S₃ is on. The voltage gain of the converter is G_L = 4d_effn_S1/n_p. If 60 V ≤ V_in < 120 V, S₂, Q₃, and Q₄ are off and S₁ and S₃ are on. The voltage gain of the converter is G_M = 2d_effn_S1/n_p. If 120 V ≤ V_in < 240 V, S₃, Q₃, and Q₄ are off and S₁ and S₂ are on. The voltage gain of the proposed circuit is G_H = d_effn_S1/n_p. In order to prevent the control signal oscillation at the transition voltages 60 V and 120 V, the Schmitt trigger circuits with ±5 V voltage tolerance are used between three input voltage ranges. Thus, the actual voltage ranges are V_in,L = 30 V–65 V, V_in,M = 55 V–125 V, and V_in,H = 115 V–240 V. The circuit efficiency is assumed 90% at minimum input voltage and full road condition, and the maximum duty cycle d_max and maximum duty cycle loss d_loss,5,max are assumed to be 0.45 and 0.15, respectively, at minimum input voltage. Therefore, the maximum effective duty cycle d_eff,max = d_max – d_loss,5,max = 0.3. The primary inductances L_r1 and L_r2 can be estimated as:

$$L_{r1}=L_{r2}=\eta V_{in,min}^2{d}_{loss,5}{d}_{eff,max}{T}_{sw}/4P_o\approx 0.9\mu H$$

(14)

From Equation (11), the turns-ratio N_L is calculated as:

$$N_L=n_p/2n_{s1}=2d_{eff,max}{V}_{in,min}/V_o\approx 1.5$$

(15)

In the laboratory prototype, the primary and secondary turns of transformer T are n_p = 12 and n_s1 = n_s2 = 4. The magnetizing inductances L_m1 = L_m2 = 820 µH. Under the low input voltage range, it can obtain the minimum effective duty cycle d_eff,min in Equation (16) at V_in = 65 V.

$$d_{eff,min}=d_{eff,max}{V}_{in,L,min}/V_{in,L,max}\approx 0.14$$

(16)

The assumed ripple current Δi_Lo = 3.5 A (10% of the rated load current) at V_in,L,max = 65 V. The output inductance L_o is obtained as:

$$L_o=d_{eff,min}{T}_{sw}\left(V_{in,L,max}/N_L-V_o\right)/\Delta i_{Lo}\approx 17\mu H$$

(17)

The output inductance L_o = 20 µH is used in the prototype circuit. The maximum root-mean-squared (rms) currents of Q₁ ~ Q₆ are approximated as $I_{o,rated}/\left(n_L\eta \sqrt{2}\right)\approx 18 A$. The maximum rating voltage of Q₁–Q₆ is equal to V_in,max = 240 V. Therefore, the MOSFETs IXTN80N30L2 with the 300 V/80 A/30 mΩ rating are used for switches Q₁–Q₆ and S₁. The MOSFETs STD100N10F7 with 100 V/80 A/6.8 mΩ ratings are used for switches S₂ and S₃. The synchronous rectifiers MOSFETs IXFH80N25X3 with 250 V/80 A/16 mΩ ratings are used for diodes D₁–D₄ to further reduce conduction losses. The output capacitance C_o = 470 µF/35V. The PWM generator UCC3895 is used to provide the PWM waveforms for Q₁–Q₆. The voltage regulator TL431 is used to regulate load voltage. The Schmitt comparators and logic gates are used to produce the on/off signals of S₁–S₃. Figure 6 provides the control blocks in the prototype circuit.

5. Experimental Verifications

The components of the prototype circuit were obtained in the previous section. The experimental results are verified in this section to demonstrate the converter effectiveness. Figure 7 demonstrates the test waveforms for low voltage operation. The PWM waveforms v_Q1,g – v_Q4,g at V_in = 30 V are provided in Figure 7a. The gate voltages of AC switches S₁–S₃ under V_in = 30 V are given in Figure 7b. One can observe that S₁ and S₂ are off and S₃ is on. Therefore, only the full-bridge converter with Q₁–Q₄ and diodes D₃ and D₄ are operated. Figure 7c provides the experimental results of v_ab and i_Lr1 under V_in = 30 V input. The secondary-side diode currents at V_in = 30 V are shown in Figure 7d. It can be obtained that D₁ and D₂ are in the off-state in the low input voltage operation. Similarly, the PWM waveforms v_Q1,g – v_Q4,g, v_S1,g – v_S3,g, v_ab, i_Lr1, and i_D1 – i_D4 at V_in = 63 V input are demonstrated in Figure 7e–h. From the test results in Figure 7c,g, one can observe that the leg voltage v_ab has a large duty cycle at V_in = 30 V compared to V_in = 63 V. Therefore, the output inductor current i_Lo has less ripple current Δi_Lo at 30 V input voltage than 63 V input voltage. This large ripple current at 63 V input can be observed in i_Lr1 in Figure 7g and i_D3 and i_D4 in Figure 7h. Figure 8 provides the measured waveforms of the converter for the medium voltage range operation and the rated power. For the medium input voltage range, S₁ and S₃ are conducting, S₂, Q₃, and Q₄ are turned off, and D₁ and D₂ are reverse biased. The gate voltages v_Q1,g, v_Q2,g, v_Q5,g, and v_Q6,g are given in Figure 8a, and the gate voltages of S₁–S₃ are shown in Figure 8b under V_in = 57 V. The measured waveforms of v_ac, i_Lr1, and i_D1 – i_D4 are demonstrated in Figure 8c,d under V_in = 57 V. Similarly, the measured waveforms of Q₁, Q₂, Q₅, Q₆, S₁–S₃, v_ac, i_Lr1, and i_D1 ~ i_D4 are provided in Figure 8e–h under V_in = 123 V. The measured results for the high voltage range are provided in Figure 9. For the high voltage range operation, S₁ and S₂ are on, S₃ is off, PWM switches Q₃ and Q₄ are off, and D₃ and D₄ are off. The turns-ratio 2n_p/n_s1 of the transformer T is operated in the high input voltage range. Figure 9a–d gives the test results of Q₁, Q₂, Q₅, Q₆, S₁–S₃, v_ac, i_Lr1, and i_D1 ~ i_D4 at V_in = 117 V. Similarly, the measured waveforms under V_in = 240 V are demonstrated in Figure 9e–h. The measured waveforms of Q₁ (leading-leg switch) are illustrated in Figure 10. From the test results in Figure 10, it is clear that the leading-leg switch Q₁ has the zero voltage switching turn-on characteristic from minimum to maximum input voltage and from 20% power to the rated power. Figure 11 gives the measured waveforms of Q₃ (lagging-leg switch) under 30 V input and 50% and 100% rated power. From Figure 11, it can be observed that Q₃ (lagging-leg switch) turns on under zero voltage from 50% rated power to full rated power. Q₅ and Q₆ are operated under medium and high input voltage ranges. Figure 12 gives the measured waveforms of Q₅ (lagging-leg switch) under V_in = 240 V and 50% and 100% rated power. One can observe that the leading-leg switch Q₅ turns on under zero voltage from 50% rated power to full rated power. Figure 13 demonstrates the measured efficiencies for different voltage ranges. Compared to the high input voltage range, the converter has large primary current and conduction losses under low input voltage range. Figure 14a gives the test results of the input voltage V_in and the switching signals v_Q3,g and v_Q4,g between V_in = 30 V and V_in = 80 V under full load operation. When 30 V < V_in < 60 V, the converter is operated in the low input voltage range. The switches Q₃ and Q₄ are activated, and switch S₁ is off. When V_in > 60 V and < 80 V, the converter is operated at the medium input voltage range. Therefore, S₁ is on, and Q₃ and Q₄ are off. Figure 14b provides the test results of V_in and S₂ between V_in = 65 V and V_in = 150 V under full load operation. When V_in is increased from 65 V and greater than 120 V, the switch S₂ is turned on. Then, the converter is operated under the high input voltage range. If the V_in is decreased from 150 V and less than 120 V, the switch S₂ is turned off, and the converter is operated under the medium input voltage range. Figure 14c shows the test waveforms of input and output voltages under full load. The input voltage is variated between 30 V (low input voltage range) and 200 V (high input voltage range). It is obvious that the load voltage is stable at 12 V output voltage.

6. Conclusions

To overcome the limited input voltage range operation of conventional PWM converters for solar power conversion, a novel three-leg PWM converter with an adjustable transformer turns-ratio was proposed and implemented to realize soft switching turn-on with wide input voltage operation. According to the input voltage range, the proposed three-leg converter had two equivalent circuits with variable primary winding turns on the input-side. On the secondary-side, the proposed converter also had two equivalent circuits by using variable secondary winding turns to achieve different voltage gains. Thus, the proposed three-leg converter had three equivalent circuits operated at different input voltage ranges to provide a stable DC output voltage. Each equivalent circuit using PWM operation could be operated to achieve 2:1 input voltage range operation. Thus, the proposed circuit could realize 8:1 (V_in,in ~ 8V_in,min) wide input voltage range operation. The Schmitt voltage comparators were adopted to generate the signals of the three voltage range selection. The proposed three-leg converter could work as the first stage of photovoltaic (PV) power converters with a wide range of voltage variation. Experiments from a laboratory prototype confirmed the theoretical converter characteristics with wide voltage range operation.