Single-Phase 13-Level Power Conditioning System for Peak Power Reduction of a High-Speed Railway Substation

The control and operation of a single-phase 13-level power conditioning system (PCS) for peak power reduction of a high-speed railway substation (HSRS) are proposed. This PCS is a single-phase 3100 V, 2 MVA 13-level H-bridge multi-level inverter structure. It has excellent power quality. It is easy to serialize by voltage. In addition, the DC bus power of each cell inverter is supplied by lithium-ion batteries. The generalized reduction gradient optimization algorithm based on past load pattern is applied to the power management system for peak power reduction of HSRS. The phase detector and power controller for the control of a single-phase PCS based on virtually coordinated axes using an all-pass filter are expected to be robust to external disturbances with fast response characteristics. This study also proposes an adapted select switch (ASS) method that can change the switching depending on the operation state of PCS and the state of charge (SOC) of the battery to minimize battery imbalance by controlling each cell inverter of the H-bridge. The validity of the proposed system was confirmed by PSiM simulation and experiments using a demonstration system of 6 MW PCS and 2.68 MWh batteries at one of Gyeongbu high-speed line substations in Korea.


Introduction
With the increase of traffic volume and traffic congestion due to industrial development and urban population concentration, measures to solve traffic problems are seriously highlighted. In this situation, electric railways have been proposed as the best alternative to solve transportation problems due to their advantages of being environmentally friendly, high energy use efficiency, safe, fast and convenient.
The demand for high-speed trains is continuously increasing due to their fast and convenient advantages. Therefore, railroad companies are increasing the number of rail operations to meet increasing demand. However, the increase in the number of trains causes problems of serious voltage drop and no margin for power supply capacity of high-speed railway substations (HSRSs) [1,2]. This peak power not only increases the electricity bill of the substation, but also adversely affects the stability of the power supply, such as voltage drop on the feed line [3].
Therefore, various studies have been performed to stabilize the high-speed railway power system. The optimal scheduling by adjusting the operation time and pattern of trains on the supply line has been highlighted as a way to use energy efficiently without any special cost investments [4]. However, it is not easy to find an optimal pattern because there are various variables depending on driving habits of locomotive engineers and sudden occurrences of train stations. For voltage stabilization, reactive Figure 1 shows the configuration of the peak power reduction system (PPRS) for HSRS. It is linked to a 55 kV supply line to perform the function of reducing peak power and stabilizing catenary voltage. The PPRS consists of a PMS, a PCS, and batteries. The PMS is responsible for monitoring the catenary condition and for protecting the cooperation system with the substation. The PCS controls the power as a power command given by the PMS. On the other hand, the battery performs the function of energy storage and transmits the battery state to the PMS via the battery management system (BMS).

Power Management System
In general, high-speed trains run according to a pre-determined schedule. Thus, they show relatively regularized load patterns on every day of the week. However, load patterns can be changed due to delays of passengers' boarding and train operation as well as the formation of temporary trains. Therefore, to reduce the peak load of HSRS, a future ESS operation plan has to be established optimally by predicting load patterns as accurately as possible [21]. Figure 2 shows the optimization algorithm of the ESS operation for peak power reduction using load prediction techniques [22].

Power Management System
In general, high-speed trains run according to a pre-determined schedule. Thus, they show relatively regularized load patterns on every day of the week. However, load patterns can be changed due to delays of passengers' boarding and train operation as well as the formation of temporary trains. Therefore, to reduce the peak load of HSRS, a future ESS operation plan has to be established optimally by predicting load patterns as accurately as possible [21]. Figure 2 shows the optimization algorithm of the ESS operation for peak power reduction using load prediction techniques [22].
To analyze daily load prediction patterns, past data were collected for three weeks and groups of candidates for peak power were chosen among 96 sections of 15 min duration per day. After this, charging and discharging sections were determined by applying the objective function to reduce the peak power among the peak power candidate groups. The objective function is set to minimize the charging cost of the daily ESS and the sum of peak reduction of the discharge interval, as in Equation (1).
where, i is an each section number of the daily peak power calculation interval for 15 min, EO i is the amount of PCS charging or discharging energy for section i, which is a plus sign in charging and a negative sign in discharging, C i is the electric charge rate at section i, and PL i is the saved electric charge through peak power reduction. The battery daily charge/discharge plan obtained from the objective function reflects the constraints and establishes the final optimization plan. The constraints are PCS operation interval, upper and lower ranges of the battery SOC, and upper and lower ranges of supply power. The mathematical models for optimization with constraints are solved by using the generalized reduced gradient (GRG) algorithm. To analyze daily load prediction patterns, past data were collected for three weeks and groups of candidates for peak power were chosen among 96 sections of 15 min duration per day. After this, charging and discharging sections were determined by applying the objective function to reduce the peak power among the peak power candidate groups. The objective function is set to minimize the charging cost of the daily ESS and the sum of peak reduction of the discharge interval, as in Equation (1).
where, is an each section number of the daily peak power calculation interval for 15 min, is the amount of PCS charging or discharging energy for section , which is a plus sign in charging and a negative sign in discharging, is the electric charge rate at section , and is the saved electric charge through peak power reduction.
The battery daily charge/discharge plan obtained from the objective function reflects the constraints and establishes the final optimization plan. The constraints are PCS operation interval, upper and lower ranges of the battery SOC, and upper and lower ranges of supply power. The mathematical models for optimization with constraints are solved by using the generalized reduced gradient (GRG) algorithm. Figure 3 shows the simulated results of PMS when the daily operation plan of ESS based on the predicted load is applied to the actual load data. According to the analysis of the substation power for some past years, the peak power generated by the substation is analyzed to be about 30 MW. Therefore, the target peak power of the substation is set to 24 MW under the assumption that the capacity of the peak reduction system is 6 MW PCS with 2.68 MWh battery when the PMS simulation is performed.  Figure 3 shows the simulated results of PMS when the daily operation plan of ESS based on the predicted load is applied to the actual load data. According to the analysis of the substation power for some past years, the peak power generated by the substation is analyzed to be about 30 MW. Therefore, the target peak power of the substation is set to 24 MW under the assumption that the capacity of the peak reduction system is 6 MW PCS with 2.68 MWh battery when the PMS simulation is performed.  The simulation results showed that the peak power generation of the substation was accurately predicted at 09:30 AM through the load prediction algorithm of the PMS. Therefore, the peak power generated by the substation was managed at 23.926 MW by supplying 6 MW power from the PCS. If the PMS failed to predict the load, the peak power generated from the substation might be approximately 30 MW.  The simulation results showed that the peak power generation of the substation was accurately predicted at 09:30 AM through the load prediction algorithm of the PMS. Therefore, the peak power generated by the substation was managed at 23.926 MW by supplying 6 MW power from the PCS. If the PMS failed to predict the load, the peak power generated from the substation might be approximately 30 MW.

Battery and Battery Management System
Batteries applied to the development of peak reduction devices for HSRS are designed to install in 40 ft containers, consisting of trays, racks, and banks with lithium-ion batteries. In the container, each of the six banks are insulated so that they can be connected to each cell inverter in the PCS. Batteries connected to the 2 MW PCS are installed with a capacity of 149 kWh for each bank with a total capacity of 894 kWh. Table 1 shows the specifications of each battery unit. In addition, monitoring and managing battery condition is performed through the battery management system (BMS). As shown in Figure 4, the BMS is also installed with a tray, rack, and system to match the battery configuration. The tray BMS collects the condition of the battery on a cell basis. The collected data is managed through the rack BMS. The system BMS also collects information from each rack BMS, compiles the information in bank units, and transmits it to the PCS and PMS in real time.  The simulation results showed that the peak power generation of the substation was accurately predicted at 09:30 AM through the load prediction algorithm of the PMS. Therefore, the peak power generated by the substation was managed at 23.926 MW by supplying 6 MW power from the PCS. If the PMS failed to predict the load, the peak power generated from the substation might be approximately 30 MW.

Battery and Battery Management System
Batteries applied to the development of peak reduction devices for HSRS are designed to install in 40 ft containers, consisting of trays, racks, and banks with lithium-ion batteries. In the container, each of the six banks are insulated so that they can be connected to each cell inverter in the PCS. Batteries connected to the 2 MW PCS are installed with a capacity of 149 kWh for each bank with a total capacity of 894 kWh. Table 1 shows the specifications of each battery unit. In addition, monitoring and managing battery condition is performed through the battery management system (BMS). As shown in Figure 4, the BMS is also installed with a tray, rack, and system to match the battery configuration. The tray BMS collects the condition of the battery on a cell basis. The collected data is managed through the rack BMS. The system BMS also collects information from each rack BMS, compiles the information in bank units, and transmits it to the PCS and PMS in real time.

Power Conditioning System (PCS)
The PCS applied to the development of the peak power reduction system for HSRS is connected in parallel to a single-phase 55 kV supply line. It controls the power according to the schedule of the charging and discharging power operation optimized by PMS. The H-bridge-type multilevel inverter method is applied for PCS to overcome the voltage limit of AC output by battery serial configuration voltage, thereby improving the system efficiency and output characteristics [23,24].
The applied PCS consists of a single phase 13-level H-bridge-type multilevel inverter using six separate battery banks, as shown in Figure 5. The PCS hardware is designed so that the main circuit of each cell inverter can be separated into a plug-in type. The control method of multi-level inverter adopts an intensive control method based on hardwire instead of a distributed control method through the communication interface, as shown in Figure 6, thus enhancing the stability and reliability of the system. In addition, the phase disposition (PD) PWM method is chosen for the

Power Conditioning System (PCS)
The PCS applied to the development of the peak power reduction system for HSRS is connected in parallel to a single-phase 55 kV supply line. It controls the power according to the schedule of the charging and discharging power operation optimized by PMS. The H-bridge-type multilevel inverter method is applied for PCS to overcome the voltage limit of AC output by battery serial configuration voltage, thereby improving the system efficiency and output characteristics [23,24].
The applied PCS consists of a single phase 13-level H-bridge-type multilevel inverter using six separate battery banks, as shown in Figure 5. The PCS hardware is designed so that the main circuit of each cell inverter can be separated into a plug-in type. The control method of multi-level inverter adopts an intensive control method based on hardwire instead of a distributed control method through the communication interface, as shown in Figure 6, thus enhancing the stability and reliability of the system. In addition, the phase disposition (PD) PWM method is chosen for the modular multi-level converter (MMC) to get the best THD characteristics [25]. A three-level switching is applied for each cell inverter using the unipolar PWM technique. Table 2 shows the comparison of specifications between the existing PCS and the proposed one. Unlike conventional techniques, the proposed PCS was designed to be suitable for single-phase high-voltage large capacity customers. through the communication interface, as shown in Figure 6, thus enhancing the stability and reliability of the system. In addition, the phase disposition (PD) PWM method is chosen for the modular multi-level converter (MMC) to get the best THD characteristics [25]. A three-level switching is applied for each cell inverter using the unipolar PWM technique. Table 2 shows the comparison of specifications between the existing PCS and the proposed one. Unlike conventional techniques, the proposed PCS was designed to be suitable for single-phase high-voltage large capacity customers.

PCS Controller Design
Controllers for the single-phase 13-level multi-level PCS consist of a phase detection controller for voltage sensing of the catenary, a power controller for power control, and a balancing controller for optimal utilization of batteries separated by a cell inverter. In this paper, controllers are designed using virtual coordinate axes to improve the dynamic characteristics of phase detection controllers and power controllers on the single-phase system. This paper also uses a battery balancing control technique that allows the battery separated by each cell inverter to distribute power according to the SOC of batteries and PCS operating conditions.

Single-Phase Synchronous Reference Frame-Phase Locked Loop (SRF-PLL) Controller
The PCS connected to the single-phase 55 kV power line shall provide power by accurately identifying the voltage phase information of the catenary. Normally, the synchronous reference frame-phase locked loop (SRF-PLL) technique is applied to the three-phase power system, which detects the voltage phase angle through the synchronous coordinate transformation from the measured voltage [26,27]. In this paper, to apply the SRF-PLL technique to the single-phase system, the all-pass filter (APF) method is used to detect the voltage phase angle.
In particular, a low-pass filter (LPF) was applied to the voltage converted into a synchronous reference frame for stable phase detection and reduced disturbance so that the response characteristics of PLL could be improved and its stability could be ensured [28]. Figure 7 shows a block diagram of a single-phase SRF-PLL phase angle detector. The single-phase input voltage, v s , can be determined with Equation (2).
where, v s qs is the q-axis voltage at the d-q stationary coordinate system. Applying APF, as in Equation (3), v s ds , the orthogonal component of v s qs can be obtained with Equation (4).
The d-q synchronous coordinate transformation from Equations (2) and (4) can be calculated using Equation (5). As a result, v e ds and v e qs are calculated as shown in Equation (6). If the phase angle of the voltage can be accurately known, the d-axis voltage v e ds becomes zero and the q-axis voltage v e qs becomes the magnitude of the voltage, as shown in Equation (6). The controller is configured as shown in Figure 7 so that the d-axis voltage is zero due to this relationship. In the block diagram shown in Figure 7, if the phase angle range is small enough, it can be sin θ e θ e . For this reason, the error of the d-axis voltage can be linearized to the error of the phase angle. The block diagram in Figure 7 is modeled as a linearized control system with LPF, as shown in Figure 8.
The d-q synchronous coordinate transformation from Equations (2) and (4) can be calculated using Equation (5). As a result, and are calculated as shown in Equation (6).
If the phase angle of the voltage can be accurately known, the d-axis voltage becomes zero and the q-axis voltage becomes the magnitude of the voltage, as shown in Equation (6). The controller is configured as shown in Figure 7 so that the d-axis voltage is zero due to this relationship. In the block diagram shown in Figure 7, if the phase angle range is small enough, it can be sin ≅ . For this reason, the error of the d-axis voltage can be linearized to the error of the phase angle. The block diagram in Figure 7 is modeled as a linearized control system with LPF, as shown in Figure 8. From Figure 8, the transfer function of the PLL system is calculated with Equation (7), where ( ) and ( ) are the open-loop transfer function and the low-pass filter transfer function, as shown in Equations (8) and (9), respectively.
where, is the proportional gain of the PI controller, τ is the time constant of the PI controller, and is the bandwidth of the low-pass filter. Pole placement techniques are used to model the PLL closed loop transfer function of Equation (7) into a typical secondary control system. Equation (7)  From Figure 8, the transfer function of the PLL system is calculated with Equation (7), where G(s) pll and K(s) LPF are the open-loop transfer function and the low-pass filter transfer function, as shown in Equations (8) and (9), respectively.
where, K P is the proportional gain of the PI controller, τ is the time constant of the PI controller, and ω c is the bandwidth of the low-pass filter. Pole placement techniques are used to model the PLL closed loop transfer function of Equation (7) into a typical secondary control system. Equation (7) may be expressed in the form of multiplication of the dominant pole and a typical secondary control system, as shown in Equation (10) [28,29].
where ζ is the damping ratio and ω n is the bandwidth of the typical secondary system. Equations (11) and (12) can be calculated by assuming that Equation (10) has a dominant pole of k = 1 and applying the coefficient comparison method from the characteristic equation of Equations (7) and (10).
Setting the bandwidth ω n and damping ratio ζ of the typical secondary system gives the bandwidth of the low-pass filter and the optimized gain of the PI control. Empirically, the cutoff frequency of LPF, ω c , is determined from 100 to 300 rad/s. For applying to the PCS, the bandwidth and damping ratio are chosen as 100 rad/s and 0.75 respectively, to meet ω c to be 150 rad/s.

Power Controller
Definitions of electric power for the single-phase in the sinusoidal system have been well established. For an ideal single-phase system with a sinusoidal voltage source and a linear load, the voltage and current are represented by Equation (13). v s = V s sin ω e t, . . . , i s = I s sin(ω e t + φ) where V s and I s represent the peak values of the voltage and current. The instantaneous power is given by the product of the instantaneous voltage and current, as shown in Equation (14).
Equation (14) shows that the instantaneous power of the single-phase system is not constant. It has an oscillating component at twice the line frequency with the average value of 1 2 V s I s cos φ. Decomposition of the oscillating component and rearrangement of Equation (14) yields the following Equation (15), with two terms which derive the traditional concept of active and reactive power [30].
where P and Q represent active and reactive powers, respectively. In general, the power of the three-phase system can be analyzed through the d-q synchronous transformation, as shown in Equation (16)  where v e ds , v e qs , i e ds , and i e qs are the d-q synchronous transformation of the input voltage, v s , and current, i s . For a single-phase system, it is possible to calculate power applying Equation (16) by calculating the voltage and current orthogonal components using an all-pass filter. In addition, the v e ds can be calculated as '0 , which is the phase reference value of the system voltage.
The power in the single-phase system can be verified, as shown in Equation (17), to enable the control of active and reactive powers through d-axis and q-axis currents.
where, P * is the active power command, Q * is the reactive power command, I e * ds is the d-axis current command, and I e * qs is the q-axis current command. Figure 9 shows the equivalent circuit of a single-phase PCS system, where v s is the source voltage, v c is the generated voltage of PCS, i s is the generated current of PCS, and L s and R s are the reactance and resistance of the source and filter reactor. The voltage equation of the equivalent circuit shown in Figure 9 is shown in Equation (18). Equation (18) in the d-q synchronous coordinate system can be expressed as shown in Equation (19).

Current Controller
where, is the d-axis voltage of the PCS, is the q-axis voltage of the PCS, and is 0. If the intermediate variable and are defined as in Equation (20), Equation (19) can be expressed as Equation (21).
Variables and are obtained by Equation (22). Equation (18) in the d-q synchronous coordinate system can be expressed as shown in Equation (19).
where, v e cd is the d-axis voltage of the PCS, v e cq is the q-axis voltage of the PCS, and v e ds is 0. If the intermediate variable x 1 and x 2 are defined as in Equation (20), Equation (19) can be expressed as Equation (21). Variables x 1 and x 2 are obtained by Equation (22).
where k P and k I are the proportional gain and the integral gain of the PI controller, respectively. Figure 10 shows a block diagram of the current controller. From Figure 10, the transfer function of the current controller is calculated, as shown in Equation (23).
where α is a parameter for selecting the PI or IP controller (α = 1 for PI and α = 0 for IP). The advantage of the IP controller is that it is easy to set gains. However, the phase delay in the cut-off frequency band is 90°. On the other hand, for PI controllers, although there are some difficulties in setting gains due to the addition of zero to the transfer function, the phase delay is only 45°, thus showing better dynamic characteristics than the IP controller under similar gain.
In this paper, α is selected as '1′ to compose the PI current controller. The PI controller is very difficult to designate poles and zeroes as arbitrary values. Thus, it is relatively easy to establish stable gains by applying the 'approximate gain setting' [33].
This approach takes advantage of the fact that the closed loop transfer function appears as ( + ) ⁄ , as shown in Equation (24), approximating the open loop transfer function to ⁄ . At this point, the cross-over frequency at which the gain of the closed loop transfer function is '1' is equal to .
Calculation of the transfer function by Equations (23) and (24) is performed as shown in Equation (25). From the calculated equation, the gain value of the current controller by the coefficient comparison method can be obtained, as shown in Equation (26).
If the cross-over frequency, , is large, dynamic characteristics are great. Therefore, the quick response in transient condition may be obtained. However, due to the sensitivity of noise and disturbance in the system, it is necessary to select appropriate values. Empirically, it is determined between 750 to 1500 rad/s of LPF. In this study, LPF of 1200 rad/s is applied to the PCS current controller. The advantage of the IP controller is that it is easy to set gains. However, the phase delay in the cut-off frequency band is 90 • . On the other hand, for PI controllers, although there are some difficulties in setting gains due to the addition of zero to the transfer function, the phase delay is only 45 • , thus showing better dynamic characteristics than the IP controller under similar gain.
In this paper, α is selected as '1 to compose the PI current controller. The PI controller is very difficult to designate poles and zeroes as arbitrary values. Thus, it is relatively easy to establish stable gains by applying the 'approximate gain setting' [33].
This approach takes advantage of the fact that the closed loop transfer function appears as ω cc /(s + ω cc ), as shown in Equation (24), approximating the open loop transfer function to ω cc /s. At this point, the cross-over frequency at which the gain of the closed loop transfer function is '1' is equal to ω cc .
Calculation of the transfer function by Equations (23) and (24) is performed as shown in Equation (25). From the calculated equation, the gain value of the current controller by the coefficient comparison method can be obtained, as shown in Equation (26).
(s + ω cc ) k P L s s + k I L s = ω cc s 2 + R s + k P L s s + k I L s (25) k P = L s ω cc , k I = ω cc (k P + R s ) + k P If the cross-over frequency, ω cc , is large, dynamic characteristics are great. Therefore, the quick response in transient condition may be obtained. However, due to the sensitivity of noise and disturbance in the system, it is necessary to select appropriate values. Empirically, it is determined between 750 to 1500 rad/s of LPF. In this study, LPF of 1200 rad/s is applied to the PCS current controller.

Multi-Level PWM Configuration
As shown in Figure 11, various modulation schemes can be applied for the switching of multi-level inverters depending on the purpose of use and the application area [34]. The H-bridge-type inverter is applied with a level-shifted method (LSM) to enable power distribution control as DC link power is used by the battery. It is also applied using the PD method with the best THD characteristics among LSM methods [35].  The cascade-type inverter consisting of an H-bridge has an output voltage, as shown in the red dotted line in Figure 12. The Fourier transform is calculated with Equation (27). In addition, the amount of power over one cycle of each cell inverter is distributed, as shown in Equation (28), by phase angles where θ m is sin n m and n is from 1 to m.
where is sin and n is from 1 to m. As shown in the results of Equation (28), the H-bridge-type inverter requires an appropriate power distribution algorithm to use the equal energy of each separated dc-link stage. In particular, if batteries are utilized, they should be operated by considering the SOC status of batteries separated from each cell inverter. If the power distribution of each battery bank in a multi-level PCS is not achieved, the PCS will not be operating due to SOC deviations between battery-banks connected to each cell inverter.
Typically, the carrier of a multi-level inverter is balanced on each cell inverter using the reference period rotation (RPR) method, which rotates the switching of each cell inverter to the cycle of the reference voltage, or the carrier period rotation (CPR) method, which rotates to the cycle of the carrier [36].
Here, the CPR method has the advantage of fast power distribution rotation cycles for each cell inverter. However, it has the disadvantage of increasing switching losses for each cell inverter. As a result, the capacity of the heat-block is minimized by applying the RPR method to the commercial product to reduce switching losses. However, conventional balancing methods can be used effectively if there are no restrictions on separated DC power, but they are difficult to apply by deviations in the battery bank if isolated DC power is used on a limited basis, such as batteries.
In this paper, an adapted select switch (ASS) method that can be adapted and operated according to the occurrence of these battery deviations is proposed. The ASS method actively changes switching depending on the operating state of the PCS and the SOC state of the battery to output the battery. The ASS method is implemented as a rank function that selects the ranking of the SOC status of batteries in real time. In addition, the switching matching function for the PWM output of each cell inverter is calculated through the arrangement of the rank function to the battery SOC state and the value of the PCS's charging and discharging state variables. Figure 13 shows a flow chart for the configured battery balancing algorithm. As shown in Figure 13, the battery balancing algorithm performs ranking operations through SOC status information for the battery bank. The maximum deviation of the battery bank is less than 5%. It operates in RPR mode. If the deviation reaches 5% or more, the ASS mode is started. When operation starts in ASS mode, the hysteresis band is configured so that the current state can be maintained until the battery deviation is less than 2%.
In the ASS mode, the switching mapping function is configured so that the SOC of the battery bank can be charged in low order when the PCS is charged. The SOC of the battery bank can be discharged in high order when the PSC is discharged.
value of the PCS's charging and discharging state variables. Figure 13 shows a flow chart for the configured battery balancing algorithm. As shown in Figure  13, the battery balancing algorithm performs ranking operations through SOC status information for the battery bank. The maximum deviation of the battery bank is less than 5%. It operates in RPR mode. If the deviation reaches 5% or more, the ASS mode is started. When operation starts in ASS mode, the hysteresis band is configured so that the current state can be maintained until the battery deviation is less than 2%.

Simulation Results
To verify the peak power reduction algorithm of the single-phase 13-level MMC-type PCS, simulation studies were implemented with a PSiM simulator. When it performs the PSiM simulation, the controller configuration is modelled as a digital controller using the dynamic linking library (DLL) to implement controllers in experiments by using the same C-code in PSiM.
The simulation confirmed the response characteristics for single-phase PLL controllers and power controllers. In addition, the operation of the balancing algorithm according to battery voltage separated by each cell inverter and the output characteristics of each PWM mode were confirmed. Table 3 shows main parameters used in simulations.  Figure 14 shows a simulation result that identifies the response characteristics of a single-phase SRF-PLL controller. The response characteristics of the PLL were verified by making the voltage change by 42% and by making the phase jump by 45 degrees. As a result, the response time of the PLL controller was 11.5 ms when phase jumps and voltage changes were made. The waveform shown in Figure 15a (bottom) also confirms that the voltage and current waveforms of the PCS output are sinusoidal and controlled by the unit power factor. Figure 15b shows response characteristics during control by including the reactive power command in Figure  15a. The reactive power was changed from 250 kVar to 500 kVar, as shown in the waveform of Figure  15b (middle). Including reactive power, as shown in these results, it was confirmed that active and reactive powers had the same response characteristics. This is the result of the power component being separated by the d-q axis of the proposed power controller. The waveform shown in Figure  15b (bottom) is the result of checking the output voltage and current of the PCS. Results showed that the power factor was controlled by the reactive power control. For this reason, the bandwidth of the phase detection controller is designed with the experience of the engineer as the system situation. The bandwidth of the phase detection controller used in the simulation is chosen as 100 rad/s by taking account of the situation in the actual demonstration system.
If the bandwidth of the phase detection controller is selected too large, it may cause the controller to become more sensitive and be significantly affected by external disturbances, which may cause the controller to malfunction. On the other hand, choosing a too-small bandwidth will cause the controller to become too slow. Figure 15 shows simulation results for verifying the response characteristics according to the power command. Figure 15a shows response characteristics of the power controller when the active power command value is changed from 1 MW to 2 MW. As shown in these results, it can be seen that the actual active power (P_real) is responding to the active power command (P_ref) in about 12 ms without overshoot.
The waveform shown in Figure 15a (bottom) also confirms that the voltage and current waveforms of the PCS output are sinusoidal and controlled by the unit power factor. Figure 15b shows response characteristics during control by including the reactive power command in Figure 15a. The reactive power was changed from 250 kVar to 500 kVar, as shown in the waveform of Figure 15b (middle). Including reactive power, as shown in these results, it was confirmed that active and reactive powers had the same response characteristics. This is the result of the power component being separated by the d-q axis of the proposed power controller. The waveform shown in Figure 15b Table 3. The simulation conditions for verifying the operation of the balancing mode are set as follows. Figure 16a,b set each battery bank voltage at 800 V for the PCS to operate in RPR mode. Figure 16c,d randomly set each battery bank voltage from 800 V to 900 V for the PCS to operate in ASS mode. The power command of the PCS is set to allow charging of 2 MW, regardless of mode. From the simulation results, it can be explained that the mode is automatically selected and operated according to the battery voltage condition and operating conditions of the PCS. Figure 16a,b are results selected and operated in RPR mode. In Figure 16a, the top waveform shows the output voltage and current of the PCS, the middle waveform shows each battery bank voltage, and the bottom waveform shows each battery bank power. Figure 16b shows the output voltage waveform of each cell inverter. These results confirmed that during RPR mode operation, the output of each cell inverter was rotated every 100 ms (6/60 Hz). Therefore, the power of each battery bank charges the same power every 100 ms. Results for the ASS mode in Figure 16c,d are verified in the same way as in the RPR mode. In the ASS mode, it was verified that the output of each cell inverter was controlled through the ranking function calculated by the PCS operation status and the battery bank voltage. Figure 17a shows simulation results of single-phase 13-level PCS output voltage and current waveforms. Figure 17b shows the fast Fourier transform (FFT) analysis of the output waveform. As shown in the FFT analysis results in Figure 17b, the THD of PWM output voltage and the output current were analyzed to be 10.8% and 2.4% respectively, according to the application of the 13-level multi-level PCS. Since the analyzed THD value was significantly lower than the normal two-level PCS, the size of the output filter could be compact. and current of the PCS, the middle waveform shows each battery bank voltage, and the bottom waveform shows each battery bank power. Figure 16b shows the output voltage waveform of each cell inverter. These results confirmed that during RPR mode operation, the output of each cell inverter was rotated every 100 ms (6/60 Hz). Therefore, the power of each battery bank charges the same power every 100 ms. Results for the ASS mode in Figure 16c,d are verified in the same way as in the RPR mode. In the ASS mode, it was verified that the output of each cell inverter was controlled through the ranking function calculated by the PCS operation status and the battery bank voltage.  Figure 17b shows the fast Fourier transform (FFT) analysis of the output waveform. As shown in the FFT analysis results in Figure 17b, the THD of PWM output voltage and the output current were analyzed to be 10.8% and 2.4% respectively, according to the application of the 13-level multi-level PCS. Since the analyzed THD value was significantly lower than the normal two-level PCS, the size of the output filter could be compact.

Experimental Results
The PPRS demo system consisting of 6 MW PCS and 2.68 MWh batteries was installed at the Korean railroad (KORAIL) substation under commercial operation to verify the effectiveness of the PPRS for HSRS. The PPRS for demonstration consisted of a unit capacity of 2 MW PCS, 894 kWh battery, with each PCS connected to the transformer at three parallels. In addition, the PCS's power operation was provided with the interface through PMS, which was developed for HSRS. Table 4 shows the specifications of the main facilities of the demonstration system. Figures 18 and 19 show operating characteristics of the phase detection controller. The operating

Experimental Results
The PPRS demo system consisting of 6 MW PCS and 2.68 MWh batteries was installed at the Korean railroad (KORAIL) substation under commercial operation to verify the effectiveness of the PPRS for HSRS. The PPRS for demonstration consisted of a unit capacity of 2 MW PCS, 894 kWh battery, with each PCS connected to the transformer at three parallels. In addition, the PCS's power operation was provided with the interface through PMS, which was developed for HSRS. Table 4 shows the specifications of the main facilities of the demonstration system.  Figures 18 and 19 show operating characteristics of the phase detection controller. The operating characteristics of the phase detector are described to verify the response characteristics of the PLL control at change amplitude and phase of the input voltage and to verify that the phase synchronization of the PCS output voltage is performed from the phase information detected by the PLL control. Figure 18 shows the experimental results of the response characteristics of the PLL controller by applying a simulated signal to the input voltage sensor to change the amplitude and phase of the input voltage. From the experimental results, the response time was measured to be 16 ms and the overshoot angular frequency of line voltage was 110 rad, as shown in Figure 18, which were very similar to the simulation results shown in Figure 14.  Figure 18 shows the experimental results of the response characteristics of the PLL controller by applying a simulated signal to the input voltage sensor to change the amplitude and phase of the input voltage. From the experimental results, the response time was measured to be 16 ms and the overshoot angular frequency of line voltage was 110 rad, as shown in Figure 18, which were very similar to the simulation results shown in Figure 14. Figure 19 shows that the PWM output voltage of the PCS detected from the actual catenary voltage is phase-synchronized through the phase information. Figure 19a also shows that the controller error according to the characteristics of the digital controller has one sampling error.    results of checking the battery information on the PMS. Battery information is transmitted by communication from the system BMS to the PMS. The transmitted battery information displays the fault information of the battery and the operational status of each battery bank such as SOC, voltage, current, power, and rack contactor state. Figure 20b and Figure 21b are output voltage waveforms of each cell inverter measured during PMS monitoring. The main measurement data in Figures 20 and 21 are summarized, as shown in Table 5.   As shown in Figure 20, the maximum deviation of the battery bank under RPR mode is 0.4%. Experimental results confirmed that the output of each cell inverter rotated at 100 ms cycles, as shown in the simulations, at which point, the power of each battery bank was charged equally at 166 kW. On the other hand, as shown in Figure 21, the maximum deviation of the battery bank under ASS mode is 4%. However, as shown in the experimental results, the power of each cell inverter is charging differently depending on the PCS condition and the SOC condition of each battery bank.
The change of the battery balancing mode is set through the hysteresis band. Changing mode by hysteresis band operates in the ASS mode when the battery bank SOC deviation is 5.0% or higher. It returns to the RPR mode when the battery bank SOC deviation is less than 2.0%. If the bandwidth of the hysteresis band is too narrow, the deviation in the battery bank will be smaller, making it possible to use the battery bank efficiently. However, it has the disadvantage of increasing the frequency of balancing mode transitions. On the other hand, if the bandwidth of the hysteresis band is too wide, it can reduce the frequency of balancing mode transitions. The drawback is that it is difficult to use battery banks efficiently.     Table 5.   As shown in Figure 20, the maximum deviation of the battery bank under RPR mode is 0.4%. Experimental results confirmed that the output of each cell inverter rotated at 100 ms cycles, as shown in the simulations, at which point, the power of each battery bank was charged equally at 166 kW. On the other hand, as shown in Figure 21, the maximum deviation of the battery bank under ASS mode is 4%. However, as shown in the experimental results, the power of each cell inverter is charging differently depending on the PCS condition and the SOC condition of each battery bank.
The change of the battery balancing mode is set through the hysteresis band. Changing mode by hysteresis band operates in the ASS mode when the battery bank SOC deviation is 5.0% or higher. It returns to the RPR mode when the battery bank SOC deviation is less than 2.0%. If the bandwidth of the hysteresis band is too narrow, the deviation in the battery bank will be smaller, making it possible to use the battery bank efficiently. However, it has the disadvantage of increasing the frequency of balancing mode transitions. On the other hand, if the bandwidth of the hysteresis band is too wide, it can reduce the frequency of balancing mode transitions. The drawback is that it is difficult to use battery banks efficiently. Figure 22 shows output results when the PCS is operated from 500 kW to 2000 kW. The PCS power command is given by the inclination of 200 kW/s due to the power acceptability problems in tramway. The experimental results shown in Figure 22 are verification results of the waveform to the output voltage and current of the single-phase 13-level multi-level PCS for the power command. The output voltage and current of the PCS can be seen to be close to the sinusoidal waveform, as shown in the experimental results. In addition, the stable power to tramway is supplied without transient characteristics. It depends on the application of the slope in case of changed power command.  Table 6 shows operation data of PMS after applying the peak power reduction algorithm of the HSRS for a week. The PMS was configured to manage the peak power of the substation below 24 MW by using the 6 MW PCS with 2.68 MWh battery as in the simulation. As the experimental results show, the peak power was 23,090 kW on July 10 with the operation of the peak power reduction system. If the peak power reduction system was not operated, the peak power during that period might be 25,689 kW on July 14. Figure 23 shows a detailed analysis of the PMS operation status data for July 14 from the operation data in Table 6. In Figure 23, the red solid line is the expected peak power when the peak reduction device is not activated, and the blue solid line is the actual generated peak power when the peak reduction device is operated. The blue bar represents the charge and discharge power of the peak reduction device.   Table 6 shows operation data of PMS after applying the peak power reduction algorithm of the HSRS for a week. The PMS was configured to manage the peak power of the substation below 24 MW by using the 6 MW PCS with 2.68 MWh battery as in the simulation. As the experimental results show, the peak power was 23,090 kW on July 10 with the operation of the peak power reduction system. If the peak power reduction system was not operated, the peak power during that period might be 25,689 kW on July 14.  Figure 23 shows a detailed analysis of the PMS operation status data for July 14 from the operation data in Table 6. In Figure 23, the red solid line is the expected peak power when the peak reduction device is not activated, and the blue solid line is the actual generated peak power when the peak reduction device is operated. The blue bar represents the charge and discharge power of the peak reduction device.  These experimental results confirmed that the PMS accurately estimated that the peak power was generated at 09:30 AM. At this point, the PCS also supplied 3265 kW of power to the tramway by the PMS command, thereby managing the peak power at 22,424 kW.
If the peak power of the substation is 30 MW within the operating period of the demo system, it is expected that PPRS would have reduced the peak power of the substation to 24 MW by supplying 6 MW to the tramway. This is about a 20% reduction in peak power for substations [37].

Conclusions
This paper proposed the single-phase 13-level PCS for peak power reduction of HSRS. The GRG optimization algorithm was applied to the PMS for the management of peak power. The PCS is the configuration of a single-phase 3100 V, 2 MVA, 13-level H-bridge multi-level inverter, which has excellent power quality. In addition, it is easy to serialize by voltage. Moreover, the DC bus power of each cell inverter was supplied by lithium-ion batteries. The phase detector and power controller for the control of a single-phase PCS based on the virtually coordinated axes using an all-pass filter were proposed to be These experimental results confirmed that the PMS accurately estimated that the peak power was generated at 09:30 AM. At this point, the PCS also supplied 3265 kW of power to the tramway by the PMS command, thereby managing the peak power at 22,424 kW.
If the peak power of the substation is 30 MW within the operating period of the demo system, it is expected that PPRS would have reduced the peak power of the substation to 24 MW by supplying 6 MW to the tramway. This is about a 20% reduction in peak power for substations [37].

Conclusions
This paper proposed the single-phase 13-level PCS for peak power reduction of HSRS. The GRG optimization algorithm was applied to the PMS for the management of peak power. The PCS is the configuration of a single-phase 3100 V, 2 MVA, 13-level H-bridge multi-level inverter, which has excellent power quality. In addition, it is easy to serialize by voltage. Moreover, the DC bus power of each cell inverter was supplied by lithium-ion batteries. The phase detector and power controller for the control of a single-phase PCS based on the virtually coordinated axes using an all-pass filter were proposed to be robust to external disturbances with fast response characteristics. This study also proposed the ASS method, which changes the switching depending on the operation state of PCS and the SOC of the battery to minimize battery imbalance by controlling each cell inverter of the H-bridge.
The validity of the proposed system was verified by PSiM simulation and experiments. Especially, the experiment was run for a week with a 6 MW PCS and 2.68 MWh batteries as a demo system at one HSRS of KORAIL under commercial operation. As the results of the operation showed, the PMS accurately predicted the peak power generation time of the substation and managed the peak power of the substation within the target peak value of 24,000 kW. The proposed PCS was supplied accurately from the PMS power command through the phase detection controller and the power controller. In case of voltage deviation of each battery bank, the RPR mode and ASS mode were automatically switched by the battery voltage balancing controller to control the voltage. Therefore, each battery bank could use the SOC from 5% to 95% practically. In the future, it is necessary to continuously obtain operation data to ensure the reliability and stability of the performance and operation of the proposed system.