A New Backward Euler Stabilized Optimum Controller for NPC Back-to-Back Five Level Converters

Abstract

This paper presents a backward Euler stabilized-based control strategy applied to a neutral point clamped (NPC) back-to-back connected five level converters. A generalized method is used to obtain the back-to-back NPC converter system model. The backward Euler stabilized-based control strategy uses one set of calculations to compute the optimum voltage vector needed to reach the references and to balance the voltage of the DC-bus capacitors. The output voltage vector is selected using a modified cost functional that includes variable tracking errors in the functional weights, whereas in classic approaches, the weights are considered constant. The proposed modified cost functional enables AC current tracking and DC-bus voltage balancing in a wide range of operating conditions. The paper main contributions are: (i) a backward Euler stabilized-based control strategy applied to a double, back-to-back connected, five level NPC converter; (ii) the use of cost functional weight varying as a function of the controlled variable tracking errors to enforce the controlled variables and to balance the DC capacitor voltages; and (iii) the demonstration of system feasibility for this type of converter topology and control strategy, ensuring a high enough computational efficiency and extending the modulation index from 0.6 to 0.93. Experimental results are presented using a prototype of a five level NPC back-to-back converter.

1. Introduction

Multilevel power converters are the converters of choice for high power medium voltage applications such as electrical machine drives or the grid interface connection of renewable energy sources [1,2,3,4]. Considering today’s power semiconductor limitations on voltage blocking and dv/dt, the attention and development of multilevel voltage source converters is increasing due to known attractive features, when compared with two level voltage source converters [5,6,7,8].

Among multilevel converters, the neutral point clamped (NPC) converter introduced in [5] is well accepted and used in several industrial applications [7]. The main drawback of the NPC topology is the voltage imbalance of the DC-bus capacitors, which has been an active research topic using external circuits [8,9], modifying pulse width modulation (PWM) techniques [10,11,12,13], space vector modulation (SVM) [3,4,14], sliding mode control exploiting converter vector redundancies [15], and predictive control [16,17,18]. Some of these techniques require a significant computing power, or have limitations when redundant vector-based strategies are used to balance the capacitor voltages. The theoretical maximum output modulation index is around 0.6 for a back-to-back connected NPC converter with an active load and zero active power exchange, when using the SVM-based control strategy [3,4].

Known NPC modulation strategies such as PWM and SVM [10,12] while operating at a constant switching frequency, do not guarantee that controlled outputs are free from DC-bus voltage disturbances, semiconductor “ON” voltages, dead times, or switching delays.

Hysteretic control methods are robust to semiconductor non-idealities, load changes, and disturbances, and present fast dynamic responses. Their major drawback is the variable switching frequency, which depends on the operating conditions and load parameters. For some quality indexes, hysteretic control methods may need higher switching frequencies when compared to PWM or SVM modulation techniques [17,18].

Optimum predictive control techniques drive the output errors towards zero by minimizing the cost functional in each sampling period [19,20,21,22]. Given the controlled output references, the first step of the NPC predictive controller is to sample the state variables. The second step uses a non-linear model of the system to predict values of the state variables in the next sampling intervals for every possible NPC switching configuration (termed the vector). This requires a powerful numerical processor to compute all the possible future values of the state variables in a sampling step well below 100 µs, to allow switching frequencies around 5 kHz. The last step computes the cost functional for all NPC vectors and chooses the vector that gives the minimum cost functional value in that sampling interval. These three steps are repeated in the next sampling time.

Predictive controllers for power electronic converters seem to be a potential alternative since they are well suited to control variables (e.g., currents, voltages, power) presenting coupled dynamics, and can offer closed loop dynamics with decoupled behavior [19]. However, in each sampling time, predictive algorithms must compute the state variable values in the next sampling interval for all of the possible NPC vectors, together with the corresponding cost functional, requiring a powerful processing unity for converters with available vectors in excess of 27 (three level converters).

Predictive algorithms used to reduce time consumption have been reported by [23,24]. These algorithms use the system inverse dynamics to directly compute the necessary output voltage vector required to track references, while predictive controllers estimate the output errors for all the available vectors. The output voltage vector is then selected among those which are available by minimizing a cost functional that computes the distance between the optimal voltage vector and the existing voltage vectors. However, in [23], the voltage balancing problem was not addressed but only pointed out briefly in cases where the converter presented redundancies. In [24], the voltage balancing problem was solved for three level inverters, but the dependence on non-modeled dynamics is not addressed. This paper uses a stable method to compute the necessary output voltage vector and extends the voltage balancing to five level NPC converters, where balancing is more challenging, by using an approach that is valid even if there are no redundant vectors. In [24], only constant weights are used in the quadratic cost function, while the proposed paper uses variable weights as a function of variable tracking errors, for the cost functional equations of functions. The approach proposed here, while not needed in three level NPCs, is nearly mandatory in five level inverters, as balancing the four DC capacitor voltages using 250 vectors is, at least, more complex and difficult. The approach of this paper enables the enlargement of NPC voltage balancing range for different active and reactive power flow conditions. In view of these problems, this paper presents a backward Euler stabilized control strategy applied to a back-to-back five level NPC converter to control the line inject AC currents and to balance the four capacitor voltages. The paper starts with the back-to-back converter modeling, using a systematic switching variable generalized for m level converters (Section 2). This modeling is an essential tool for the analysis and control strategy of the NPC back-to-back converter. The control strategy proposed (Section 3) uses a backward Euler stabilized approach to directly compute the optimum output voltage vector required to track the references in the next time step. The output voltage vector is then selected from the available voltage vectors by minimizing a variable weight cost functional that includes variable tracking errors in the weighting of the error between the optimal voltage vector and the possible voltage vectors. The new proposed cost function enables active and reactive power flow control and DC-bus voltage balancing, in a wide range of operating conditions. Simulation and experimental results for two five level NPC back-to-back connected converters validate the proposed control strategy and show the feasibility of the proposed system (Section 4). Experimental results are obtained using a 230 V ac/600 V dc/230 V ac five level NPC back-to-back converter prototype. Both converters are controlled using one Power PC-based board (DS1103) with a 32 µs sampling time, for acquiring all the data, completing the calculations of the two 125 vectors converters, and computing the gate signals to drive all the 48 IGBTs.

2. System Modeling

Figure 1 shows the m level back-to-back converter arrangement. The generalized system is composed by two three phase back-to-back m level diode-clamped converters, where each NPC converter is connected to an AC system using a transformer. The modeling assumes ideal electrical components and semiconductor devices (zero ON voltages, zero OFF currents, zero switching times).

To obtain a model valid for NPC multilevel converters having an arbitrary number of levels m, it is advantageous to start numbering the upper IGBT switches S_k1, S_k2, … S_kn, … S_k(m−1) in each k leg (k ∈ {1, 2, 3}) from the leg midpoint, and S’_k1, S’_k2, … S’_kn, … S’_k(m−1) up from the zero voltage node. The DC-bus capacitors are also numbered up from the zero voltage point. Each semiconductor and DC-bus capacitor index is associated with the respective voltage level.

The switching strategy for an m level NPC converter ensures that the upper leg switches [S_k1 S_k2 … S_kn … S_k(m−1)] and the corresponding ones on the lower side [S’_k1 S’_k2 … S’_kn … S’_k(m−1)] are always in complementary states. Consequently, if S_kn = 1, then S’_kn must be equal to 0, where S_kn = 1 means that the specified switch is ON, and S_kn = 0 shows that the switch is OFF.

2.1. Converter Generalized State Space Model

For each NPC leg, the output voltage variables u_k (u_Rk or u_Vk for the R-side converter and V-side converter, respectively) are defined from the k leg midpoint to zero voltage. The output voltage can be written in terms of the logical state of the leg switches S_kn and DC-bus capacitor voltages, as in (1), where, $u_{C_n}$ is the voltage of the n^th dc-link capacitor.

$$u_k={\displaystyle \sum _{n=1}^{m-1}{S}_{kn}{u}_{C_n}}$$

(1)

Considering a three phase balanced network, the k phase voltage u_Sk can be related to all leg output voltages u_k and, using (1), expressed as a function of the DC-bus capacitor voltages as (2), where the elements S_Ukn are determined by (3).

$$u_{Sk}={\displaystyle \sum _{n=1}^{m-1}{S}_{Ukn}{u}_{C_n}}$$

(2)

$$S_{Ukn}=\frac{1}{3}\left(2S_{kn}-{\displaystyle \sum _{\begin{array}{l}i=1\\ i\ne n\end{array}}^3{S}_{in}}\right)$$

(3)

The DC-bus n level current i_n can be related to the phase currents i_Sk by (4):

$$i_n={\displaystyle \sum _{k=1}^3{\gamma }_{nk}{i}_{Sk}}$$

(4)

where γ_nk is a time dependent switching variable, written in terms of the k leg switching logical states (5), as follows:

$${\gamma }_{nk}=S_{k1}{S}_{k2}\mathrm{...}{S}_{kn}\left(1-S_{k\left(n+1\right)}\right)\left(1-S_{k\left(n+2\right)}\right)\mathrm{...}\left(1-S_{k\left(m-1\right)}\right)$$

(5)

At each time, the load phase current i_Sk is connected to an n DC-bus level when γ_nk = 1, or to the zero voltage bus when γ_nk = 0.

Each DC-bus n level current capacitor $i_{C_n}$ can be related to the corresponding voltage $u_{C_n}$ by (6):

$$i_{C_n}=C_n\frac{d{u}_{C_n}}{dt}$$

(6)

The above current $i_{C_n}$ can be expressed in terms of the upper capacitor current $i_{C_{(n+1)}}$ and the corresponding DC-bus n level currents from the grid side i_Rn or i_Vn, by (7):

$$i_{C_n}={\displaystyle \sum _{j=n}^{m-1}(i_{Rj}+i_{Vj})}$$

(7)

Using Equations (4), (6), and (7) for both grid sides, the voltage capacitor time derivative is expressed in terms of the phase currents, i_SRk and i_SVk, as it is shown in (8):

$$\frac{d}{dt}\left[\begin{array}{c}{u}_{C_1}\\ u_{C_2}\\ :\\ u_{C_n}\\ :\\ u_{C_{(m-1)}}\end{array}\right]=\left[\begin{array}{ccc}\frac{{\mathrm{\Gamma }}_{R11}}{C_1}& \frac{{\mathrm{\Gamma }}_{R12}}{C_1}& \frac{{\mathrm{\Gamma }}_{R13}}{C_1}\\ \frac{{\mathrm{\Gamma }}_{R21}}{C_2}& \frac{{\mathrm{\Gamma }}_{R22}}{C_2}& \frac{{\mathrm{\Gamma }}_{R23}}{C_2}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{Rn1}}{C_n}& \frac{{\mathrm{\Gamma }}_{Rn2}}{C_n}& \frac{{\mathrm{\Gamma }}_{Rn3}}{C_n}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{R(m-1)1}}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{R(m-1)2}}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{R(m-1)3}}{C_{(m-1)}}\end{array}\right]\left[\begin{array}{c}{i}_{SR1}\\ i_{SR2}\\ i_{SR3}\end{array}\right]+\left[\begin{array}{ccc}\frac{{\mathrm{\Gamma }}_{V11}}{C_1}& \frac{{\mathrm{\Gamma }}_{V12}}{C_1}& \frac{{\mathrm{\Gamma }}_{V13}}{C_1}\\ \frac{{\mathrm{\Gamma }}_{V21}}{C_2}& \frac{{\mathrm{\Gamma }}_{V22}}{C_2}& \frac{{\mathrm{\Gamma }}_{V23}}{C_2}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{Vn1}}{C_n}& \frac{{\mathrm{\Gamma }}_{Vn2}}{C_n}& \frac{{\mathrm{\Gamma }}_{Vn3}}{C_n}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{V(m-1)1}}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{V(m-1)2}}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{V(m-1)3}}{C_{(m-1)}}\end{array}\right]\left[\begin{array}{c}{i}_{SV1}\\ i_{SV2}\\ i_{SV3}\end{array}\right]$$

(8)

where the k column matrix element, ${\mathrm{\Gamma }}_{Rnk}$ or ${\mathrm{\Gamma }}_{Vnk}$ (k leg), is determined using the value of the time dependent switching variable, γ_Rnk or γ_Vnk, in the case of the R or V side, respectively, as (9) and (10):

$${\mathrm{\Gamma }}_{Rnk}={\displaystyle \sum _{i=n}^{m-1}{\gamma }_{Rik}}$$

(9)

$${\mathrm{\Gamma }}_{Vnk}={\displaystyle \sum _{i=n}^{m-1}{\gamma }_{Vik}}$$

(10)

Applying the Concordia transformation [25] to Equations (2) and (8) and considering that zero sequence components are null, the multilevel converter matrix equations in the αβ coordinates are given by (11) and (12), as follows:

$$\left[\begin{array}{c}{u}_{S\alpha }\\ u_{S\beta }\end{array}\right]=\left[\begin{array}{cccccc}{S}_{U1\alpha }& S_{U2\alpha }& \mathrm{...}& S_{Un\alpha }& \mathrm{...}& S_{U(m-1)\alpha }\\ S_{U1\beta }& S_{U2\beta }& \mathrm{...}& S_{Un\beta }& \mathrm{...}& S_{U(m-1)\beta }\end{array}\right]\left[\begin{array}{c}{u}_{C_1}\\ u_{C_2}\\ :\\ u_{C_n}\\ :\\ u_{C_{(m-1)}}\end{array}\right]$$

(11)

$$\frac{d}{dt}\left[\begin{array}{c}{u}_{C_1}\\ u_{C_2}\\ :\\ u_{C_n}\\ :\\ u_{C_{(m-1)}}\end{array}\right]=\left[\begin{array}{cccc}\frac{{\mathrm{\Gamma }}_{R1\alpha }}{C_1}& \frac{{\mathrm{\Gamma }}_{R1\beta }}{C_1}& \frac{{\mathrm{\Gamma }}_{V1\alpha }}{C_1}& \frac{{\mathrm{\Gamma }}_{V1\beta }}{C_1}\\ \frac{{\mathrm{\Gamma }}_{R2\alpha }}{C_2}& \frac{{\mathrm{\Gamma }}_{R2\beta }}{C_2}& \frac{{\mathrm{\Gamma }}_{V2\alpha }}{C_2}& \frac{{\mathrm{\Gamma }}_{V2\beta }}{C_2}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{Rn\alpha }}{C_n}& \frac{{\mathrm{\Gamma }}_{Rn\beta }}{C_n}& \frac{{\mathrm{\Gamma }}_{Vn\alpha }}{C_n}& \frac{{\mathrm{\Gamma }}_{Vn\beta }}{C_n}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ \frac{{\mathrm{\Gamma }}_{R(m-1)\alpha }}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{R(m-1)\beta }}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{V(m-1)\alpha }}{C_{(m-1)}}& \frac{{\mathrm{\Gamma }}_{V(m-1)\beta }}{C_{(m-1)}}\end{array}\right]\left[\begin{array}{c}{i}_{SR\alpha }\\ i_{SR\beta }\\ i_{SV\alpha }\\ i_{SV\beta }\end{array}\right]$$

(12)

where, Г_να, Г_νβ, S_Unα, and S_Unβ are obtained by applying the αβ0 transformation to the Г_n1, Г_n2, Г_n3, and S_Un1, S_Un2, S_Un3 variables.

2.2. Grid Side Interface Modeling

The time derivative of the k phase current of the R-side or V-side converter in αβ coordinates, i_Sαβ, is obtained using (13), where u_Gαβ is the grid voltage, R and L represent the grid connection per phase of resistance and inductance, and u_SRαβ is the converter AC output voltage.

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{S\alpha }\\ i_{S\beta }\end{array}\right]=\left[\begin{array}{cc}-\frac{R}{L}& 0\\ 0& -\frac{R}{L}\end{array}\right]\left[\begin{array}{c}{i}_{S\alpha }\\ i_{S\beta }\end{array}\right]+\left[\begin{array}{cc}\frac{1}{L}& 0\\ 0& \frac{1}{L}\end{array}\right]\left[\begin{array}{c}{u}_{G\alpha }\\ u_{G\beta }\end{array}\right]+\left[\begin{array}{cc}-\frac{1}{L}& 0\\ 0& -\frac{1}{L}\end{array}\right]\left[\begin{array}{c}{u}_{S\alpha }\\ u_{S\beta }\end{array}\right]$$

(13)

3. Backward Euler Stabilized Optimum Control

3.1. Global System Control

The control structure of the NPC back-to-back converter system, shown in Figure 2, uses two controllers, one for each converter side. The R-side NPC controls the R-side AC currents, enforcing the DC-bus voltage u_dc (therefore ensuring energy balancing), and establishing the reactive power injected in the R-side grid. Additionally, it balances the capacitor voltages. The V-side NPC controls the V-side AC currents (establishing the active and reactive power to be delivered to the V-side), and balances the capacitor voltages. The power flow control enforces, via the u_dc bus voltage or directly, both R and V sides sinusoidal AC current references. Each NPC will be provided with one independent vector selection controller.

The R-side converter maintains the DC-bus voltage u_dc at a given reference using a Proportional-Integral (PI) controller. From the u_dc controller output, a reference value for the grid current d component i_SRdref is obtained, enforcing the active power demanded from the R grid. The reactive power reference Q_Rref is used to obtain the grid current q component reference i_SRqref. These current reference values, as well as the grid currents i_SR123 and the capacitor voltages u_C1…u_C4, are the inputs of the backward Euler Stabilized optimum controller, whose output is the three phase vector to be applied by the converter (a b c).

The V-side controller controls the active power P_V and reactive power Q_V on the V-side grid. The reference value of the grid current d component i_SVdref is established from the reference of the active power flow. The reference value of the grid current q component i_SVqref is established from the reactive power reference. The reference currents i_SVdqref, together with the grid currents i_SV123 and capacitor voltages, are the inputs of the backward Euler Stabilized optimum controller vector selection block. This controller also balances the capacitor voltages around their reference values.

3.2. Backward Euler Stabilized Optimum Current Control and Capacitor Voltage Balancing

3.2.1. AC Current Control

Using the stable Euler backward approach [26], the current values in the next time step, $i_{S\alpha {\beta }_{(t_s+T_s)}}$ can be obtained from (14):

$$i_{S\alpha {\beta }_{(t_s+T_s)}}=i_{S\alpha {\beta }_{t_s}}+T_s{\frac{d{i}_{S\alpha \beta }}{dt}|}_{t_s+T_s}$$

(14)

This is an implicit method used to solve stiff differential equations. Under the Lipschitz continuity assumption on the current derivative, it can be shown that if T_s is small enough, the Equation (14) has a unique solution. In addition, the Euler backward method is absolutely stable [26]. The backward Euler method is therefore very useful because its stability region contains the whole left half of the complex plane.

Using (14) and (13), the optimum vector that assures the references tracking in the next time step, $u_{S{\alpha }_{(t_s+T_s)}}$ and $u_{S{\beta }_{(t_s+T_s)}}$ components, denoted $u_{S\alpha {\beta }_{(t_s+T_s)}}$, is computed as (15):

$${\left[\begin{array}{c}{u}_{S\alpha }\\ u_{S\beta }\end{array}\right]}_{t_s+T_s}=-\frac{L+R{T}_s}{T_s}\left[\begin{array}{c}{i}_{S{\alpha }_{(t_s+T_s)}}-i_{S{\alpha }_{t_s}}\\ i_{S{\beta }_{(t_s+T_s)}}-i_{S{\beta }_{t_s}}\end{array}\right]+\left[\begin{array}{cc}-R& 0\\ 0& -R\end{array}\right]{\left[\begin{array}{c}{i}_{S\alpha }\\ i_{S\beta }\end{array}\right]}_{t_s}+{\left[\begin{array}{c}{u}_{G\alpha }\\ u_{G\beta }\end{array}\right]}_{t_s+T_s}$$

(15)

From (15), it is possible to compute the optimum converter voltage vector components V_I = $u_{S\alpha {\beta }_{(t_s+T_s)}}$ needed, so that the i_Sαβ current vector is equal to its reference at the next sampling time $i_{S\alpha {\beta }_{(t_s+T_s)}}$ = $i_{S\alpha \beta ref}$. The optimum vector V_I = [$u_{S{\alpha }_{(t_s+T_s)}}$, $u_{S{\beta }_{(t_s+T_s)}}$]^T is only computed once in each sampling step and is used in the cost functional equations in order to select the best vector to be applied in the converter. Figure 3 shows a diagram of the backward Euler stabilized optimum control principle, where the selected vector is the one that minimizes a weighted distance to the optimum vector.

3.2.2. Voltage Balancing Control

Similar to current control and using the Euler backward approach, each capacitor optimal current $i_{C_n(t_s+T_s)}$ that leads the n^th capacitor voltage $u_{C_n{t}_s}$ towards the reference u_Cref in the next sampling time, $u_{C_n(t_s+T_s)}$ = $u_{C_{n}ref}$, can be estimated using (16) as a discrete time approximation of (6). All the DC-bus capacitors have the same value for their voltage reference u_Cref. For each level, the total DC-bus level currents, $i_{Rn(t_s+T_s)}$ or $i_{Vn(t_s+T_s)}$, are obtained using (17).

$$u_{C_n(t_s+T_s)}=u_{C_n{t}_s}+T_s{\frac{d{u}_{C_n}}{dt}|}_{t_s+T_s}\Rightarrow u_{C_n(t_s+T_s)}=u_{C_n{t}_s}+T_s\frac{i_{C_n(t_s+T_s)}-i_{C_n{t}_s}}{C}\Rightarrow i_{C_n(t_s+T_s)}=\frac{C_n}{T_s}\left(u_{C_n(t_s+T_s)}-u_{C_n{t}_s}\right)$$

(16)

$$i_{RVn(t_s+T_s)}=\frac{i_{C_n(t_s+T_s)}-i_{C_{(n+1)}(t_s+T_s)}}{2}$$

(17)

Therefore, the needed DC-bus currents to be applied in the following time step in order to assure the desired capacitor voltages, can be written as a vector form I_U in (18):

$${\mathrm{I}}_{\mathrm{U}}={\left[\begin{array}{cccccc}{i}_{(m-1)(t_s+T_s)}& \mathrm{..}& i_{n(t_s+T_s)}& \mathrm{..}& i_{1(t_s+T_s)}& i_{0(t_s+T_s)}\end{array}\right]}^T$$

(18)

The NPC converter available capacitor current vectors ${\mathrm{I}}_{{\mathrm{V}}_{\mathrm{i}}}$ can be computed using Equation (19). ${\mathrm{I}}_{{\mathrm{V}}_{\mathrm{i}}}$ is computed for each converter voltage vector V_i (u_Sαi, u_Sβi), considering that the phase currents will approximately follow their references in the next sampling time. Equation (19) is applied separately to both converter sides.

$${\mathrm{I}}_{{\mathrm{V}}_{\mathrm{i}}}={\left[{\gamma }_{nk}\right]}_{{\mathrm{V}}_{\mathrm{i}}}{\left[\begin{array}{ccc}{i}_{S1ref}& i_{S2ref}& i_{S3ref}\end{array}\right]}^T$$

(19)

3.2.3. Cost Functional and Vector Selection

The vector selection strategy, applied to both converters independently, minimizes a cost functional (20), relating the weighted distances to the optimum vectors, where W_I(i_Sk), and $W_U(u_{C_n})$ are the weights of errors $e_{U_{V_i}}$ and $e_{I_{V_i}}$ between the references and the values obtained from the application of each NPC vector V_i, respectively.

$$f_C({\mathrm{V}}_{\mathrm{i}})=\sqrt{W_I(i_{Sk})e_{U_{V_i}}^2+W_U(u_{C_n})e_{I_{V_i}}^2}$$

(20)

In (20), the vector error $e_{U_{Vi}}$ is given by (21) and evaluates the distance between the current control optimal-vector V_I ($u_{\mathrm{S}{\alpha }_{(t_s+T_s)}}$, $u_{\mathrm{S}{\beta }_{(t_s+T_s)}}$), and the i^st NPC available vector V_i = [$u_{\mathrm{S}{\alpha }_i}$, $u_{\mathrm{S}{\beta }_i}$]. It gives the information of the optimal-vector V_I deviation from the possible vector V_i.

$$e_{U_{V_i}}=\sqrt{{(u_{\mathrm{S}{\alpha }_{(t_s+T_s)}}-u_{\mathrm{S}{\alpha }_i})}^2+{(u_{\mathrm{S}{\beta }_{(t_s+T_s)}}-u_{\mathrm{S}{\beta }_i})}^2}$$

(21)

Moreover, the error $e_{I_{V_i}}$, given by (22), is the converter i^st DC-bus current vector ${\mathrm{I}}_{{\mathrm{V}}_{\mathrm{i}}}$ deviation from the optimal current vector I_U, which is necessary to balance the capacitor voltages. From (18) and (19):

$$e_{I_{V_i}}=\sqrt{{\displaystyle \sum _{n=1}^4{\left({\mathrm{I}}_{{\mathrm{U}}_n}-{\mathrm{I}}_{{\mathrm{V}}_{\mathrm{i}n}}\right)}^2}}$$

(22)

The phase current control is further associated with the weight W_I(i_Sk) of the cost functional (20) given in (23), showing that it depends on the current tracking error. In (23), ρ_I is a constant for all possible vectors and is used to match current error units, which are weighted with voltage error units.

$$W_I(i_{Sk})={\rho }_I\left({\left(i_{\alpha ref}-i_{{\alpha }_{t_s}}\right)}^2+{\left(i_{\beta ref}-i_{{\beta }_{t_s}}\right)}^2\right)$$

(23)

If only AC current control was required, a constant weight W_I(i_Sk) in (20) would be enough. However, since it is also necessary to balance the capacitor voltages, it is better to consider a quadratic form (23) of W_I(i_Sk) in the cost functional, in order to give greater weight to the current error when bigger tracking errors occur.

The DC capacitor voltage balance is not the main purpose of NPC converter control, but it is nevertheless an essential task to enable the NPC correct operation. Thus, in the cost functional (20), the weight $W_U(u_{C_n})$ imposes the need to balance the capacitor voltages. It is given by (24) as a quadratic function of the capacitors’ voltage tracking errors sum, where ρ_C is considered to be a constant value.

$$W_U(u_{C_n})={\rho }_C{\left({\displaystyle \sum _{n=1}^4\left|u_{Cref}-u_{C_n}\right|}\right)}^2$$

(24)

The variable weighting strategy, W_I(i_Sk), and $W_U(u_{C_n})$, give greater attention, either to the current control or to DC-bus voltages balancing control as a function of tracking errors, without needing to compute the controlled variable values for every possible converter vector. This flexibility allows covering a larger range of NPC operating conditions.

The cost functional (20) is calculated for each NPC possible vector V_i, including the redundant vectors. The selected vector is the one that scores the minimum value for the cost functional f_C(V_i).

4. Simulation and Experimental Results

The proposed system simulations and experimental results, shown in the following points, were obtained using a 230 V ac/600 V dc/230 V ac five level NPC back-to-back prototype, shown in Figure 4. This prototype uses 48 IGBTs (Semikron Elektronik Gmbh & Co., Nuremberg, Germany) as controlled power semiconductors. Both five level NPC converters are controlled using just one Power PC-based board (DS1103 from dSPACE GmbH, Paderborn, Germany) with a 32 μs sampling time, which performs sampling and calculations, and outputs semiconductor signals. The system parameters are presented in

Table 1. System parameters.

Symbol	Description	Value
C1, C2, C3, C4	DC-bus capacitors	4.7 mF
fR, fV	Fundamental grid frequencies	50 Hz
L	Coupling inductors	8 mH
R	Coupling inductors resistance	0.1 Ω
Ts	Sampling time	32 μs
udc	DC-bus voltage	600 V
uGR, uGV	AC grid voltages	230 V
ρC	Capacitors voltage error weights	5
ρi	Current error weights	1

.

4.1. Current Control

Table 2. Operation conditions of Figure 5.

Figure	uGR	iSRq	udc	iSVd	iSVq	uGV1
5	230 V	0	600 V	−5 A	0	230 V

presents the steady state operation conditions used in the experimental result shown in Figure 5. This figure shows the phase current i_SV1 experimental result and the respective frequency spectrum. From Figure 5, it is possible to see that the output phase currents exhibit the fundamental component at 50 Hz and also a spread spectrum with a maximum frequency around 5 kHz. This maximum frequency is well above each semiconductor switching frequency, since the output switching frequency is the contribution of the eight IGBTs of each one of the three converter legs.

Table 3. Operation conditions of Figure 6 and Figure 7.

Figure	uGR	iSRq	udc	iSVd	iSVq	uGV1
6	230 V	0	600 V	Step: 5 A to −5 A	0	230 V
7	230 V	0	600 V	−4A	Step: 5 A to −5 A	230 V

presents the operation conditions used to obtain the simulation results of Figure 6a and Figure 7a, and the corresponding experimental results shown in Figure 6b and Figure 7b. These figures show the phase current i_SV1 control during a step in the i_SVd and i_SVq reference, respectively.

From Figure 6 and Figure 7, it can be seen that the backward Euler stabilized control strategy accurately tracks the current references in a steady state or during a step in the i_SVd or i_SVq reference, respectively. The measured current ripple was less than 0.25 A in 5 A (<5%).

The time evolution of the capacitor voltages during the step transitions of Figure 6 and Figure 7 are presented in Figure 8a,b respectively. From Figure 8, it can be seen that the deviation of the capacitor voltages, u_C1…4, is around 1.5 V over 150 V (1%).

The proposed control strategy achieves high output modulation indexes, $m_o={\widehat{u}}_{GV}/u_{dc}$, even in the most difficult operation conditions for a NPC back-to-back connection with an active load, that is, with no active power exchange [4].

Table 4. Operation conditions of Figure 9.

Figure	uGR	iSRq	udc	iSVd	iSVq	uGV1
9	230 V	0	600 V	0	Step: 5 A to −5 A	230 V

shows the operation conditions of the simulation results presented in Figure 9, and displays the 1st harmonic u_GV12-1h of the output line-to-line voltage.

The simulation results of Figure 9 were obtained using a modulation index around m_o = 0.93. This result clearly shows the limits extension of the proposed control strategy, when compared with redundant vector-based strategies as sinusoidal pulse width modulation (SPWM) or space vector modulation (SVM) [3,4] (the theoretical maximum output modulation index is around 0.6).

4.2. DC-bus Voltage Control and Capacitors Voltage Balancing

DC-bus voltage control robustness is verified by applying a grid side voltage sag perturbation of a 25% nominal voltage, for which the operation conditions are presented in

Table 5. Operation conditions of Figure 10.

Figure	uGR1	iSRq	udc	iSVd	iSVq	uGV1
10	230 V|170 V|230 V	0	600 V	−5 A	0	230 V

and the results are shown in Figure 10. It can be seen that the DC-bus voltage remains almost constant through a sag perturbation on the main grid voltage. The maximum voltage disturbance measured was 50 V in 600 V (<9%).

The voltage balancing of the capacitors is tested by restarting the voltage balancing algorithm, which means that ρ_C ≠ 0, after a time interval without considering it (ρ_C = 0). The operating conditions are presented in

Table 6. Operation conditions of Figure 11.

Figure	ρC	uGR1	iSRq	udc	iSVd	iSVq	uGV1
11	15|0|15	230 V	0	600 V	−2.5 A	0	230 V

and the results are shown in Figure 11. From Figure 11, it can be seen that the four capacitor voltages u_C1…4 deviate from the reference during the time interval without voltage balancing. After restarting the voltage balancing algorithm, the backward Euler stabilized control strategy has the capability to rapidly restore the capacitor voltage balance.

4.3. Power Flow Control

Several conditions can be imposed in order to test power flow control. Figure 12 and Figure 13 show the i_SVd reference, phase current, and u_dc voltage for two different power flow conditions, presented in

Table 7. Operation conditions of Figure 12 and Figure 13.

Figure	uGR	iSRq	udc	iSVd	iSVq	uGV1
11	230 V	0	600 V	Setp: 5 A to −5 A	0	230 V
12	230 V	0	600 V	Setp: −5 A to 5 A	0	230 V

.

From Figure 12 and Figure 13, it is possible to see the u_dc recovery after a negative or positive step in active power flow, respectively. The experimental results obtained attest the good performance of the proposed control strategy.

From [19,21,24], the comparison presented in

Table 8. Backward Euler stabilized controller compared with existing control methods.

Method	Proportional Integral	Proportional Integral-Resonant	Sliding Mode	Predictive Optimum	Fast Predictive	Backward Euler
THD of AC currents	5.8%	7.5%	7%	4.6%	1.5%	<1.5%
DC-bus voltage unbalance	8%	-	-	-	1%	1%

can be obtained. Although the results are not directly comparable, since some of them refer to three-level converters, while the herein results are for five-level converters, it can be said that the backward Euler-based controller shows results which are better than PI controllers and are comparable to the best results obtained by advanced controllers.

5. Conclusions

The proposed backward Euler stabilized control strategy based on a generalized model of a five level NPC back-to-back converter, is able to control both the converter AC currents and to balance the four capacitor voltages.

From the active and reactive power flow of the convertors, in addition to the DC-bus voltage references, the control strategy computes, using the stable backward Euler approach, the optimum voltage or current vectors required to reach the references in the next time step. The selection of the converter output voltage vector is done by minimizing a variable weight cost functional within a sampling period. The minimum value of the cost functional gives the converter output voltage vector. The modified cost functional with variable weight allows converter control in a wide range of operating conditions.

Simulation and experimental results were obtained using a 230 V ac/600 V dc/230 V ac five level NPC back-to-back prototype. Both NPC converters are controlled with one Power PC-based board (DS1103) with a 32 µs sampling time.

The results demonstrate the feasibility and robustness of the proposed control strategy, achieving a very good compromise covering the main tasks: AC current tracking errors were lower than 5% and the DC-bus capacitor voltage balancing was within 10%. When compared with redundant vector-based control techniques, the proposed control strategy shows the extension of the modulation index, from 0.6 to 0.93.