A Novel Switched-Capacitor Multilevel Inverter Topology for Energy Storage and Smart Grid Applications

Abstract

The recent advancement in the application of the internet of things in the smart grid has led to an industrial revolution in the power industry. The Industry 4.0 revolution has already set in, allowing computers to interact for an efficient and intelligent approach in solving smart grid issues. multilevel inverters (MLIs) are an integral part of the smart grid system for integrating the distributed generation sources and storage energy systems into the smart grid. It attracted attention in industrial applications as they can handle high power and high voltage with an inherent feature of superior output voltage waveform quality. Moreover, its variant, the switched-capacitor MLI (SCMLI), has the added benefit of lesser DC supply requirement. In this paper, a switched-capacitor multilevel inverter topology has been proposed, which can operate in symmetric and asymmetric mode. The proposed SCMLI generate thirteen and thirty-one level output voltages for symmetric and asymmetric selection of DC voltage sources, respectively. The proposed SCMLI has a smaller number of switching devices for a given output voltage level as compared to other recently proposed topologies. A thorough comparison is presented with the recently proposed topologies on several parameters, including cost function. To validate the proposed topology, symmetric and asymmetric cases were simulated using Matlab^® 2018a and the results were verified using an experimental hardware setup.

1. Introduction

The increasing cost of limited fossil fuel resources has led to a massive investment of economic and human resources to develop its substitute in the form of a cheaper and cleaner energy resource. Recently, researchers and industries have seriously looked upon solar and wind energy resources to meet future energy demand. The negligible environmental effects and economic benefits are the advantages associated with using these sources. Due to the advancements in power electronics technology, highly efficient converters have been developed for energy conversion applications. The AC drives and grid applications require power inverters. While a conventional two-level inverter has been used in industrial use, it has some serious shortcomings in power quality [1]. As a result, there is a competition in the market to develop more efficient high-voltage and high-current handling inverters with superior power quality to meet the guidelines of IEEE 1547 standards of the smart grid system. The smart grid can be described as a powerful grid connecting the consumers with applications and integrating the distributed power generation system into an optimized centralized power system [2]. Physical attacks, cyber-attacks, or natural disasters are significant threats to smart grid deployment, which can even lead to blackouts, privacy breaches, infrastructural failures, operating personnel safety issues, or energy theft [3]. Multilevel inverters (MLIs) garnered a lot of concern owing to their output waveforms of high-quality along with low $\frac{dV}{dt}$ stress. Low total harmonic distortion (THD) of the output waveform is obtained by increasing the number of output voltage levels of the inverters, which results in the reduction of the size of output filters. MLIs have several DC voltage supplies, capacitors, power diodes, and switches along with driver circuits to obtain proper output voltage using a suitable switching pattern [1,4,5,6,7,8].

Flying-capacitor, diode-clamped, and cascaded MLIs are topologies that are conventional as well as well-recognized. But there are certain shortcomings of these conventional inverters. The limitations of flying capacitor and diode-clamped MLIs are that they have a high number of capacitors and diodes for a higher-level generation, while cascaded H-bridge inverters have many isolated DC supplies and a large number of power switches for high-power applications. Additionally, external circuits are a basic necessity for maintaining the capacitor voltage [9,10,11,12].

Consequently, newer MLI topologies that offer to overcome the shortcomings of these traditional MLIs were reported in the literature. MLIs using symmetrical DC supply to obtain multilevel staircase sinusoidal voltage waveforms were presented in [13,14,15,16,17]. The converters mentioned above posed a combined setup of power semiconductor devices and the supply of voltage. A step-up sinusoidal output voltage may be obtained by the use of an applicable switching pattern. It was evident from the outcomes that MLI’s performance improved as we increased the voltage level tally, but it led to more circuit components and complexity in control [18,19,20]. MLIs with asymmetrical DC voltage supply, where the number of levels was increased manifold with fewer circuit elements, were reported in [21,22,23]. However, the use of isolated DC supply was still a drawback here, leading to a cost increment.

Switched-capacitor MLIs (SCMLIs) came into the picture for a reduction in the estimate of separated DC voltage supply [24]. A lot of work was reported in the area of SCMLI. Researchers are coming with different switched-capacitor MLI topologies with self-balancing forms and self-voltage boosting capabilities, as was reported in [4,25,26,27,28]. SCMLI application areas include high-frequency AC (HFAC) system of distribution of power [29,30], HFAC microgrids [31], X-rays, UPS, LASERs, etc. In [32], SCMLI, with a cascaded structure having a boost converter (SC-based) connected with a two-level inverter, was proposed. The boost converter generated the multilevel step voltage, and the inverter was used to generate polarity. As in [32], authors of [33] proposed a novel SCMLI having an Switched Capacitor-frontend and H-bridge backend where the SC-frontend was used to increase output levels by converting series and parallel connections. In [34], a step-up multilevel converter topology was proposed for both asymmetric as well as symmetric types of DC supplies of voltage. Its main feature was the inherent voltage balancing capability of its capacitors. A new design of converter of switched-capacitor type was proposed in [35], where the authors used only one DC voltage supply. As a result, the total standing voltage (TSV) and maximum switch-stress voltage were reduced. Both symmetric and asymmetric topologies were presented in [36] with a reduced number of switch counts. A converter (DC to AC) with an ability to increase voltage along with voltage self-balancing was shown in [37]. Peak inverse voltage (PIV) and TSV were lower as it had one DC supply and no H-bridge. Most of the above topologies suffered from capacitor self-voltage balancing problems or high-voltage stress on switches.

This study proposes a topology for single-phase switched-capacitor multilevel inverter (SCMLI) with some novel characteristics, which operates in both symmetrical and asymmetrical configuration types to generate a 13- and 31-level output, respectively. The study aims to reduce switch count, low total standing voltage, and low individual voltage stress of the circuit components for higher output levels and capacitor self-voltage balancing capability. The only issue is its slightly higher THD due to capacitor charging and discharging. The paper is structured in the following manner. The proposed topology for symmetric and asymmetric configuration with its working is given in Section 2. Section 3 explains the modulation technique used here, i.e., nearest level control. A comparative analysis of SCMLI proposed here with other topologies presented recently is mentioned in Section 4. Power loss analysis with efficiency calculation using PLECS software is given in Section 5. Experimental and simulation results for the proposed topology is given in Section 6. Finally, the concluding remarks are mentioned in Section 7.

2. Proposed Topology

The description of the proposed SCMLI topology is shown in Figure 1. The circuit had eight switches (T₁–T₈) of unidirectional nature, three DC voltage sources, two switches (S₁ and S₂) that are bidirectional, and four capacitors. The switch pairs T₃–T₄ and T₅–T₆ were complementary, thus avoiding short-circuiting problems in the DC voltage supply. Similar topology works for asymmetrical and symmetrical configuration based on the intensity of V₁, V₂, and V₃, DC voltage supplies.

2.1. Symmetrical Configuration

For this configuration, all the sources (V₁, V₂, and V₃) of DC voltage have the same magnitude, i.e., V₁ = V₂ = V₃ = $V_{dc}$. Therefore, the proposed topology with symmetric configuration can generate 13 levels at the output (six positives, six negative, and zero). All the switching states of this configuration are shown in

Table 1. Switching states for the symmetrical configuration.

S1	S2	T1	T2	T3	T4	T5	T6	T7	T8	Vo
OFF	OFF	ON	OFF	ON	OFF	ON	OFF	ON	OFF	0
ON	OFF	OFF	OFF	ON	OFF	ON	OFF	ON	OFF	0.5$V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	ON	OFF	ON	OFF	$V_{dc}$
ON	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF	ON	1.5$V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	OFF	ON	OFF	ON	2$V_{dc}$
OFF	ON	OFF	ON	ON	OFF	OFF	ON	OFF	OFF	2.5$V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	OFF	ON	ON	OFF	3$V_{dc}$
OFF	OFF	OFF	ON	OFF	ON	OFF	ON	OFF	ON	0
ON	OFF	OFF	OFF	OFF	ON	OFF	ON	OFF	ON	$-0.5V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	OFF	ON	OFF	ON	$-V_{dc}$
ON	OFF	OFF	OFF	OFF	ON	ON	OFF	ON	OFF	$-1.5V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	ON	OFF	ON	OFF	$-2V_{dc}$
OFF	ON	ON	OFF	OFF	ON	ON	OFF	OFF	OFF	$-2.5V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	ON	OFF	OFF	ON	$-3V_{dc}$

. The switching diagrams for all the thirteen switching states are shown in Figure 2. In the switching description, the undotted line indicates the active circuit having current flow. The voltage across C₁ and C₂ will be half of the voltage V₁, and voltage across C₃ and C₄ will be half of the voltage V₃. Total standing voltage (TSV) is a parameter that was essential for inverter configuration selection. It is the sum of the absolute maximum blocking voltages through each switch. Also, there will be the same voltage stress for complementary switches. Therefore, according to the basic circuit given in Figure 1, voltage stresses across the switches:

Switches, T₁ and T₂,

$$V_{S1}=V_{S2}=V_1=V_{dc}$$

(1)

Complementary switches, T₃ and T₄,

$$V_{S3}=V_{S4}=V_1+V_2=2V_{dc}$$

(2)

Complementary switches, T₅ and T₆,

$$V_{S5}=V_{S6}=V_2+V_3=2V_{dc}$$

(3)

Switches,

$$V_{S7}=V_{S8}=V_3=V_{dc}$$

(4)

For bidirectional switches, each unidirectional switch of S₁ and S₂ had to block the voltage of both switches of bidirectional switch S₁,

$$V_{S1}\prime =V_1=V_{dc}$$

(5)

Both switches of bidirectional switch S2,

$$V_{S2}^{\prime }=V_3=V_{dc}$$

(6)

Therefore,

$$TSV=V_{S1}+V_{S2}+V_{S3}+V_{S4}+V_{S5}+V_{S6}+V_{S7}+V_{S8}+2V_{S1}^{\prime }+2V_{S2}^{\prime }$$

(7)

(2 is for the 2 bidirectional switches S₁ and S₂).

Using Equations (1) to (6) in Equation (7), we have

$$\begin{array}{cc}\hfill TSV& =2\left(V_{S1}+V_{S3}+V_{S5}+V_{S7}+V_{S1}\prime +V_{S2}\prime \right)\hfill \\ \hfill & =2\left(V_{dc}+2V_{dc}+2V_{dc}+V_{dc}+V_{dc}+V_{dc}\right)\hfill \\ \hfill & =16V_{dc}\hfill \end{array}$$

(8)

For per unit TSV, the TSV is divided by the peak of the output voltage. Therefore,

$$TS{V}_{p.u}=\frac{16V_{dc}}{6V_{dc}}=2.67$$

(9)

2.2. Asymmetrical Configuration

The same topology can generate more output levels using asymmetrical configuration. However, determining the appropriate ratio of the voltage sources to have maximum output levels was essential for lowering down the THD. After analyzing the combinations for the three DC voltage sources, the one with V₁ = 12$V_{dc}$, V₂ = $V_{dc}$, and V₃ = 2 $V_{dc}$ gave the highest number of output levels. Thirty-one output levels can be obtained using this combination of supply of DC voltage for the same topology.

Table 2. Switching states for the asymmetrical configuration.

S1	S2	T1	T2	T3	T4	T5	T6	T7	T8	Vo
OFF	OFF	OFF	ON	OFF	ON	OFF	ON	OFF	ON	0
OFF	OFF	ON	OFF	ON	OFF	OFF	ON	OFF	ON	$V_{dc}$
OFF	OFF	OFF	ON	OFF	ON	OFF	ON	ON	OFF	$2V_{dc}$
OFF	OFF	ON	OFF	ON	OFF	OFF	ON	ON	OFF	$3V_{dc}$
ON	OFF	OFF	OFF	ON	OFF	ON	OFF	OFF	ON	$4V_{dc}$
ON	ON	OFF	OFF	ON	OFF	ON	OFF	OFF	OFF	$5V_{dc}$
ON	OFF	OFF	OFF	ON	OFF	ON	OFF	ON	OFF	$6V_{dc}$
ON	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF	ON	$7V_{dc}$
ON	ON	OFF	OFF	ON	OFF	OFF	ON	OFF	OFF	$8V_{dc}$
ON	OFF	OFF	OFF	ON	OFF	OFF	ON	ON	OFF	$9V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	ON	OFF	OFF	ON	$10V_{dc}$
OFF	ON	OFF	ON	ON	OFF	ON	OFF	OFF	OFF	$11V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	ON	OFF	ON	OFF	$12V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	OFF	ON	OFF	ON	$13V_{dc}$
OFF	ON	OFF	ON	ON	OFF	OFF	ON	OFF	OFF	$14V_{dc}$
OFF	OFF	OFF	ON	ON	OFF	OFF	ON	ON	OFF	$15V_{dc}$
OFF	OFF	ON	OFF	ON	OFF	ON	OFF	ON	OFF	0
OFF	OFF	OFF	ON	OFF	ON	ON	OFF	ON	OFF	$-V_{dc}$
OFF	OFF	ON	OFF	ON	OFF	ON	OFF	OFF	ON	$-2V_{dc}$
OFF	OFF	OFF	ON	OFF	ON	ON	OFF	OFF	ON	$-3V_{dc}$
ON	OFF	OFF	OFF	OFF	ON	OFF	ON	ON	OFF	$-4V_{dc}$
ON	ON	OFF	OFF	OFF	ON	OFF	ON	OFF	OFF	$-5V_{dc}$
ON	OFF	OFF	OFF	OFF	ON	OFF	ON	OFF	ON	$-6V_{dc}$
ON	OFF	OFF	OFF	OFF	ON	ON	OFF	ON	OFF	$-7V_{dc}$
ON	ON	OFF	OFF	OFF	ON	ON	OFF	OFF	OFF	$-8V_{dc}$
ON	OFF	OFF	OFF	OFF	ON	ON	OFF	OFF	ON	$-9V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	OFF	ON	ON	OFF	$-10V_{dc}$
OFF	ON	ON	OFF	OFF	ON	OFF	ON	OFF	OFF	$-11V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	OFF	ON	OFF	ON	$-12V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	ON	OFF	ON	OFF	$-13V_{dc}$
OFF	ON	ON	OFF	OFF	ON	ON	OFF	OFF	OFF	$-14V_{dc}$
OFF	OFF	ON	OFF	OFF	ON	ON	OFF	OFF	ON	$-15V_{dc}$

shows distinct states of switching for the configuration. The switching diagrams for some of the 31 switching states are shown in Figure 3. Voltage stresses across the switches:

$$V_{S1}=V_{S2}=V_1=12V_{dc}$$

(10)

$$V_{S1}=V_{S2}=V_1=12V_{dc}$$

(11)

$$V_{S5}=V_{S6}=V_2+V_3=3V_{dc}$$

(12)

$$V_{S7}=V_{S8}=V_3=2V_{dc}$$

(13)

For bidirectional switches, each unidirectional switch of S₁ has to block the voltage of

$$V_{S1}\prime =V_1=12V_{dc}$$

(14)

and, each unidirectional switch of S₂ has to block the voltage of

$$V_{S2}^{\prime }=V_3=2V_{dc}$$

(15)

Trefore,

$$TSV=2\left(V_{S1}+V_{S3}+V_{S5}+V_{S7}+V_{S1}\prime +V_{S2}\prime \right)$$

(16)

Using Equations (10) to (15) in Equation (16), we have

$$TSV=2\left(12V_{dc}+13V_{dc}+3V_{dc}+2V_{dc}+12V_{dc}+2V_{dc}\right)=88V_{dc}$$

(17)

For per unit TSV,

$$TS{V}_{p.u}=\frac{88V_{dc}}{15V_{dc}}=5.87$$

(18)

3. Nearest Level Control

Modulation techniques are of great importance for multilevel inverters as they influence harmonics, control dynamics, switching loss, filter size, etc. [38]. Traditional modulation methods have the standard features of high switching loss, switching harmonics, increased switching frequency, and high complexity as submodules increases, etc. Nearest level control (NLC) has the advantage of having more voltage levels as it approximates the reference voltage with the nearest voltage level, which results in fundamental switching frequency having low switching losses [39]. This method was useful for higher output voltage applications as the switching losses and low-order harmonics were minimized. This method can operate at 50 Hz and is extendable to N-Levels. This method was more straightforward, and the round-off method was used for the calculation of normalized value. The amplified signal was obtained by multiplying the reference signal by A, as given in Figure 4b. After comparing the signals obtained with constants, the pulses thus obtained were combined according to logic for switching to get the required pulses of switching. NLC was applied for controlling the voltage at the output of the proposed multilevel inverter for both symmetric and asymmetric configurations. The working principle of the NLC is mentioned as part of Figure 4a,b. There was a variation in the reference voltage (Vref) to change the modulation index (MI), which is given as:

$$\mathrm{Modulation}\mathrm{Index}=\frac{V_{ref}}{V_{out}}=\frac{2V_{ref}}{\left(\mathrm{N}-1\right)V_{dc}}$$

(19)

4. Comparative Analysis

In this section, the SCMLI proposed is compared with the formerly presented SCMLIs. A thorough comparison was carried out considering $TS{V}_{p.u}$; the number of components required; cost function (CF), which is taken from [7]; etc. Estimation of the overall cost of each topology was done using the ratio of cost function over the output voltage levels.

$$CF=\left(N_{sw}+N_{dr}+N_{cap}+N_{di}+\gamma TS{V}_{pu}\right)\times N_{Vdc}$$

(20)

where, $N_{sw}$ represents the switch count, $N_{dr}$ represents gate drivers’ count, $N_{cap}$ represents the number of capacitors, $N_{di}$ represents the diode count, $N_{Vdc}$ represents the number of dc voltage sources, γ represents weight coefficient, $TS{V}_{pu}$ represents total standing voltage.

Different components required, such as gate drivers, switches, capacitors, diodes, and isolated sources of DC voltage and total standing voltage per unit, were suitably considered for the estimation of the cost function. For selecting proper switches for any topology, the TSV of the structure will be necessary. A weight coefficient (γ) was multiplied with $TS{V}_{pu}$ to precisely apply its impact on the proposed CF. γ greater than or less than one selects which among TSV and the number of switches was the most relevant quantity. The comparative analysis is done in the following two sections.

4.1. Comparision with a Single Source and Symmetric Topologies

Here, the general features of the proposed 13-level symmetric topology are compared with some recent topologies of SCMLIs and are summarized in

Table 3. Comparison of the proposed symmetric topology with different single source and symmetric topologies of similar voltage levels.

SCMLI Presented in	${\mathit{N}}_{\mathit{l}\mathit{e}\mathit{v}\mathit{e}\mathit{l}}$	${\mathit{N}}_{\mathit{s}\mathit{w}}$	${\mathit{N}}_{\mathit{V}\mathit{d}\mathit{c}}$	${\mathit{N}}_{\mathit{d}\mathit{r}}$	${\mathit{N}}_{\mathit{c}\mathit{a}\mathit{p}}$	${\mathit{N}}_{\mathit{d}\mathit{i}}$	$\mathit{T}\mathit{S}{\mathit{V}}_{\mathit{p}\mathit{u}}$	$\frac{\mathit{C}.\mathit{F}}{{\mathit{N}}_{\mathit{l}\mathit{e}\mathit{v}\mathit{e}\mathit{l}}}$
								γ = 0.5	γ = 1.5
[7] sym	9	10	1	8	2	1	6.00	2.70	3.33
[7] asym	17	18	2	14	4	2	6.00	4.82	5.52
[33]	13	18	3	18	3	3	5.00	10.27	11.42
[34]	13	14	2	14	4	4	5.30	5.95	6.76
[35]	13	16	2	16	4	2	5.60	6.27	7.13
[36]	13	14	6	14	0	0	4.70	13.11	16.20
[37]	13	29	1	29	5	0	4.83	5.03	5.40
[40]	9	8	1	8	4	4	4.00	2.90	3.33
[41]	17	14	4	14	4	8	4.25	9.91	10.91
[42]	17	10	2	10	2	4	5.50	3.38	4.03
Proposed multilevel inverters (MLI)	13	12	3	10	4	0	2.17	6.08	6.75

. One of the notable merits of the proposed structure was its lowest $TS{V}_{pu}$ among the papers presented in [7,33,34,35,36,37,40,41,42]. It also had the lowest number of switch count among its 13-level counterparts. Value of $\frac{C.F}{N_{level}}$ was also low for both conditions of γ = 0.5 and γ = 1.5 for 13 levels. Value of $\frac{C.F}{N_{level}}$ was very high in [33,36] as compared to the proposed topology. Structures in [7,40] had a lower value of $\frac{C.F}{N_{level}}$ than the proposed one as they have a single DC source, and their TSV was higher.

4.2. Comparison with a Symmetric Topologies

Asymmetric topologies have come into the picture for obtaining output levels in higher numbers. The proposed asymmetric topology was compared with recent SCMLIs of similar voltage levels comprehensively, which is shown in

Table 4. Comparison of the proposed asymmetric topology with asymmetric topologies of similar voltage levels.

SCMLI Presented in	${\mathit{N}}_{\mathit{l}\mathit{e}\mathit{v}\mathit{e}\mathit{l}}$	${\mathit{N}}_{\mathit{s}\mathit{w}}$	${\mathit{N}}_{\mathit{V}\mathit{d}\mathit{c}}$	${\mathit{N}}_{\mathit{d}\mathit{r}}$	${\mathit{N}}_{\mathit{c}\mathit{a}\mathit{p}}$	${\mathit{N}}_{\mathit{d}\mathit{i}}$	$\mathit{T}\mathit{S}{\mathit{V}}_{\mathit{p}\mathit{u}}$	$\frac{\mathit{C}.\mathit{F}}{{\mathit{N}}_{\mathit{l}\mathit{e}\mathit{v}\mathit{e}\mathit{l}}}$
								γ = 0.5	γ = 1.5
[34]	31	14	2	14	4	4	5.33	2.49	2.83
[35]	31	16	2	16	4	2	5.67	2.63	3.00
[42]	25	12	2	12	2	2	5.00	2.44	2.84
[43]	31	14	6	10	0	0	5.33	5.16	6.19
[23]	25	12	4	10	0	0	5.00	3.92	4.72
[34]	49	18	2	18	6	6	5.50	2.07	2.30
[44]	25	14	2	10	4	0	5.83	2.47	2.94
Proposed MLI	31	12	3	10	4	0	5.87	2.80	3.37

. For higher levels (here 31), this topology did not have a marked difference in the different properties given in the table. The value of $\frac{C.F}{N_{level}}$ in the proposed MLI wass less than the structures presented in [23,43]. The number of drivers and switch count used here was lowest. Most importantly, the same topology was used for symmetric as well as asymmetric design in the topology proposed.

5. Power Loss Analysis

Losses in terms of power and efficiency in the overall sense of suggested topology were estimated by using PLECS software. Conduction and switching losses for all the switches and losses across the capacitors were calculated precisely using thermal modeling in the software. IGBT switch IGA30N60H3 manufactured by Infineon was taken for this analysis. The turn ON, turn OFF, and conduction loss model of the IGBT taken is given in Figure 5, respectively. Here three main types of losses were taken into account: switching losses ($P_S$) and conduction losses ($P_C$) of all the semiconductor devices and ripple loss ($P_R$) of the capacitors.

5.1. Switching Losses $({\mathrm{P}}_{\mathrm{S}})$

Switching losses were there at the instant when the switches turn ON or OFF. The following equations can be expressed for the kth switch considering approximation in a linear sense between current and voltage of switches during the period of switching [45]:

Loss of power during switching

$$\begin{array}{c}\mathrm{ON}=P_{S,on,k}=f{{\displaystyle \int }}_0^{t_{on}}v\left(t\right)i\left(t\right)dt\hfill \\ =f\underset{0}{\overset{t_{on}}{{\displaystyle \int }}}\left(\frac{V_{S,k}}{t_{on}}t\right)\left(-\frac{I_k}{t_{on}}\left(t-t_{on}\right)\right)dt=\frac{1}{6}f{V}_{S,k}{I}_k{t}_{on}\hfill \end{array}$$

(21)

Loss of power during switching

$$\begin{array}{c}\mathrm{OFF}=P_{S,off,k}=f{{\displaystyle \int }}_0^{t_{off}}v\left(t\right)i\left(t\right)dt\hfill \\ =f\underset{0}{\overset{t_{off}}{{\displaystyle \int }}}\left(\frac{V_{S,k}}{t_{off}}t\right)\left(-\frac{I_k{}^{\prime }}{t_{off}}\left(t-t_{off}\right)\right)dt=\frac{1}{6}f{V}_{S,k}{I}_k{}^{\prime }{t}_{off}\hfill \end{array}$$

(22)

where $I_k$ and $I_k{}^{\prime }$ denote currents across the kth switch when it was turned ON, and prior to turning it OFF, respectively. f is the frequency of switching and $V_{S,k}$ denotes voltage for the OFF-state of the kth switch. For calculating the loss in switching as total, the ON ($N_{on}$) and the OFF number of switching states ($N_{off}$) for each cycle are multiplied with (21) and (22) following (23):

$$P_S={\displaystyle \sum }_{k=1}^{12}\left({\displaystyle \sum }_{m=1}^{N_{on}}{P}_{S,on,km}+{\displaystyle \sum }_{m=1}^{N_{off}}{P}_{S,off,km}\right)$$

(23)

5.2. Conduction Losses ($P_C$)

The internal resistance of each component, i.e., semiconductor devices and capacitors, had to be addressed to calculate losses in conduction at the condition of steady-state. Each capacitor was assumed to be the same. The results were taken using the PLECS software for a resistive load since the state of resistive loading is said to be the worst-case scenario in the analysis of loss of power for the SCMLIs [45,46].

5.3. Capacitor Ripple Losses ($P_R$)

Ripple losses occured by the difference between the input voltage (V_in) and the voltage across the capacitors (V_Cj(j = 1,2,3,4)), when the capacitors are connected in parallel [46]. It was assumed that the capacitor was fully charged to V_in during the charging state.

The capacitor ripple voltage is taken as:

$$\Delta V_{Cj}=\frac{1}{C_j}\underset{t^{\prime }}{\overset{t}{{\displaystyle \int }}}{i}_{C_j}\left(t\right)dt\mathrm{for}\mathrm{j}=1,2,3,4$$

(24)

Here, $i_{C_j}$ denotes passing current of the jth capacitor. The discharging period is [$t^{\prime }-t$]. Thus, the total ripple loss in the duration of the output waveform cycle is given by (25).

$$P_R=\frac{f}{2}{\displaystyle \sum }_{j=1}^4{C}_j\Delta V_{Cj}{}^2$$

(25)

From (24) and (25), it is evident that ripple loss is inversely proportional to the capacitance. Thus, larger capacitance led to less ripple loss and hence improved efficiency. The efficiency of the overall proposed inverter is given by (26).

$$\eta =\frac{P_o}{P_o+P_S+P_C+P_R}$$

(26)

The efficiency versus output power curve for both symmetrical and asymmetrical configurations is shown in Figure 6 for a resistive load. Maximum efficiency was achieved with about 98.7% along with a 100-watt output power for both the configurations in which capacitor ripple loss had neglected. Capacitor ESR loss (conduction loss due to internal resistance of the capacitors (here 0.1 ohm is taken)) was taken in its place. Power loss distribution among different switches and capacitors are given in Figure 7 for both settings. S₁ and S₂ were the bidirectional switches, as shown in Figure 1. Both switches of the bidirectional switches had the same loss. All the complementary switches also had the same losses as the number of states when they were turned ON and turned OFF for a full cycle.

6. Results and Discussions

Simulation of the suggested topology for asymmetric and the symmetric case was done using ${\mathrm{Matlab}}^{\circledR }$ 2018a and for verifying the results obtained, experimental results were also taken. Both of these results are discussed in the subsequent subsection.

6.1. Simulation Results

For symmetrical configuration, the magnitude of the three DC voltage sources was similar, and for simulation purposes, it was taken to be 100 volts. The resultant voltage at the output had a peak voltage of 300 V with 50-V steps and 13 levels in totality. All four capacitances were considered to be 4700 µF. The current waveform and voltage at the output for Z = 50 Ω +100 mH as the R-L load with varying MI are presented in Figure 8a. The number of levels for voltage at the output was directly proportional to the MI. At MI = 0.5, the output voltage levels were reduced by half, which can be analyzed from Figure 8a. The current waveform and voltage at the output with a load change of Z = 50 Ω +100 mH to Z=25 Ω +100 mH, which are given in Figure 8b–d, show the harmonic analysis of the voltage obtained and the current waveforms for Z = 50 Ω +100 mH, respectively. Voltage and current THD was achieved as 6.36% and 0.56%, respectively. Current THD was lower as the inductive load reduced the high-frequency current components.

For the asymmetrical case, V₁ = 240 V, V₂ = 20 V, and V₃ = 40 V. The resultant output waveform has a peak voltage of 300 Volts with a step size of 20 Volts. Figure 9a shows the current waveform and voltage at the output for Z = 50 Ω +100 mH as the R-L load with varying MI. Figure 9b presents the current waveform and voltage at the output with Z = 50 Ω +100 mH to Z = 25 Ω +100 mH as the change in load. Harmonic analysis for the obtained voltage and current waveforms for Z = 50 Ω +100 mH, as shown in Figure 9c,d, respectively. Voltage and current THD was obtained as 2.63% and 0.16%, respectively.

6.2. Experimental Results

Figure 10 shows that the above results obtained were verified using an experimental prototype for both symmetrical and asymmetrical cases. Toshiba IGBT GT50J325 was taken as the switch, and the dSPACE 1104 controller was used to obtain gating pulses for these switches. Figure 11a,b shows the output voltage and current waveforms for RL load of 200 Ω +100 mH and a resistive load of 120 Ω, respectively, for the symmetrical case. In this case, V₁ = V₂ = V₃ = 80 V was chosen. The thirteen-level output had the peak voltage of 240 V with a step voltage of 40 V. The output waveforms with load change and MI change are given in Figure 11c,d. The load change was from 120 Ω to 60 Ω, and MI change was from 0.33 to 1. The 13-level output is shown in Figure 12a. For the asymmetrical case, V1 = 240 V, V2 =20 V, and V3 = 40 V were taken. Figure 12b shows the output waveform having a load change from no load to 120 Ω to 60 Ω. Figure 12c shows the thirty-one-level output voltage with the maximum voltage of 300 volts having steps of 20 volts. The output waveform for a resistive load of 32 Ω is given in Figure 12d.

7. Conclusions

An innovative SCMLI topology is suggested here. The mentioned topology could operate for symmetrical as well as the asymmetrical case. Apart from lower switch count, TSV was also remarkably lower for the symmetrical case and comparable with other recent topologies in the asymmetrical case. It had the lowest switch count compared to other 13-level topologies presented, as discussed in Section 4.1 and given in Table 3. Its economic aspect was also taken into account using the cost function, and it stands well with other topologies shown in Table 3 and Table 4. Hardware implementation was carried out to verify the simulation results under the condition of varying load and modulation indexes. Thus, the proposed topology is the right candidate to be used in the smart grid system 4.0, which has a stringent requirement under IEEE 1547 standards.