Phase-Shift PWM Converter with Wide Voltage Operation Capability

Abstract: A soft switching three-level pulse-width modulation (PWM) converter is presented for industrial electronics with wide voltage range operation, such as solar power or fuel cell applications. Phase shift PWM scheme is used on the input-side to accomplish the zero voltage turn-on on power switches and improve the converter efficiency. Three-level diode-clamp circuit topology is adopted in the presented circuit to lessen the voltage ratings on active devices for high voltage applications. Three sub-circuits with the different turns-ratio of transformers can be selected in the presented converter in order to achieve 10:1 (Vin,max = 10Vin,min) wide input voltage operation when compared to the conventional multilevel converter. The proposed circuit is a single-stage converter instead of two-stage converter to realize wide voltage operation. Therefore, the presented converter has less component counts. Finally, the design procedure and experiments with a 300W laboratory circuit are presented and discussed to confirm the circuit analysis and converter performance.


Introduction
Renewable energy power conversions have been widely developed to improve and overcome the energy shortage and air pollution from fossil fuels. Wind power and solar power are the most attractive energy sources in modern power generation systems. Power electronic techniques are widely used in the wind power and solar power conversion system to provide the stable voltage output. However, the output voltage of solar panels and wind turbine generators is variable with the wide variation, due to the output voltage value, is related to solar intensity or wind speed. The classical two-stage or three-stage converters are usually adopted [1][2][3] to overcome the wide voltage variation problem of solar panels and or wind turbine generators, and also provide the stable output voltage. Unfortunately, the classical two-stage or three-stage circuit topologies have high power losses and low efficiency. The series-parallel connected converters have been presented in [4][5][6][7] to have wide voltage operation. However, the drawbacks of these circuit topologies are many circuit switches and components in these circuit topologies and the circuit reliability and efficiency are reduced. Phase shift pulse-width modulation (PWM) full-bridge or half-bridge converters [8][9][10][11][12] have developed to present zero voltage switching (ZVS) and wide voltage operation. The control scheme is more difficult to be implemented by the general analog integrated circuit. The resonant converters [13][14][15][16][17][18][19] are widely used in the consumer power supplies for their advantages of low switching loss, high efficiency, and galvanic isolation. The inductor-inductor-capacitor (LLC) circuit topology is the most practical resonant converter with high frequency operation when compared to the different resonant circuit topologies. Unfortunately, the input or output voltage range in circuit topologies [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] is less than 4:1 (i.e., V in,max ≤ 4V in,min ) voltage range. Three-level or multi-level converters [20][21][22][23] with neutral-point diode-clamp, flying capacitor, and series-connected full-bridge circuit topologies are often adopted for high voltage operation to reduce the voltage ratings on active devices. Three-level Figure 1a presents the circuit configuration of the presented circuit topology. Three-level diode clamped converter, including S 1~S4 , C 1 , C 2 , C f , D a , D b , L r , and T 1 , is adopted to lessen the voltage stress on power switches for medium input voltage applications. On the secondary-side, three different winding turns, n s1 , n s1 + n s2 and n s1 + n s2 + n s3 , with alternating current power switches Q 1~Q3 are used to provide three different DC voltage gains and extend the voltage range operation. Each switch of Q 1~Q3 are implemented by two power MOSFETS with back-to-back connection. When Q 1~Q3 are off, the back-to-back body diodes of two MOSFETs are reverse biased and no current will flow through Q 1~Q3 . The presented converter has three sub-circuits, according to the input voltage range. If V in is in the low voltage range V in,L = V in,min~2 V in,min , the switch Q 3 turns on and Q 1 and Q 2 turn off ( Figure 1b). The turns-ratio (n s1 +n s2 +n s3 )/n p of transformer T is used in Figure 1b to maintain high voltage gain. In the low input voltage operation, diodes D 1~D4 are off. If V in is in the medium voltage range V in,M = 2V in,min~4 V in,min , switch Q 2 turns on and Q 1 and Q 3 turn off (Figure 1c). The secondary turns n s1 +n s2 are adopted on the secondary-side. Similarly, switch Q 1 turns on and Q 2 and Q 3 turn off in Figure 1d when V in is in the high voltage range V in,H = 4V in,min1 0V in,min . D 3~D6 are reverse biased in this sub-circuit. The low turns-ratio n s1 /n p is used under the high input voltage range. The secondary winding turns n s1 , n s1 + n s2 or n s1 + n s2 + n s3 , are connected to the output load to achieve three different DC voltage gains, according to the switching states of Q 1Q Electronics 2019, x, x FOR PEER REVIEW

Circuit Operation
The presented converter is operated with the phase-shift PWM scheme. The corresponding switches Q 1~Q3 are controlled to be on or off, so that the proper secondary winding turns n s1 , n s1 + n s2 or n s1 +n s2 + n s3 are connecting to the output road to accomplish wide voltage operation due to the input voltage value. In the presented circuit, it assumes that L m >> L r , C 1 = C 2 , C S1 = ... = C S4 = C oss , C f >> C oss , n s1 = n s2 = n s3 /2 and V C1 = V C2 = V in /2. The circuit can achieve 10:1, i.e., V in,max = 10V in,min , wide input voltage operation. Three sub-circuits, as shown in Figure 2, can be selected in the presented converter based on the input voltage ranges, V in,L = V in,min~2 V in,min , V in,M = 2V in,min~4 V in,min , and V in,H = 4V in,min~1 0V in,min .
At time t5, iD5 is equal to zero ampere and the time interval of state 5 is expressed as Δt45 = t5-t4 ≈ 4LrIo/(nLVin). The duty loss in state 5 is calculated as dloss,5 = Δt45/Tsw = 4LrIofsw/(nLVin), where fsw is the switching frequency and Tsw is the switching period, as both D5 and D6 are still conducting in this state. The PWM waveforms in the states 6-10 are symmetry to waveforms in the states 1-5. Thus, the circuit analysis and discussion of the states 6-10 are neglected.

Medium Input Voltage Range (Q2 on; Q1, Q3 off)
If Vin is in the medium voltage range, 2Vin,min ~ 4Vin,min. The secondary-side switch Q2 turns on and Q1 and Q3 turn off (Figure 1c). The winding turns ns1 + ns2 are connected to the inductor Lo. The transformer turns-ratio under medium voltage range is nM = np/(ns1 + ns2). The DC voltage gain is expressed as GDC,M = Vo/Vin.M = de/nM, where Vin,M denotes Vin in medium input voltage range. The proposed converter has less voltage gain under medium input voltage range and larger voltage gain under low input voltage range since nL < nM. Figure 3a illustrates the main PWM circuit waveforms under medium input voltage range. There are ten operating states for every switching cycle. Figure  3b-k provide these ten equivalent circuits. At t4, vCS3 is equal to zero. DS3 conducts and S3 turns on after t4 to achieve ZVS operation since iLr(t4) > 0. The leg voltage vab = −VC2 = −Vin/2. Owing to D3 and D4 conduct in state 5, vLr equals −Vin/2 and iLr decreases. The diode current iD3 will decrease to 0 at time t5. The PWM waveforms in states 6-10 are symmetrical to waveforms in states 1-5, so that the circuit analysis and discussion of states 6-10 are ignored.

Low Input Voltage Range (Q 3 on; Q 1 , Q 2 off)
If V in is in the low voltage range V in,min~2 V in,min . The secondary-side switch Q 3 turns on and Q 1 and Q 2 turn off ( Figure 1b). The winding turns n s1 + n s2 + n s3 are connected to the output inductor. The transformer turns-ratio is n L = n p /(n s1 + n s2 + n s3 ). The DC voltage gain is calculated as G DC,L = V o /V in.L = d e /n L , where d e is the effective duty cycle and V in,L denotes V in in low input voltage range. Figure 2a shows the PWM waveforms under low input voltage range. i At time t 1 , S 1 turns off. Since i Lr (t 1 ) > 0, C S1 is charged from 0 V and C S4 is discharged from V in /2. State 2 [t 1 , t 2 ]:S 1 turns off at time t 1 . C S1 (C S4 ) is charged (discharged) from 0 V (V in /2). C S1 and C S4 are about several hundreds of picofarads. Therefore, i Lr and i Lo are almost constant in state 2. If the stored energy in L o and L r is greater than the stored energy in C S1 and C S4 , i.e., L r + n 2 L L o i 2 Lr (t 1 ) ≥ C oss V 2 in /2, then v CS4 will be decreased to zero at t 2 . The time duration in state 2 is obtained in (2).
The dead time t d between the gate signals of S 4 and S 1 should be greater than time duration ∆t 12 in state 2 to ensure the ZVS operation of S 4 after t 2 .
State 3 [t 2 , t 3 ]: The body diode D S4 is forward biased due to i Lr (t 2 ) > 0 and v CS4 (t 2 ) = 0. Therefore, S 4 turns on after time t 2 to accomplish soft switching turn-on. Because L m >> L r and the leg voltage v ab = 0, it can obtain the primary-side winding voltage and secondary-side winding voltage are all equal to zero. Diodes D 5 and D 6 are all forward biased, v Lo = −V o and i Lo decreases. The primary-side current is calculated in Equation (3).  (4).
The state 3 ends at time t 3 when S 2 is off.

State 4 [t 3 , t 4 ]:
This state starts at time t 3 when S 2 turns off. Owing to i Lr at t 3 is positive, C S3 (C S2 ) is discharged (charged) from V in /2 (0 V). D 5 and D 6 still conduct in this state. The primary-side winging voltage v Lm = 0. If the energy in the inductor L r is greater than the energy in capacitors C S2 and C S3 , i.e., L r i 2 Lr (t 3 ) ≥ C oss V 2 in /2, then the capacitor v CS3 will be decreased to zero. The time duration in state 4 is calculated as At time t 5 , i D5 is equal to zero ampere and the time interval of state 5 is expressed as ∆t 45 = t 5 -t 4 ≈ 4L r I o /(n L V in ). The duty loss in state 5 is calculated as d loss,5 = ∆t 45 /T sw = 4L r I o f sw/ (n L V in ), where f sw is the switching frequency and T sw is the switching period, as both D 5 and D 6 are still conducting in this state. The PWM waveforms in the states 6-10 are symmetry to waveforms in the states 1-5. Thus, the circuit analysis and discussion of the states 6-10 are neglected.

Medium Input Voltage Range (Q 2 on; Q 1 , Q 3 off)
If V in is in the medium voltage range, 2V in,min~4 V in,min . The secondary-side switch Q 2 turns on and Q 1 and Q 3 turn off ( Figure 1c). The winding turns n s1 + n s2 are connected to the inductor L o . The transformer turns-ratio under medium voltage range is n M = n p /(n s1 + n s2 ). The DC voltage gain is expressed as The proposed converter has less voltage gain under medium input voltage range and larger voltage gain under low input voltage range since n L < n M . Figure 3a illustrates the main PWM circuit waveforms under medium input voltage range. There are ten operating states for every switching cycle. Figure 3b-k provide these ten equivalent circuits.
State 1 [t 0 ,t 1 ]: This state starts at time t 0 when S 1 and S 2 are conducting. Because L r << L m , the primary-  5, v Lr equals −V in /2 and i Lr decreases. The diode current i D3 will decrease to 0 at time t 5 . The PWM waveforms in states 6-10 are symmetrical to waveforms in states 1-5, so that the circuit analysis and discussion of states 6-10 are ignored. State 4 [t3, t4]: Switch S2 turns off at time t3. iLr(t3) > 0 discharges CS3 from Vin/2 to 0 V at time t4. As D1 and D2 both conduct in state 4, the primary-side winging voltage vLm = 0. If the inductor energy ( )/2 is greater than the capacitor energy /4, then CS3 will be discharged to zero voltage. At time t4, vCS3(t4) = 0. Since iLr(t4) > 0, DS3 is conducting and S3 turns on after t4 to achieve ZVS. In this state, vab = −VC2 = −Vin/2, vLr = −Vin/2 and iLr decreases. At time t5, the commutation interval of D1 and D2 is completed and iD1 is decreased to 0. The circuit operation of the states 6-10 are similar to the circuit analysis of the states 1-5. Therefore, the circuit discussion of the states 6-10 are ignored. > 0 discharges C S3 from V in /2 to 0 V at time t 4 . As D 1 and D 2 both conduct in state 4, the primary-side winging voltage v Lm = 0. If the inductor energy L r i 2 Lr (t 3 )/2 is greater than the capacitor energy C oss V 2 in /4, then C S3 will be discharged to zero voltage. At time t 4 , v CS3 (t 4 ) = 0. Since i Lr (t 4 ) > 0, D S3 is conducting and S 3 turns on after t 4 to achieve ZVS. In this state, v ab = −V C2 = −V in /2, v Lr = −V in /2 and i Lr decreases. At time t 5 , the commutation interval of D 1 and D 2 is completed and i D1 is decreased to 0. The circuit operation of the states 6-10 are similar to the circuit analysis of the states 1-5. Therefore, the circuit discussion of the states 6-10 are ignored.

Circuit Characteristics and Design Procedures
The presented three-level converter with different secondary winding turns is controlled with phase-shift PWM operation to realize wide input voltage operation. The secondary switches Q1 ~ Q3 turn on or off to accomplish the different DC voltage gain in order to control the load voltage based on the different input voltage range. The output voltage is calculated in equation (6).
The output inductance Lo is calculated in equation (10), based on the given ripple current ΔiLo.
The duty cycle loss in the state 5 depends on Lr and the inductance Lr can be expressed in equation (11).
The presented circuit is operated under the input voltage range Vin from 80 V ~ 800 V, Vo = 12 V, Po,rated = 300 W, and fsw = 150 kHz. The theoretical three input voltage ranges are Vin,L = 80 V ~ 160 V, Vin,M = 160 V ~ 320 V, and Vin,H = 320 V ~ 800 V. If the input voltage is in the low voltage range (Vin = 80 V ~ 160 V), the secondary switch Q3 is on and Q1 and Q2 are off. The winding turns ns1+ns2+ns3 connect to the output filter inductor Lo. When Vin is increased and equal to 160 V (in medium voltage range Vin = 160 V ~ 320 V), then Q2 is on and Q1 and Q3 are off. Afterwards, the winding turns ns1 + ns2 connect to the output inductor Lo. Similarly, the input voltage is in the high voltage range from 320 V to 800 V. Switch Q1 is on and Q2 and Q3 are off. Only the winding turns ns1 connect to Lo. There is a ±20 V voltage tolerance with Schmitt trigger circuit between three voltage ranges to avoid the signal oscillation at the voltages 160 V between low and medium input voltage ranges and 320 V between the medium and high voltage ranges. The Schmitt comparators and logic gates shown in Figure 5 are

Circuit Characteristics and Design Procedures
The presented three-level converter with different secondary winding turns is controlled with phase-shift PWM operation to realize wide input voltage operation. The secondary switches Q 1~Q3 turn on or off to accomplish the different DC voltage gain in order to control the load voltage based on the different input voltage range. The output voltage is calculated in Equation (6).
The duty cycle loss in the state 5 depends on L r and the inductance L r can be expressed in Equation (11).
The presented circuit is operated under the input voltage range V in from 80 V~800 V, V o = 12 V, P o,rated = 300 W, and f sw = 150 kHz. The theoretical three input voltage ranges are V in,L = 80 V~160 V, V in,M = 160 V~320 V, and V in,H = 320 V~800 V. If the input voltage is in the low voltage range (V in = 80 V~160 V), the secondary switch Q 3 is on and Q 1 and Q 2 are off. The winding turns n s1 +n s2 +n s3 connect to the output filter inductor L o . When V in is increased and equal to 160 V (in medium voltage range V in = 160 V~320 V), then Q 2 is on and Q 1 and Q 3 are off. Afterwards, the winding turns n s1 + n s2 connect to the output inductor L o . Similarly, the input voltage is in the high voltage range from 320 V to 800 V. Switch Q 1 is on and Q 2 and Q 3 are off. Only the winding turns n s1 connect to L o . There is a ±20 V voltage tolerance with Schmitt trigger circuit between three voltage ranges to avoid the signal oscillation at the voltages 160 V between low and medium input voltage ranges and 320 V between the medium and high voltage ranges. The Schmitt comparators and logic gates shown in Figure 5 are adopted to provide the PWM signals for each output voltage range. Therefore, the actual three input voltage ranges are V in,L = 80 V~180 V, V in,M = 140 V~340 V, and V in,H = 300 V~800 V.
The voltage rating of active devices S1 ~ S4 is Vin,max/2 = 400 V. The MOSFETs IPW60R070P6 (650V/33A) are used for switch S1 ~ S4 and Q1 ~ Q3. The average diode currents iD1,av ~ iD6,av are Io,rated/2 = 12.5 A. The maximum voltage stress of D1 ~ D6 are approximately Vin,max/nL = 800 V/2 = 400 V. The ultrafast recovery diodes APT30DQ60BG (600 V/30 A) are adopted for diodes D1 ~ D6. The other passive components in the prototype circuit are Co = 470 μF/35 V, C1 = C2 = 150 μF/450 V, Cf = 1 μF/630 V, and Da and Db are DSEI30-12A with 1200 V/26 A voltage/current stress. The control block of the proposed circuit is given in Figure 5. Two Schmitt comparators and logic gates are adopted to determine three input voltage ranges by using the switching status of Q1 ~ Q3. The phase-shift PWM control integrated circuit UCC3895 is adopted for producing the PWM signals of S1 ~ S4. The voltage regulator TL431 and optocoupler PC817 are adopted to control the load voltage. The type 3 voltage control [29] with two zeros and three poles are used to have the enough phase margin at crossover frequency at 8 kHz.   The proposed converter is assumed to have 90% efficiency at V in = 80V and full road condition under low input voltage range (80V~180V). The assumed maximum duty cycle d max of the leg voltage v ab under V in = 80 V is 0.48. The duty cycle loss d loss,5 at the state 5 is assumed 0.15 and the effective duty cycle d e,max = d max − d loss,5 = 0.33. The primary inductance L r is obtained from (6) and (11).

Experimental Results
The turn-ratio n L can be expected in Equation (13).
In the presented circuit, the turns-ratio of transformer T are n L = 2, n M = 4 and n H = 8, with the primary-side turns n p = 16, the secondary-side turns n s1 = n s2 = 2 and n s3 = 4 and the magnetizing inductance L m = 650 µH. For low voltage range, the minimum effective duty cycle d e,min under the maximum input voltage 180 V is calculated as. d e,min = d e,max V in,L,min /V in,L,max ≈ 0.147 (14) If the ripple current ∆i Lo is assumed 30% of I o,max under V in,L,max = 180 V (low input voltage range). The output filter inductance L o can be derived in Equation (15).
The actual output inductance L o = 8 µH is used in the presented circuit. Under the minimum input voltage, the switches S 1~S4 have the maximum current stress. The switch root-mean-square (rms) currents are approximated in Equation (16).
The voltage rating of active devices S 1~S4 is V in,max /2 = 400 V. The MOSFETs IPW60R070P6 (650V/33A) are used for switch S 1~S4 and Q 1~Q3 . The average diode currents i D1,av~iD6,av are I o,rated /2 = 12.5 A. The maximum voltage stress of D 1~D6 are approximately V in,max /n L = 800 V/2 = 400 V. The ultrafast recovery diodes APT30DQ60BG (600 V/30 A) are adopted for diodes D 1~D6 . The other passive components in the prototype circuit are C o = 470 µF/35 V, C 1 = C 2 = 150 µF/450 V, C f = 1 µF/630 V, and D a and D b are DSEI30-12A with 1200 V/26 A voltage/current stress. The control block of the proposed circuit is given in Figure 5. Two Schmitt comparators and logic gates are adopted to determine three input voltage ranges by using the switching status of Q 1~Q3 . The phase-shift PWM control integrated circuit UCC3895 is adopted for producing the PWM signals of S 1~S4 . The voltage regulator TL431 and optocoupler PC817 are adopted to control the load voltage. The type 3 voltage control [29] with two zeros and three poles are used to have the enough phase margin at crossover frequency at 8 kHz.

Experimental Results
The test results that are based on the circuit components are shown in Table 1 derived in the previous section are demonstrated to confirm the circuit performance. Figures 6-8 show the test waveforms of the presented circuit under low, medium, and high input voltage ranges, and the rated output power. Figure 6a provides the measured PWM waveforms of switches S 1~S4 under V in = 80 V and the rated output power 300 W. Figure 6b provides the PWM signals of switches Q 1~Q3 on the secondary-side. Switch Q 3 is on and Q 1 and Q 2 are off due to the V in = 80V being in the low voltage range. Figure 6c,d provide the measured main currents on the input and output sides. It can observe that the diodes D 5 and D 6 are conducting due to Q 3 is in the on-state. The currents i D1~iD4 are all zero due to Q 1 and Q 2 are off. Figure 6e-h provide the experimental waveforms of the presented circuit under V in = 175 V and P o = 300 W. Figure 6e gives the PWM signals of S 1~S4 . Q 1 and Q 2 are off and Q 3 is on as shown in Figure 6f due to V in = 175 V is in the low voltage range. Figure 6g,h present the main currents on the input and output sides. From Figure 6c,g, the ripple current ∆i Lo at 80 V input voltage is less than the ripple current ∆i Lo at 175 V input voltage due to the duty cycle of the converter leg voltage at V in = 80 V case is larger than the duty cycle at V in = 175 V condition. The measured waveforms in Figure 6 are almost conformed with the theoretical waveforms in Figure 2 under low input voltage range. Figure 7 presents the test results of the presented circuit under the medium input voltage range (V in = 140 V~340 V) and the rated output power. Figure 7a-d gives the experimental waveforms at V in = 145 V and P o = 300 W. Figure 7a,b demonstrate the PWM waveforms of switches S 1~S4 and Q 1~Q3 . Q 1 and Q 3 are off and Q 2 is on due to the medium input voltage range operation (Figure 7b). Figure 7c,d provide the main currents on the input and output sides. Diodes D 3 and D 4 are conducted in the medium input voltage range and D 1 , D 2 , D 5 , and D 6 are off. Similarly, Figure 7e-h provide the test results of the presented circuit under V in = 335 V and P o = 300 W. It is clear that the ripple current ∆i Lo at V in = 145 V (Figure 7c) is less than the ripple current ∆i Lo at V in = 335 V (Figure 7g). Figure 8 gives the test results of the proposed circuit under high input voltage range (V in = 300 V~800 V) and the rated output power. Figure 8a-d provide the measured waveforms at V in = 305 V and P o = 300 W. Figure 8e-h demonstrate the test results at V in = 800 V and P o = 300 W. For high input voltage range, switch Q 1 is on and Q 2 and Q 3 are off (Figure 8b,f). Therefore, diodes D 3~D6 are off (Figure 8d,h). Figure 8a,e show the PWM waveforms of S 1~S4 for V in = 305 V and 800 V, respectively. Figure 8c,g provide the measured currents i Lr , i D1 , i D2 and i Lo for V in = 305 V and 800 V, respectively. Figure 9 shows the test results of S 1 (the leading-leg switch) at V in = 80 V, 400 V and 800 V conditions. Figure 9a,b show the measured results of S 1 at 20% and 100% loads under V in = 80 V input. The drain voltage v S1,d is reduced to zero voltage before S 1 is turned on. Similarly, Figure 9c,d provide the measured waveforms of S 1 at 20% and 100% loads under V in = 400 V input. Figure 9e,f demonstrate the measured waveforms of S 1 at 20% and 100% loads under V in = 800 V input, respectively. The other leading-leg switch S 4 has the same turn-on/turn-off characteristics as switch S 1 . From the experimental waveforms in Figure 9, the leading-leg switches S 1 and S 4 can turn on at ZVS from 20% to 100% rated load. Figure 10 provides the experimental results of the lagging-leg switch S 2 at V in = 80 V, 400 V, and 800 V. Figure 10a,b show the test results of S 2 for 20% and 50% rated power under 80V input case. It can be observed that S 2 is turned on at hard switching operation at 20% load ( Figure 10a) and soft switching operation at 50% load (Figure 10b). Figure 10c,d provide the test results of S 2 for V in = 400 V and 800 V, respectively, under the rated power. From the experimental waveforms that are shown in Figure 10, the lagging-leg switches S 1 and S 2 are almost turned on at hard switching operation. Figure 11 gives the measured converter efficiencies under different voltage ranges. Basically, the converter has larger duty cycle at the low input voltage in each voltage range. The larger duty cycle will result in less root mean square current on the primary-side and less conduction losses. The circuit efficiency at V in = 80 V is better than the circuit efficiency at V in = 175 V under a low input voltage range. Similarly, the circuit efficiency at V in = 305 V is better than the circuit efficiency at V in = 800 V under high input voltage range operation. The circuit efficiency under the high input voltage range is better than the low input voltage range since the presented circuit has larger the primary-side current under low input voltage range. The synchronous rectifiers with low turn-on resistance instead of rectifier diodes can be adopted on the secondary side to reduce the conduction losses in order to increase the circuit efficiency. The Litz wire [30] can be adopted to avoid the skin effect on winding resistance to reduce the copper losses on transformer and output inductor. The more power loss analysis of power semiconductors, inductors, transformers, and capacitors on power converters has been discussed in [31].  (g) (h) Figure 6. Experimental waveforms at the rated output power and low input voltage range (a) primary-side switch waveforms vS1,g ~ vS4,g under Vin = 80 V (b) secondary-side switch waveforms vQ1,g    v S1,g i S1 v S1,d 10V 50V 20A Figure 8. Experimental waveforms at the rated output power and high input voltage range (a) primary-side switch waveforms v S1,g~vS4,g under V in = 305 V (b) secondary-side switch waveforms v Q1,g~vQ3,g under V in = 305 V (c) i Lr , i D1 , i D2 , and i Lo under V in = 305 V (d) i D3~iD6 under V in = 305 V (e) primary-side switch waveforms v S1,g~vS4,g under V in = 800V (f) secondary-side switch waveforms v Q1,g~vQ3,g under V in = 800 V (g) i Lr , i D1 , i D2 , and i Lo under V in = 800 V (h) i D3~iD6 under V in = 800 V.

Conclusion
In solar power system, the input voltage from solar panel is wide variation due to the different solar intensity in day and night. The conventional two-level or three-level converter cannot be operated under wide voltage operation. In this paper, a three-level diode-clamped DC/DC converter

Conclusion
In solar power system, the input voltage from solar panel is wide variation due to the different solar intensity in day and night. The conventional two-level or three-level converter cannot be operated under wide voltage operation. In this paper, a three-level diode-clamped DC/DC converter

Conclusions
In solar power system, the input voltage from solar panel is wide variation due to the different solar intensity in day and night. The conventional two-level or three-level converter cannot be operated under wide voltage operation. In this paper, a three-level diode-clamped DC/DC converter with three auxiliary secondary turns is presented and then discussed to provide the capability of 10:1 wide voltage range operation for solar power converters to supply the isolated power supply for control board demand. Three sets of secondary windings are adopted in the presented circuit to overcome the wide input voltage variation in solar power converters. The proposed converter can operate at three input voltage ranges to supply the stable DC voltage at the output load due to three different secondary winding turns connected to output side. The PWM scheme is adopted to control the load voltage in each input voltage range. The leading-leg switches in the three-level converter can be realized with ZVS operation due to the large inductor energy on the output inductor. The lagging-leg switches are almost operated at hard switching operation due to the limited energy stored on the leakage inductor of transformer. The large leakage inductor or external inductor can be used on the input side to overcome this disadvantage. However, the large leakage inductor will increase the duty cycle loss in state 5. The future work of this project will investigate the new snubber circuit or auxiliary circuit added on the output side to lessen the freewheel current. Thus, the duty cycle loss can be expected to reduce and the soft switching operation range of the lagging-leg switches can be extended. The proposed converter can be used in the solar power system with wide input voltage variation from solar panel to provide the standalone power unit for control system demand. Finally, the test results prove the performance and feasibility of the presented circuit.