Multilayer Model Predictive Control for a Voltage Mode Digital Power Amplifier

The application of the finite control set model predictive control to cascaded inverters is severely limited by its computational complexity. In this paper, a load observer based multilayer model predictive control is proposed for the voltage mode digital power amplifier employing cascaded full-bridge neutral point clamped inverter, which can avoid the use of load current sensor and greatly reduce the controller computation without affecting its dynamic performance. The discrete mathematical model of the voltage mode digital power amplifier employing cascaded full-bridge neutral point clamped inverter is established with filter inductor current and filter capacitor voltage as state variables. A load current observer is designed based on this to avoid the use of load current observer. Based on the discrete model and the observed load current, the upper layer of the multilayer model predictive control determines the optimal level that minimizes the cost function. The middle layer allocates the optimal level to each submodule in order to achieve capacitor voltage balancing. The lower layer determines the switching state of each submodule in order to reduce switching actions. Finally, the experimental results based on the designed nine-level prototype show that the develop multilayer model predictive control lead to acceptable steady state, dynamic and robust performance, with only 1.37% of the run time of the traditional model predictive control.


Introduction
Power amplifiers are widely used in industrial testing and measurement [1]. They are also often used to drive underwater acoustic transducers to produce low-frequency tunable sound sources, which can realize submarine navigation and ranging [2]. Currently, power amplifiers can be divided into class A, class B, class AB and class D. Class D power amplifier, also known as the digital power amplifier, is widely used in high-power occasions because of its advantages of low power loss and high efficiency [3]. According to the different types of loads driven by digital power amplifiers, the digital power amplifiers can be divided into two modes: the voltage mode and the current mode. The voltage mode digital power amplifiers are mainly used to provide alternating electrical energy to loads such as piezoelectric ceramic transducers [4]. Compared with two-level or three-level inverter, cascaded inverter, such as cascaded H-bridge inverter [5], modular multilevel converter [6] and cascaded full-bridge neutral point clamped inverter (CFNPCI) [7], has the advantages of high power, low step voltage and step current, strong fault handling ability, modular structure and high output waveform quality; thus, it is often employed by high power digital power amplifiers. However, high power digital power amplifiers employing cascaded inverter use a large number of switching devices, which makes the control the digital power amplifiers very complex. In addition, digital power amplifiers load current sensor, a load observer is designed in Section 3, which can estimate the load current online. On this basis, a low complexity MMPC is proposed in Section 4, which divides multiple control objectives of the digital power amplifier system into upper, middle and lower layers. In Section 5, the feasibility and effectiveness of the proposed MMPC are verified on a nine-level experimental prototype. The circuit structure of the voltage mode digital power amplifier employing CFNPCI is shown in Figure 1. The output voltage of the CFNPCI is expressed by V ab , and the output voltage of the digital power amplifier, V o , can be obtained after filtering by LC filter composed of filter inductor L f and filter capacitor C f . The current of the filter inductor is expressed by i f , and its positive direction is shown in Figure 1. The voltage of the filter capacitor is also the digital power amplifier output voltage, which is denoted by V o . The output current of the digital power amplifier is denoted by i o . The CFNPCI consists of n identical submodules in series, and the topology of each submodule is a full-bridge neutral point clamped inverter. The DC side of each submodule uses an isolated power supply module with output voltage of V dc to provide voltage support. Two capacitors with same value, C i1 and C i2 , are connected in series to obtain two electric potentials of V dc /2 and −V dc /2. Each submodule consists of eightIGBTs, eightanti-parallel diodes and fourclamping diodes. The AC side of each submodule can output five levels of −2, −1, 0, 1, 2. Then the voltage mode digital power amplifier composed of n submodules can output 4n + 1 levels of −2n, −2n + 1, . . . , 0, . . . , 2n − 1, and 2.

Circuit
load current sensor, a load observer is designed in Section 3, which can est current online. On this basis, a low complexity MMPC is proposed in Se divides multiple control objectives of the digital power amplifier system middle and lower layers. In Section 5, the feasibility and effectiveness of MMPC are verified on a nine-level experimental prototype.

Circuit Structure of the Voltage Mode Digital Power Amplifier Employing CF
The circuit structure of the voltage mode digital power amplifi CFNPCI is shown in Figure 1. The output voltage of the CFNPCI is express the output voltage of the digital power amplifier, Vo, can be obtained after f filter composed of filter inductor Lf and filter capacitor Cf. The current o ductor is expressed by if, and its positive direction is shown in Figure 1. The filter capacitor is also the digital power amplifier output voltage, which is d The output current of the digital power amplifier is denoted by io. The CF of n identical submodules in series, and the topology of each submodule i neutral point clamped inverter. The DC side of each submodule uses an i supply module with output voltage of Vdc to provide voltage support. T with same value, Ci1 and Ci2, are connected in series to obtain two electri Vdc/2 and −Vdc/2. Each submodule consists of eightIGBTs, eightanti-parall fourclamping diodes. The AC side of each submodule can output five levels 2. Then the voltage mode digital power amplifier composed of n submodu 4n + 1 levels of −2n, −2n + 1, …, 0, …, 2n − 1, and 2.  The driving signal of IGBT is represented by S xij . x ∈ {a, b} denotes legs of the inverter, where a denotes the left one, b denotes the right one. i ∈ {1, 2, . . . , n} denotes the submodule number, j ∈ {1, 2, 3, 4} denotes the number of the transistor in the same bridge. In normal operation, S ia1 and S ia3 complement each other, S ia2 and S ia4 complement each other, too. S ib1 , S ib2 , S ib3 and S ib4 also meet this constraint. S i = [S ai1 S ai2 S ai3 S ai4 S bi1 S bi2 S bi3 S bi4 ] is defined as the switching state of the ith submodule, and M i is used to denote the output level of the ith submodule. U Ci1 and U Ci2 respectively denote the voltages of DC capacitors C i1 and C i2 in the ith submodule. ∆U Ci is defined as the difference between U Ci1 and U Ci2 , which can be calculated by (1).
(1) Table 1 shows the relationship between the change of ∆U Ci , the output level M i , the inductor current i f , and the nineeffective switching states.

Discrete Model of the Voltage Mode Digital Power Amplifier Employing CFNPCI
Assuming that the capacitor voltages in all submodules are well balanced, (2) can be obtained according to Kirchhoff's law of voltage and current.
The total output level M ∈ {−2n, −2n + 1, . . . , 0, . . . , 2n − 1, 2}, and can be expressed as (4) Using x = [i f V o ] T to denote the system state variables, and substituting (3) and (4) into (2), the continuous system model of the voltage mode digital power amplifier can be obtained, as shown in (5), where For the purpose of digital control, (5) should be discretized. The sampling period is denoted as T S . The discrete model is expressed as (6), e Aτ B 2 dτ, k and k + 1 represent the kT S and (k + 1)T S instant, respectively. In addition, the system output equation can be expressed by (7).

Design of the Load Observer
The load current i o , which is also the output current of the voltage mode digital power amplifier, depends on the load. It can be seen from (6) that i o is an interference term for the close-loop of V o , which is generally measured by the configured current sensor. In this paper, a state observer is designed to estimate i o online, which avoids the use of current sensor and reduces the system hardware cost.
Assuming that the load current i o is constant in a single sampling period [10], and extending i o to a state variable of the system, (8) can be obtained.
The system output equation can be rewritten as (9).
, C = 1 0 0 0 1 0 , then the state observer shown in (10) can be constructed to realize online estimation of load current i o .
In (10),X(k) = î f (k)V o (k)î o (k) denotes the estimated value of the extended system state variable i o (k) is the estimated value of i o (k), and can be calculated based on (11).
The designed load observer can be regarded as a discrete Kalman Filter, and its gain matrix K can be calculated to obtain the optimal estimation of i o in the presence of random measurement noise.
It should be pointed out that the estimation error of the designed load observer depends on the selected gain matrix K. Unreasonable gain parameters will lead to large estimation error of i o , and eventually lead to tracking error of the MMPC in Section 4. Therefore, the gain matrix of the load observer should be elaborated to achieve a tradeoff between the dynamic performance and the noise immunity. The parameter selection method in [10] can be used to determine the gain matrix K.

Multilayer Model Predictive Control for the Voltage Mode Digital Power Amplifier Employing CFNPCI
In traditional model predictive control (TMPC), the cost function under all switching states must be calculated in each control cycle, and the switching state which minimizes the cost function should be selected. However, if we extend the TMPC to CFNPCI with n submodules, there will be 9 n effective switching states. This also means that the cost function needs to be repeatedly calculated for 9 n times to obtain the optimal switching state, and the amount of calculation increases exponentially with the increase of the submodule number n, which will pose a great challenge to the computational performance of the controller.
The overall control of the CFNPCI, as shown in Figure 2a, consists of the designed load observer and the proposed MMPC. The structure of the proposed MMPC is shown in Figure 2, including upper, middle and lower layers. No matter how large n is, the MMPC can avoid the repeated calculation of the cost function, greatly reduce the computational burden of the controller, and the dynamic performance can also not be affected. The upper layer control is used to determine the optimal level to minimize the cost function. The middle layer control is used to distribute the optimal level to each submodule aiming to balance the capacitor voltages in all the submodules. The lower layer control is used to determine the switching state of each submodule aiming to minimize the switching actions.

Multilayer Model Predictive Control for the Voltage Mode Digital Power Am Employing CFNPCI
In traditional model predictive control (TMPC), the cost function under all sw states must be calculated in each control cycle, and the switching state which m the cost function should be selected. However, if we extend the TMPC to CFNPC submodules, there will be 9 n effective switching states. This also means that function needs to be repeatedly calculated for 9 n times to obtain the optimal sw state, and the amount of calculation increases exponentially with the increas submodule number n, which will pose a great challenge to the computationa mance of the controller.
The overall control of the CFNPCI, as shown in Figure 2a, consists of the d load observer and the proposed MMPC. The structure of the proposed MMPC i in Figure 2, including upper, middle and lower layers. No matter how large MMPC can avoid the repeated calculation of the cost function, greatly reduce t putational burden of the controller, and the dynamic performance can also no fected. The upper layer control is used to determine the optimal level to minim cost function. The middle layer control is used to distribute the optimal level submodule aiming to balance the capacitor voltages in all the submodules. Th layer control is used to determine the switching state of each submodule ai minimize the switching actions.

The Upper Layer Control
Voref(k + 1) is used to represent the output voltage reference at (k + 1)TS. T filter inductor current reference ifref(k + 1) can be calculated by (12).
The used system cost function J(h) can be expressed by (13),

The Upper Layer Control
V oref (k + 1) is used to represent the output voltage reference at (k + 1)T S . Then, the filter inductor current reference i fref (k + 1) can be calculated by (12).
The used system cost function J(h) can be expressed by (13), where i fh (k + 1) and V oh (k + 1) respectively denote the instantaneous values of the inductor current i f and the capacitor voltage V oh at (k + 1)T s if the candidate output level h is selected in the kth control period. λ 1 and λ 2 are the weight factors. i fh (k + 1) can be calculated based on (14), while V oh (k + 1) can be calculated based on (15), whereî o (k) is obtained from the designed load observer in Section 3. Define the function J 1 (h) as shown in (16), where a 1 can be calculated by (17), h 1 can be calculated by (18).
Define the function J 2 (h) as shown in (19), where a 2 can be calculated by (20), h 2 can be calculated by (21).
It is easy to know that J(h) = J 1 (h) + J 2 (h). If we assume that h is a continuous variable whose domain of definition is (−∞, +∞), according to (16) and (19), the relationship between J 1 (h) and h is linear, the relationship between J 2 (h) and h also is linear.
Therefore, the function curves of J(h), J 1 (h) and J 2 (h) with respect to h have only four cases, as shown in Figure 3. where ifh(k + 1) and Voh(k + 1) respectively denote the instantaneous values of the inductor current if and the capacitor voltage Voh at (k + 1)Ts if the candidate output level h is selected in the kth control period. λ1 and λ2 are the weight factors. ifh(k + 1) can be calculated based on (14), while Voh(k + 1) can be calculated based on (15), where ( ) ô i k is obtained from the designed load observer in Section 3.
It is easy to know that J(h) = J1(h) + J2(h). If we assume that h is a continuous variable whose domain of definition is (−∞, +∞), according to (16) and (19), the relationship between J1(h) and h is linear, the relationship between J2(h) and h also is linear.
Therefore, the function curves of J(h), J1(h) and J2(h) with respect to h have only four cases, as shown in Figure 3.
Based on Figure 3, we can discuss the abscissa p when J(h) takes the minimum value in the interval [−2n, 2n]. The results are shown in Table 2.
The optimal output level M(k) must be the element in the set H that minimizes the cost function J(h), while the minimum of J(h) should be 0. Therefore, M(k) can be calculated by (22), where floor(p) means to round down p to obtain the largest integer not greater than p; ceil(p) means to round up p to obtain the smallest integer not less than p.
In order to further reduce the amount of calculation, the approximate calculation method shown in (23) is used in this paper, where round(p) means to round p to obtain the nearest integer to p. The maximum difference between the result of (23) and the result of (22) is one level, which will not cause unacceptable control error. However, if we obtain M(k) based on (23) rather than (22), J[floor(p)] and J[ceil(p)] can be avoided calculating and comparing with each other.
Because a1 and a2 are only determined by the weight factors and system parameters, they can be calculated off-line in the initialization link, and there is no need to calculate them in each control cycle, so the algorithm computation can be further reduced. Figure  4 shows the flow chart of the upper layer control when a1 ≥ a2 and a1 < a2 respectively.
Based on Figure 3, we can discuss the abscissa p when J(h) takes the minimum value in the interval [−2n, 2n]. The results are shown in Table 2.
The optimal output level M(k) must be the element in the set H that minimizes the cost function J(h), while the minimum of J(h) should be 0. Therefore, M(k) can be calculated by (22), where floor(p) means to round down p to obtain the largest integer not greater than p; ceil(p) means to round up p to obtain the smallest integer not less than p.
In order to further reduce the amount of calculation, the approximate calculation method shown in (23) is used in this paper, where round(p) means to round p to obtain the nearest integer to p. The maximum difference between the result of (23) and the result of (22) is one level, which will not cause unacceptable control error. However, if we obtain M(k) based on (23) rather than (22), J[floor(p)] and J[ceil(p)] can be avoided calculating and comparing with each other.
Because a 1 and a 2 are only determined by the weight factors and system parameters, they can be calculated off-line in the initialization link, and there is no need to calculate them in each control cycle, so the algorithm computation can be further reduced. Figure 4 shows the flow chart of the upper layer control when a 1 ≥ a 2 and a 1 < a 2 respectively. Electronics 2021, 10,  Based on the above analysis, the tracking error of the MMPC is not only related to the estimation accuracy of the output current io, but also related to its control period. A shorter control period will lead to a smaller tracking error. The upper layer control significantly reduces the computation and the running time of the MPC algorithm, so that a shorter control period can be used and a smaller tracking error can be obtained.

The Middle Layer Control
Since each submodule can output fivelevels of 2, 1, 0, −1, −2, the constraint condition of (24) must be satisfied when the optimal level obtained by upper layer control is allocated to each submodule.
However, the number of level combinations satisfying the constraint of (24) is large, which makes the level allocation complex. In this paper, the following three constraints are added to simplify the level allocation algorithm: (1) When M(k) > 0, Mi(k) is selected from 2, 1 and 0; (2) When M(k) < 0, Mi(k) is selected from −2, −1 and 0; (3) When M(k) = 0, Mi(k) is set to 0. Furthermore, the analysis of Table 1 shows that only the 1 and −1 levels will affect the submodule capacitor voltages. Therefore, in order to achieve capacitor voltage balance, the submodules with larger capacitor voltage differences should be allocated 1 or −1 level, while the submodules with smaller capacitor voltage differences should be allocated 2, 0 or −2 level. Based on this analysis, this paper proposes the following allocation steps: Step 1: Calculate the absolute values of capacitor voltage differences of all submodules; Step 2: Sort the absolute values of capacitor voltage differences of all submodules in descending order; Step 3: According to the sorting result of Step 2, the first allocation pass is performed from front to back, and each submodule is allocated +1 level (Mi(k) > 0) or −1 level (Mi(k) < 0). If the output level cannot be allocated completely in the first pass, the second pass will be performed from the back to the front until the output level is allocated completely. Based on the above analysis, the tracking error of the MMPC is not only related to the estimation accuracy of the output current i o , but also related to its control period. A shorter control period will lead to a smaller tracking error. The upper layer control significantly reduces the computation and the running time of the MPC algorithm, so that a shorter control period can be used and a smaller tracking error can be obtained.

The Middle Layer Control
Since each submodule can output fivelevels of 2, 1, 0, −1, −2, the constraint condition of (24) must be satisfied when the optimal level obtained by upper layer control is allocated to each submodule.
However, the number of level combinations satisfying the constraint of (24) is large, which makes the level allocation complex. In this paper, the following three constraints are added to simplify the level allocation algorithm: (1) When M(k) > 0, M i (k) is selected from 2, 1 and 0; (2) When M(k) < 0, M i (k) is selected from −2, −1 and 0; (3) When M(k) = 0, M i (k) is set to 0. Furthermore, the analysis of Table 1 shows that only the 1 and −1 levels will affect the submodule capacitor voltages. Therefore, in order to achieve capacitor voltage balance, the submodules with larger capacitor voltage differences should be allocated 1 or −1 level, while the submodules with smaller capacitor voltage differences should be allocated 2, 0 or −2 level. Based on this analysis, this paper proposes the following allocation steps: Step 1: Calculate the absolute values of capacitor voltage differences of all submodules; Step 2: Sort the absolute values of capacitor voltage differences of all submodules in descending order; Step 3: According to the sorting result of Step 2, the first allocation pass is performed from front to back, and each submodule is allocated +1 level (M i (k) > 0) or −1 level (M i (k) < 0). If the output level cannot be allocated completely in the first pass, the second pass will be performed from the back to the front until the output level is allocated completely. Figure 5 shows the level allocation process when the submodule number n = 3 and the total output level M(k) = 2 or −5. It can be seen that by using the proposed level allocation steps, the submodules with larger capacitor voltage differences can be more likely to be allocated 1 or −1 level, and the submodules with smaller capacitor voltage differences can be more likely to be allocated 2, 0 or −2 level, thus creating conditions for capacitor voltage balance control.
Electronics 2021, 10, x 10 of 16 Figure 5 shows the level allocation process when the submodule number n = 3 and the total output level M(k) = 2 or −5. It can be seen that by using the proposed level allocation steps, the submodules with larger capacitor voltage differences can be more likely to be allocated 1 or −1 level, and the submodules with smaller capacitor voltage differences can be more likely to be allocated 2, 0 or −2 level, thus creating conditions for capacitor voltage balance control.

The Lower Layer Control
Due to the additional level allocation constraints in the middle layer control, when M(k) > 0, the output level number Mi(k) of the ith submodule can only switch between 0, 1 and 2. Table 3 counts the IGBT action times when the three levels switch with each other. At the same time, according to Table 1, if a submodule is allocated +2 level, the corresponding switching state can only select S1. If a submodule is allocated +1 level, in order to achieve capacitor voltage balance, S2 should be selected when the signs of io and ΔUCi are the same, while S3 should be selected when they are opposite. If a submodule is allocated 0 level, in order to minimize the number of switching actions when switching between 0 level and +1 level, S5 should be selected. Table 3. The number of switching action when the output level switched between 0, 1 and 2.

Switching Level
Switching State Switching Actions 2 and 1 S1 and S2 2 S1 and S3 2 1 and 0 S2 and S4 2 S2 and S5 2 S2 and S6 6 S3 and S4 6 S3 and S5 2 S3 and S6 2 2 and 0 S1 and S4 4 S1 and S5 4 S1 and S6 4 When Mi(k) < 0, the following conclusions can be drawn: (1) if a submodule is allocated −2 level, S9 should be selected; (2) if a submodule is allocated −1 level, S8 should be selected when the signs of io and ΔUCi are the same, while S7 should be selected when they are opposite; (3) if a submodule is allocated 0 level, S5 should be selected. Figure 6 shows the flow chart of the switching state selection process. It can be seen that the middle layer control and the lower layer control are parallel structure, so they are more suitable to be implemented in FPGA.

The Lower Layer Control
Due to the additional level allocation constraints in the middle layer control, when M(k) > 0, the output level number M i (k) of the ith submodule can only switch between 0, 1 and 2. Table 3 counts the IGBT action times when the three levels switch with each other. At the same time, according to Table 1, if a submodule is allocated +2 level, the corresponding switching state can only select S1. If a submodule is allocated +1 level, in order to achieve capacitor voltage balance, S2 should be selected when the signs of i o and ∆U Ci are the same, while S3 should be selected when they are opposite. If a submodule is allocated 0 level, in order to minimize the number of switching actions when switching between 0 level and +1 level, S5 should be selected. Table 3. The number of switching action when the output level switched between 0, 1 and 2.

Switching Level
Switching State Switching Actions 2 and 1 S1 and S2 2 S1 and S3 2 1 and 0 S2 and S4 2 S2 and S5 2 S2 and S6 6 S3 and S4 6 S3 and S5 2 S3 and S6 2 2 and 0 S1 and S4 4 S1 and S5 4 S1 and S6 4 When M i (k) < 0, the following conclusions can be drawn: (1) if a submodule is allocated −2 level, S9 should be selected; (2) if a submodule is allocated −1 level, S8 should be selected when the signs of i o and ∆U Ci are the same, while S7 should be selected when they are opposite; (3) if a submodule is allocated 0 level, S5 should be selected. Figure 6 shows the flow chart of the switching state selection process. It can be seen that the middle layer control and the lower layer control are parallel structure, so they are more suitable to be implemented in FPGA. Electronics 2021, 10, x 11 of 16

Comparisons of Computation
In order to prove the advantages of the MMPC in reducing the calculation amount, the TMPC proposed in [7] is used to compare with the algorithm in this paper. In order to obtain a general conclusion independent of the specific controller, Table 4 compares the number of addition, subtraction, multiplication, division and comparison operations required by the TMPC and the MMPC.
It can be seen from Table 4 that there is a linear or quadratic relationship between the calculation amount required by the MMPC and the submodule number n, while the calculation amount required by the TMPC has an exponential relationship with n. Therefore, the MMPC proposed in this paper has a significant advantage in the algorithm computation. Table 4. Comparisons of computation complexity.

Experimental Verification
In order to verify the feasibility and effectiveness of the designed load current observer and the proposed MMPC in this paper, an experimental prototype as shown in Figure 7 is built in the laboratory for experimental verification. The experimental prototype consists of two submodules, which can output up to ninelevels. The output frequency band of the prototype is from 50 Hz to 800 Hz. The filter inductance is 2 mH, and the filter capacitance is 4.7 µF. The rated power of each submodule is 2 kW, the dc input voltage f each submodule is 300 V and the dc capacitance is 1070 µF. The control period is set to 25 µs.

Comparisons of Computation
In order to prove the advantages of the MMPC in reducing the calculation amount, the TMPC proposed in [7] is used to compare with the algorithm in this paper. In order to obtain a general conclusion independent of the specific controller, Table 4 compares the number of addition, subtraction, multiplication, division and comparison operations required by the TMPC and the MMPC.
It can be seen from Table 4 that there is a linear or quadratic relationship between the calculation amount required by the MMPC and the submodule number n, while the calculation amount required by the TMPC has an exponential relationship with n. Therefore, the MMPC proposed in this paper has a significant advantage in the algorithm computation.

Experimental Verification
In order to verify the feasibility and effectiveness of the designed load current observer and the proposed MMPC in this paper, an experimental prototype as shown in Figure 7 is built in the laboratory for experimental verification. The experimental prototype consists of two submodules, which can output up to ninelevels. The output frequency band of the prototype is from 50 Hz to 800 Hz. The filter inductance is 2 mH, and the filter capacitance is 4.7 µF. The rated power of each submodule is 2 kW, the dc input voltage f each submodule is 300 V and the dc capacitance is 1070 µF. The control period is set to 25 µs.

Comparisons of Computation
In order to prove the advantages of the MMPC in reducing the calculation amount, the TMPC proposed in [7] is used to compare with the algorithm in this paper. In order to obtain a general conclusion independent of the specific controller, Table 4 compares the number of addition, subtraction, multiplication, division and comparison operations required by the TMPC and the MMPC.
It can be seen from Table 4 that there is a linear or quadratic relationship between the calculation amount required by the MMPC and the submodule number n, while the calculation amount required by the TMPC has an exponential relationship with n. Therefore, the MMPC proposed in this paper has a significant advantage in the algorithm computation. Table 4. Comparisons of computation complexity.

Experimental Verification
In order to verify the feasibility and effectiveness of the designed load current observer and the proposed MMPC in this paper, an experimental prototype as shown in Figure 7 is built in the laboratory for experimental verification. The experimental prototype consists of two submodules, which can output up to ninelevels. The output frequency band of the prototype is from 50 Hz to 800 Hz. The filter inductance is 2 mH, and the filter capacitance is 4.7 µF. The rated power of each submodule is 2 kW, the dc input voltage f each submodule is 300 V and the dc capacitance is 1070 µF. The control period is set to 25 µs.  In the designed experimental prototype, the number of submodules n is equal to 2, and the maximum total output level M can be taken as 4. Based on Table 4, the TMPC requires  1863 addition calculations, 1296 subtraction calculations, 2754 multiplication calculations,  729 division calculations and 405 comparison calculations for each control period, which poses a huge challenge to the computing performance of the controller. However, the MMPC proposed in this paper only requires 5 addition calculations, 9 subtraction calculations, 5 multiplication calculations, and 11 comparison calculations for each control period. In addition, both the TMPC and the MMPC are tested on a DSP of TMS320F28335. The results show that the TMPC takes 503 µs to run once, while the improved algorithm only takes 6.9 µs to run once. Therefore, the develop multilayer structure greatly reduces the computation burden of the controller and can be acceptable for general digital controllers.

Steady State Performance
In order to study the steady state performance of the designed load observer and the proposed MMPC, the output voltage reference V oref is set as a sine wave with frequency of 800 Hz and amplitude of 550 V. The load is set to an 80 Ω resistor. The experiment results are shown in Figure 8, where Figure 8a shows the waveforms of V o and its reference V oref , Figure 8b shows the waveforms of i f and its reference i fref , Figure 8c shows the waveforms of i o and its estimated value, and Figure 8d shows the capacitor voltages of the first submodule. It should be pointed out that the waveform of i o in Figure 8c is obtained by directly measuring based on the current probe. In the designed experimental prototype, the number of submodules n is equal to 2, and the maximum total output level M can be taken as 4. Based on Table 4, the TMPC  requires 1863 addition calculations, 1296 subtraction calculations, 2754 multiplication  calculations, 729 division calculations and 405 comparison calculations for each control period, which poses a huge challenge to the computing performance of the controller. However, the MMPC proposed in this paper only requires 5 addition calculations, 9 subtraction calculations, 5 multiplication calculations, and 11 comparison calculations for each control period. In addition, both the TMPC and the MMPC are tested on a DSP of TMS320F28335. The results show that the TMPC takes 503 µs to run once, while the improved algorithm only takes 6.9 µs to run once. Therefore, the develop multilayer structure greatly reduces the computation burden of the controller and can be acceptable for general digital controllers.

Steady State Performance
In order to study the steady state performance of the designed load observer and the proposed MMPC, the output voltage reference Voref is set as a sine wave with frequency of 800 Hz and amplitude of 550 V. The load is set to an 80 Ω resistor. The experiment results are shown in Figure 8, where Figure 8a shows the waveforms of Vo and its reference Voref, Figure 8b shows the waveforms of if and its reference ifref, Figure 8c shows the waveforms of io and its estimated value, and Figure 8d shows the capacitor voltages of the first submodule. It should be pointed out that the waveform of io in Figure 8c  It can be seen from Figure 8 that the designed load observer accurately estimates the actual load current io under steady state condition. The small estimating error of io leads the proposed MMPC to output accuracy inductor current and output voltage, which means small tracking errors are obtained. In addition, the total harmonic distortion rate of the output voltage is tested to be 0.84%, which shows acceptable waveform quality. Therefore, both the load observer and the MMPC show good steady state performance. It can be seen from Figure 8 that the designed load observer accurately estimates the actual load current i o under steady state condition. The small estimating error of i o leads the proposed MMPC to output accuracy inductor current and output voltage, which means small tracking errors are obtained. In addition, the total harmonic distortion rate of the output voltage is tested to be 0.84%, which shows acceptable waveform quality. Therefore, both the load observer and the MMPC show good steady state performance.

Dynamic Performance
The output voltage reference V oref is set as a sine wave with frequency of 50Hz and amplitude of 275 V, while its amplitude steps to 550 V at some point. The load is still set to an 80 Ω resistor. Under this condition, the dynamic performance of the load observer and the MMPC is tested. The experiment results are shown in Figure 9, where Figure 9a shows the waveforms of V o and its reference V oref , Figure 9b shows the waveforms of i f and its reference i fref , Figure 9c shows the waveforms of i o and its estimated value, and Figure 9d shows the capacitor voltages of the first submodule.
It can be seen from Figure 9 that, within 0.4 ms, the designed load observer can still quickly and accurately estimate the actual load current under the condition of both the output voltage reference and the load current step change. This also means that the selected gain parameters of the load observer have a good tradeoff between the dynamic performance and the noise immunity. With the help of this, the proposed MMPC also quickly and accurately tracks the step change output reference. Therefore, the dynamic performances of both the load observer and the MMPC are verified.

Dynamic Performance
The output voltage reference Voref is set as a sine wave with frequency of 50Hz and amplitude of 275 V, while its amplitude steps to 550 V at some point. The load is still set to an 80 Ω resistor. Under this condition, the dynamic performance of the load observer and the MMPC is tested. The experiment results are shown in Figure 9, where Figure 9a shows the waveforms of Vo and its reference Voref, Figure 9b shows the waveforms of if and its reference ifref, Figure 9c shows the waveforms of io and its estimated value, and Figure 9d shows the capacitor voltages of the first submodule. It can be seen from Figure 9 that, within 0.4 ms, the designed load observer can still quickly and accurately estimate the actual load current under the condition of both the output voltage reference and the load current step change. This also means that the selected gain parameters of the load observer have a good tradeoff between the dynamic performance and the noise immunity. With the help of this, the proposed MMPC also quickly and accurately tracks the step change output reference. Therefore, the dynamic performances of both the load observer and the MMPC are verified.

Robust Performance
The load of the voltage mode digital power amplifier employing CFNPCI is set as the uncontrolled rectifier bridge shown in Figure 10, which is a nonlinear load. In the rectifier bridge, the capacitance is set to be 400 µF, the resistance is set to be 120 Ω. The robust performance of the load observer and the MMPC is verified under this condition. The output voltage reference Voref is still set to a sine wave with frequency of 50 Hz and amplitude of 550 V.

Robust Performance
The load of the voltage mode digital power amplifier employing CFNPCI is set as the uncontrolled rectifier bridge shown in Figure 10, which is a nonlinear load. In the rectifier bridge, the capacitance is set to be 400 µF, the resistance is set to be 120 Ω. The robust performance of the load observer and the MMPC is verified under this condition. The output voltage reference V oref is still set to a sine wave with frequency of 50 Hz and amplitude of 550 V.  Figure 11 shows the waveforms of Vo and its reference Voref. It can be seen that, even when the voltage mode digital power amplifier supplies power to a non-linear load, th total harmonic distortion rate of the output voltage still reaches 1.74%, which show strong system robustness.

Conclusions
A cascaded multilevel inverter provides an effective way to increase the capacity o the digital power amplifier. In this paper, a load observer is designed for the voltag mode digital power amplifier employing CFNPCI topology, which could estimate th output current online without configuring the output current sensor, thus reducing th hardware cost. On this basis, an MMPC is proposed, which could completely avoid cycli calculation and comparison of the system cost function, so the amount of calculation o the controller can be significantly reduced. The test results show that the TMPC takes 503 µs to run once, while the MMPC only takes 6.9 µs to run once. In addition, the experi mental results show that the total harmonic distortion rate of the output voltage is only 0.84% in the steady state experiment, both the load observer and the MMPC could track the step change load and reference within 0.4ms in the dynamic experiment, and the tota harmonic distortion rate of the output voltage can still reach 1.74% even when the digita power amplifier supplies power for diode rectifier bridge load.   Figure 11 shows the waveforms of V o and its reference V oref . It can be seen that, even when the voltage mode digital power amplifier supplies power to a non-linear load, the total harmonic distortion rate of the output voltage still reaches 1.74%, which shows strong system robustness.  Figure 11 shows the waveforms of Vo and its reference Voref. It can be seen that, even when the voltage mode digital power amplifier supplies power to a non-linear load, the total harmonic distortion rate of the output voltage still reaches 1.74%, which shows strong system robustness.

Conclusions
A cascaded multilevel inverter provides an effective way to increase the capacity o the digital power amplifier. In this paper, a load observer is designed for the voltage mode digital power amplifier employing CFNPCI topology, which could estimate the output current online without configuring the output current sensor, thus reducing the hardware cost. On this basis, an MMPC is proposed, which could completely avoid cyclic calculation and comparison of the system cost function, so the amount of calculation o the controller can be significantly reduced. The test results show that the TMPC takes 503 µs to run once, while the MMPC only takes 6.9 µs to run once. In addition, the experi mental results show that the total harmonic distortion rate of the output voltage is only 0.84% in the steady state experiment, both the load observer and the MMPC could track the step change load and reference within 0.4ms in the dynamic experiment, and the tota harmonic distortion rate of the output voltage can still reach 1.74% even when the digita power amplifier supplies power for diode rectifier bridge load.

Conclusions
A cascaded multilevel inverter provides an effective way to increase the capacity of the digital power amplifier. In this paper, a load observer is designed for the voltage mode digital power amplifier employing CFNPCI topology, which could estimate the output current online without configuring the output current sensor, thus reducing the hardware cost. On this basis, an MMPC is proposed, which could completely avoid cyclic calculation and comparison of the system cost function, so the amount of calculation of the controller can be significantly reduced. The test results show that the TMPC takes 503 µs to run once, while the MMPC only takes 6.9 µs to run once. In addition, the experimental results show that the total harmonic distortion rate of the output voltage is only 0.84% in the steady state experiment, both the load observer and the MMPC could track the step change load and reference within 0.4ms in the dynamic experiment, and the total harmonic distortion rate of the output voltage can still reach 1.74% even when the digital power amplifier supplies power for diode rectifier bridge load.

Abbreviations
All the parameters related to equations are defined in the following