Design and Analysis of K-Band Single-Pole Double-Throw Switches Based on GaAs Technology

: Two K-band switch circuits, each consisting of a single-pole double-throw (SPDT) switch, have been built using a 0.15 µ m GaAs process. One circuit utilizes diode techniques while the other utilizes field effect transistor (FET) techniques. The diode single-pole double-throw switches that have been devised exhibit exceptional linearity and are capable of withstanding high power levels. The switches exhibit a return loss of 10 dB or higher, an insertion loss of 3 dB or lower, and operate within a frequency range of 19 GHz to 25 GHz. They have a compact design with a core size of only 1.05 mm 2 and consume a total power of 136.8 mW. The FET SPDT switch circuits are created utilizing a parallel–parallel quarter-wavelength transmission line architecture. This design allows for a higher power output compared to using a diode. The transistorized single-pole double-throw switch circuit is designed using a parallel–parallel quarter-wavelength transmission line architecture. This design ensures a low insertion loss. By adjusting the length of the transmission line, the circuit can operate in both frequency bands; the K-band and Ka-band.


Introduction
As time passes, switching circuits are increasingly used in millimeter-wave systems such as radar, communication, and measurement to turn on and off certain signals [1].The microwave switch is a common microwave control circuit and is an important component in radar and measurement systems [2,3].To avoid a transmission distortion between the antenna end and the receiving and transmitting ends, as well as a distortion induced by reflection at the antenna end by its own terminal, the switch must have a consistent insertion loss and reflection loss during its operation.Radio frequency (RF) switches can be broadly classified into two main categories: transistor switches and diode switches [4][5][6].While the diode switch requires a DC bias voltage for it to open and close, unlike the transistor switch, it can handle more power in signal transmission [7].The diode switch outperforms the transistor switch in terms of both switching characteristics due to the impact of the beginning resistance on switch isolation and the effect of the off-state capacitance on insertion loss [8].
Within the transceiver architecture, the antenna will transfer the received signal to the input terminal of the low noise amplifier.It is necessary to ensure that the input signal does not pass through to the power amplifier.Thus, in relation to the criteria for switching characteristics, it is necessary for the switch to possess a minimal insertion loss in order to prevent an excessive attenuation of the input signal, and the low noise amplifier being unable to precisely identify the signal.Simultaneously, the switch must possess a high level of linearity in order to prevent the signal power of the power amplifier from diminishing Crystals 2024, 14, 657 2 of 17 as a result of saturation during output [9].This study presents the design of two types of single-pole double-throw switches specifically for K-band applications.The first type of switch employs diodes as the means of switching.Applying a forward bias voltage to the diode will activate it.Applying a reverse bias voltage causes the diode to deactivate.The length of the selected secondary tube can only be altered by modifying its gate width and the quantity of parallel diodes, due to limitations imposed by the process.Increasing the total area of the diode decreases the on-resistance, which helps to reduce the insertion loss.However, it also increases the on-capacitance, resulting in a leakage of current while the switch is off and diminishing the isolation of the switch [10].The second type of switch employs transistors as a means of switching and utilizes the impedance conversion of the quarter-wavelength transmission line as a method of matching to achieve the circuit signal path switching.The frequency band that is matched is directly determined by the length of the transmission line.The switch is capable of operating in both the K band and the Ka band [11].

Theoretical Analysis and Circuit Design 2.1. Theoretical Analysis of Quarter-Wavelength Transmission Lines
The transmission line model assumes the presence of a load at the terminal that differs from the characteristic impedance of the transmission line.As a result, the electromagnetic wave will be reflected from the terminal back to the source [12].At the input end of the transmission line, the combination of the reflected voltage and the original voltage, as well as the difference between the reflected current and the original current, will result in a modified input impedance.This modified impedance deviates from the original impedance characteristic determined by the length of the transmission line.The new input impedance can be mathematically expressed as In the formula, γ is the diffusion constant, which does not cause particularly large losses under a very short transmission line length, and the diffusion constant can be regarded as a purely imaginary Phase constant i β.Therefore, the above formula can also be expressed as β is the Angular wave number, and in a quarter-wavelength transmission line, β = 2π λ , l = λ 4 , and βl = π 2 .Therefore, the input impedance can be changed to the following formula The following result is According to Formula (4), when an open circuit goes through a quarter-wavelength transmission line, it is considered as a short-circuited circuit at the input point.On the other hand, if a short-circuited circuit passes through a quarter-wavelength transmission line, it is seen as an open circuit at the input point.

Design of K-Band Diode SPDT Switch
The K-band diode single-pole double-throw switching circuit, as described in this paper, is depicted in Figure 1.The RF IN port is the central connection to the antenna.Port1 and Port2 are the connections to the power amplifier and low noise amplifier, respectively.D1-D4 are diodes with the dimensions of 20 µm × 2. L1-L7 are the ring inductors used for the impedance matching.C1-C4 are the DC block capacitors.BIAS1 and BIAS2 represent two distinct direct current (DC) bias points.BIAS1 can control the switching states of D3 and D4, whereas BIAS2 can control the switching states of D1 and D2.

Design of K-Band Diode SPDT Switch
The K-band diode single-pole double-throw switching circuit, as described in this paper, is depicted in Figure 1.The RF IN port is the central connection to the antenna.Port1 and Port2 are the connections to the power amplifier and low noise amplifier, respectively.D1-D4 are diodes with the dimensions of 20 µm × 2. L1-L7 are the ring inductors used for the impedance matching.C1-C4 are the DC block capacitors.BIAS1 and BIAS2 represent two distinct direct current (DC) bias points.BIAS1 can control the switching states of D3 and D4, whereas BIAS2 can control the switching states of D1 and D2.When the RF input signal is sent from the RF IN to PORT1, BIAS1 applies a positive bias voltage to activate the D3 and D4 diodes, while a negative bias voltage is sent to the BIAS2 side to deactivate the D1 and D2 diodes.Currently, the input signal is transmi ed straight from the RF IN to PORT1 using diode D3.Despite the activation of diode D4 in this working scenario, the inductor L6 effectively prevents the high-frequency signal from being discharged to the ground.Additionally, the purpose of the L2 inductor is to safeguard the power supply by blocking the flow of the RF signal into it, thereby preventing any potential harm.The placement of C1 and C4 in the center of the circuit ensures that the bias voltage on both sides remains independent of each other.On the other hand, C2 and C3 are included to prevent the transmission of DC signals to the measuring instrument, which might potentially cause damage.The D1 and D3 diodes currently determine the insertion loss and the degree of isolation of this circuit by allowing the RF signal to flow through them.Given that the circuit described in this work is symmetrical, the RF input signal can be successfully processed by simply altering the voltage of BIAS1 and BIAS2 when it is delivered to PORT2.

Design of K-Band FET SPDT Switch
The circuit employs a GaAs pHEMT 0.15 µm process transistor as the switching component to construct a single-pole double-throw switching circuit, as depicted in Figure 2, which represents the circuit's structural diagram as described in this work.Within the diagram, PORT1 is linked to the antenna terminal, PORT2 is linked to the low noise amplifier, and PORT3 is linked to the power amplifier.TL1 to TL4 refer to the quarter-wavelength double-layer metal transmission lines that have been specifically designed to match the frequencies of 20 GHz for PORT2 and 30 GHz for PORT3.M1 to M4 are GaAs pHEMT transistors, and the biasing transistor is activated or deactivated by manipulating the voltage of VG1, VG2, VM1, and VM2.The size of the transistor directly affects its on-resistance and off-capacitance.If the area is too small, the on-resistance increases, leading to inadequate isolation.Conversely, if the area is too large, the closing capacitor becomes too large to function as a low-pass filter, causing the circuit's overall characteristics to be weakened at high frequencies.Ultimately, a transistor size of NoF = 2 was selected.C1-C3 serve as DC barrier capacitors to impede the flow of current into the instrument.A bypass capacitor, known as CB, serves the purpose of safeguarding the power supply by obstructing the flow of RF impulses that could potentially lead to harm.RG functions as a gate resistor and serves the additional purpose of blocking the RF signals from entering the power supply.The resistance R is utilized to achieve a 50Ω match at the isolation termination.When the RF input signal is sent from the RF IN to PORT1, BIAS1 applies a positive bias voltage to activate the D3 and D4 diodes, while a negative bias voltage is sent to the BIAS2 side to deactivate the D1 and D2 diodes.Currently, the input signal is transmitted straight from the RF IN to PORT1 using diode D3.Despite the activation of diode D4 in this working scenario, the inductor L6 effectively prevents the high-frequency signal from being discharged to the ground.Additionally, the purpose of the L2 inductor is to safeguard the power supply by blocking the flow of the RF signal into it, thereby preventing any potential harm.The placement of C1 and C4 in the center of the circuit ensures that the bias voltage on both sides remains independent of each other.On the other hand, C2 and C3 are included to prevent the transmission of DC signals to the measuring instrument, which might potentially cause damage.The D1 and D3 diodes currently determine the insertion loss and the degree of isolation of this circuit by allowing the RF signal to flow through them.Given that the circuit described in this work is symmetrical, the RF input signal can be successfully processed by simply altering the voltage of BIAS1 and BIAS2 when it is delivered to PORT2.

Design of K-Band FET SPDT Switch
The circuit employs a GaAs pHEMT 0.15 µm process transistor as the switching component to construct a single-pole double-throw switching circuit, as depicted in Figure 2, which represents the circuit's structural diagram as described in this work.Within the diagram, PORT1 is linked to the antenna terminal, PORT2 is linked to the low noise amplifier, and PORT3 is linked to the power amplifier.TL1 to TL4 refer to the quarter-wavelength double-layer metal transmission lines that have been specifically designed to match the frequencies of 20 GHz for PORT2 and 30 GHz for PORT3.M1 to M4 are GaAs pHEMT transistors, and the biasing transistor is activated or deactivated by manipulating the voltage of VG1, VG2, VM1, and VM2.The size of the transistor directly affects its on-resistance and off-capacitance.If the area is too small, the on-resistance increases, leading to inadequate isolation.Conversely, if the area is too large, the closing capacitor becomes too large to function as a low-pass filter, causing the circuit's overall characteristics to be weakened at high frequencies.Ultimately, a transistor size of NoF = 2 was selected.C1-C3 serve as DC barrier capacitors to impede the flow of current into the instrument.A bypass capacitor, known as CB, serves the purpose of safeguarding the power supply by obstructing the flow of RF impulses that could potentially lead to harm.RG functions as a gate resistor and serves the additional purpose of blocking the RF signals from entering the power supply.The resistance R is utilized to achieve a 50Ω match at the isolation termination.
When the signal transitions from PORT1 to PORT2, the bias voltage is adjusted to deactivate the M1 and M3 transistors, putting them in an open state, while activating the M2 transistor.Formula (4) indicates that the impedance is short-circuited from PORT1 to PORT2 and open in the direction of PORT3.The signal is transmitted from PORT1 to PORT2.Currently, the control M4 transistor is functioning in the linear area, allowing it to be considered as a resistor.Additionally, the 50Ω resistance of PORT3 is adjusted to match the impedance.In contrast, to transmit the PORT1 signal to PORT3, the bias voltage functions in a contrary manner to the one explained earlier.In this case, transistors M2 and M4 are deactivated, while M1 is activated to regulate M3, ensuring it behaves as a resistor in the linear area.The signal is transmitted from PORT1 to PORT3.

K-Band Diode SPDT Switch Simulation Results
When the P1 to P2 channels are activated, the voltage across BIAS1(VA) is 1.5 V and the voltage across BIAS2(VB) is −2 V.The current flowing through VA is 91.2 mA and there is no current flowing through VB.The overall power usage is 136.8 mW.When the P1 to P3 channel is activated, the voltage at VA is −2 V and at VB is 1.5 V.The current passing through VA is 0 mA and through VB is 91.2 mA.The overall power usage is 136.8 mW.The S-parameter simulation commences at a frequency of 100 MHz and progressively rises to 50 GHz, with intervals of 100 MHz.
Upon opening the P1 to P2 path, the switching circuit parameters outlined in this study are simulated, and the resulting simulation outcomes are depicted in Figure 3, where Figure 3a is the simulation result diagram for the return loss.The simulation result of the insertion loss and isolation is shown in Figure 3b.In the K-band, the return loss of both the input and the output is larger than 8 dB.Within the K-band, the insertion loss is below 4 dB, and the isolation exceeds 13 dB.The simulation result of the circuit's third-order intercept point is shown in Figure 3c.The simulation is conducted at a frequency of 20 GHz, with a channel spacing of 5 MHz, and a power level of 37 dBm.When the signal transitions from PORT1 to PORT2, the bias voltage is adjusted to deactivate the M1 and M3 transistors, pu ing them in an open state, while activating the M2 transistor.Formula (4) indicates that the impedance is short-circuited from PORT1 to PORT2 and open in the direction of PORT3.The signal is transmi ed from PORT1 to PORT2.Currently, the control M4 transistor is functioning in the linear area, allowing it to be considered as a resistor.Additionally, the 50Ω resistance of PORT3 is adjusted to match the impedance.In contrast, to transmit the PORT1 signal to PORT3, the bias voltage functions in a contrary manner to the one explained earlier.In this case, transistors M2 and M4 are deactivated, while M1 is activated to regulate M3, ensuring it behaves as a resistor in the linear area.The signal is transmi ed from PORT1 to PORT3.

K-Band Diode SPDT Switch Simulation Results
When the P1 to P2 channels are activated, the voltage across BIAS1(VA) is 1.5 V and the voltage across BIAS2(VB) is −2 V.The current flowing through VA is 91.2 mA and there is no current flowing through VB.The overall power usage is 136.8 mW.When the P1 to P3 channel is activated, the voltage at VA is −2 V and at VB is 1.5 V.The current passing through VA is 0 mA and through VB is 91.2 mA.The overall power usage is 136.8 mW.The S-parameter simulation commences at a frequency of 100 MHz and progressively rises to 50 GHz, with intervals of 100 MHz.
Upon opening the P1 to P2 path, the switching circuit parameters outlined in this study are simulated, and the resulting simulation outcomes are depicted in Figure 3, where Figure 3a is the simulation result diagram for the return loss.The simulation result of the insertion loss and isolation is shown in Figure 3b.In the K-band, the return loss of both the input and the output is larger than 8 dB.Within the K-band, the insertion loss is below 4 dB, and the isolation exceeds 13 dB.The simulation result of the circuit's thirdorder intercept point is shown in Figure 3c.The simulation is conducted at a frequency of 20 GHz, with a channel spacing of 5 MHz, and a power level of 37 dBm.Upon opening the P1 to P3 channel, the switching circuit parameters outlined in this work are simulated, and the resulting simulation data are presented in Figure 4.The return loss simulation result diagram is represented by Figure 4a, and shows that both the input and output return loss in the K-band are more than 8 dB. Figure 4b shows the insertion loss and isolation simulation, where the isolation exceeds 13 dB and the insertion loss is less than 4 dB in the K-band.Figure 4c shows the simulation result for the circuit's thirdorder intercept point, which is 39 dBm and is simulated at a frequency of 20 GHz with a channel interval of 5 MHz.Upon opening the P1 to P3 channel, the switching circuit parameters outlined in this work are simulated, and the resulting simulation data are presented in Figure 4.The return loss simulation result diagram is represented by Figure 4a, and shows that both the input and output return loss in the K-band are more than 8 dB. Figure 4b shows the insertion loss and isolation simulation, where the isolation exceeds 13 dB and the insertion loss is less than 4 dB in the K-band.Figure 4c shows the simulation result for the circuit's third-order intercept point, which is 39 dBm and is simulated at a frequency of 20 GHz with a channel interval of 5 MHz.Upon opening the P1 to P3 channel, the switching circuit parameters outlined in this work are simulated, and the resulting simulation data are presented in Figure 4.The return loss simulation result diagram is represented by Figure 4a, and shows that both the input and output return loss in the K-band are more than 8 dB. Figure 4b shows the insertion loss and isolation simulation, where the isolation exceeds 13 dB and the insertion loss is less than 4 dB in the K-band.Figure 4c shows the simulation result for the circuit's thirdorder intercept point, which is 39 dBm and is simulated at a frequency of 20 GHz with a channel interval of 5 MHz.

K-Band Diode SPDT FET Simulation Results
During the transfer of the signal from P1 to P2, the input bias voltages for VG1, VG2, VM1, and VM2 are 0 V, −3 V, −0.9 V, and −2.1 V, respectively.The chip's total current is only a few nA, and the overall power consumption is nearly nothing.The S-parameter simulation commences at a frequency of 100 MHz and incrementally rises to 50 GHz, with intervals of 100 MHz.Upon opening the circuit, the P1 to P2 pathway is activated, leading to the simulation of the parameters of the switching circuit discussed in this study.The outcomes of the simulation are depicted in Figure 5. Figure 5a depicts the simulation results of the return loss.Figure 5b shows the simulation results for the insertion loss and isolation.Figure 5c displays the simulation results for the third-order intercept point of the circuit.The simulation was conducted at an operating frequency of 20 GHz with a channel interval of 5 MHz. (a)

K-Band Diode SPDT FET Simulation Results
During the transfer of the signal from P1 to P2, the input bias voltages for VG1, VG2, VM1, and VM2 are 0 V, −3 V, −0.9 V, and −2.1 V, respectively.The chip's total current is only a few nA, and the overall power consumption is nearly nothing.The S-parameter simulation commences at a frequency of 100 MHz and incrementally rises to 50 GHz, with intervals of 100 MHz.Upon opening the circuit, the P1 to P2 pathway is activated, leading to the simulation of the parameters of the switching circuit discussed in this study.The outcomes of the simulation are depicted in Figure 5. Figure 5a depicts the simulation results of the return loss.Figure 5b shows the simulation results for the insertion loss and isolation.Figure 5c displays the simulation results for the third-order intercept point of the circuit.The simulation was conducted at an operating frequency of 20 GHz with a channel interval of 5 MHz.

K-Band Diode SPDT FET Simulation Results
During the transfer of the signal from P1 to P2, the input bias voltages for VG1, VG2, VM1, and VM2 are 0 V, −3 V, −0.9 V, and −2.1 V, respectively.The chip's total current is only a few nA, and the overall power consumption is nearly nothing.The S-parameter simulation commences at a frequency of 100 MHz and incrementally rises to 50 GHz, with intervals of 100 MHz.Upon opening the circuit, the P1 to P2 pathway is activated, leading to the simulation of the parameters of the switching circuit discussed in this study.The outcomes of the simulation are depicted in Figure 5. Figure 5a depicts the simulation results of the return loss.Figure 5b shows the simulation results for the insertion loss and isolation.Figure 5c displays the simulation results for the third-order intercept point of the circuit.The simulation was conducted at an operating frequency of 20 GHz with a channel interval of 5 MHz.When the circuit is opened, the path from P1 to P3 is activated, and the characteristics of the switching circuit outlined in this work are simulated.The simulation results may be seen in Figure 6. Figure 6a displays the diagram of the simulation result for the return loss.Figure 6b shows the simulation results for the insertion loss and isolation.Figure 6c presents the simulation result for the third-order cut-off point of the circuit, which was simulated at a frequency of 30 GHz with a channel interval of 5 MHz.When the circuit is opened, the path from P1 to P3 is activated, and the characteristics of the switching circuit outlined in this work are simulated.The simulation results may be seen in Figure 6. Figure 6a displays the diagram of the simulation result for the return loss.Figure 6b shows the simulation results for the insertion loss and isolation.Figure 6c presents the simulation result for the third-order cut-off point of the circuit, which was simulated at a frequency of 30 GHz with a channel interval of 5 MHz.When the circuit is opened, the path from P1 to P3 is activated, and the characteristics of the switching circuit outlined in this work are simulated.The simulation results may be seen in Figure 6. Figure 6a displays the diagram of the simulation result for the return loss.Figure 6b shows the simulation results for the insertion loss and isolation.Figure 6c presents the simulation result for the third-order cut-off point of the circuit, which was simulated at a frequency of 30 GHz with a channel interval of 5 MHz.

Measured Results and Discussion
The implementation of the K-band diode and FET SPDT switch chips is achieved using a 0.15 GaAs pHEMT technology.The chip photographs are depicted in Figures 7  and 8, and the chips have a final area of 1 mm × 2 mm.

Measured Results and Discussion
The implementation of the K-band diode and FET SPDT switch chips is achieved using a 0.15 GaAs pHEMT technology.The chip photographs are depicted in Figures 7 and 8, and the chips have a final area of 1 mm × 2 mm.

Measured Results and Discussion
The implementation of the K-band diode and FET SPDT switch chips is achieved using a 0.15 GaAs pHEMT technology.The chip photographs are depicted in Figures 7  and 8, and the chips have a final area of 1 mm × 2 mm.

Measured Results and Discussion
The implementation of the K-band diode and FET SPDT switch chips is achieved using a 0.15 GaAs pHEMT technology.The chip photographs are depicted in Figures 7  and 8, and the chips have a final area of 1 mm × 2 mm.been specifically created for testing purposes in this research study.On either side of the circuit, G-S-G and G-S-G-S-G are directly mounted on the wafer.The Agilent N5247A PNA-X (Santa Clara, CA, USA) is a device used for analyzing microwave networks.Simultaneous measurements can be taken for the return loss, gain, and reverse isolation of the three ports.Prior to the test, the measuring line is calibrated using the test piece, and the frequency width is fine-tuned to 100 Hz in order to enhance the precision of the measurement.When conducting tests on the diode single-pole double-throw switch, it is important to follow a specific sequence.First, the power supply must be turned on.For testing from P1 to P2, the voltage should be turned on in the order of VA and VB, followed by the testing of the S-parameter.Conversely, when testing from P1 to P3, the voltage should be turned on in the order of VB and VA, and then the S-parameter can be tested.
Crystals 2024, 14, x FOR PEER REVIEW 9 of 17 Figure 9 depicts the utilization of the S-parameter test platform for this particular single-pole double-throw switch.In the diagram, DUT refers to the circuit chip that has been specifically created for testing purposes in this research study.On either side of the circuit, G-S-G and G-S-G-S-G are directly mounted on the wafer.The Agilent N5247A PNA-X (Santa Clara, CA, USA) is a device used for analyzing microwave networks.Simultaneous measurements can be taken for the return loss, gain, and reverse isolation of the three ports.Prior to the test, the measuring line is calibrated using the test piece, and the frequency width is fine-tuned to 100 Hz in order to enhance the precision of the measurement.When conducting tests on the diode single-pole double-throw switch, it is important to follow a specific sequence.First, the power supply must be turned on.For testing from P1 to P2, the voltage should be turned on in the order of VA and VB, followed by the testing of the S-parameter.Conversely, when testing from P1 to P3, the voltage should be turned on in the order of VB and VA, and then the S-parameter can be tested.Figure 10 displays the test platform used for assessing linearity.The linearity test involves two parameters, namely the 1 dB compression point and the input third-order intercept point.Due to the double-ended nature of the linearity test, a 50Ω terminal resistor is employed as a virtual resistor at the closed port.The Agilent E8257D (Santa Clara, CA, USA) is a device that generates signals.Initially, the functionality of the diode single-pole double-throw switch is assessed.During the testing of the 1 dB compression point, the output of the Agilent E8257D is connected directly to the P1 port of the circuit described in this paper.The open end of this circuit, either P1 or P2, is then connected directly to the Agilent E4448A (Santa Clara, CA, USA) spectrum analyzer.The voltage opening sequence of the power supply is dictated by the opening end.If the P2 end is opened, the sequence is VA followed by VB.If the P3 terminal is opened, the sequence is VB followed by VA.After that, the signal generator is configured to generate output signals for testing.Next, we evaluated the functionality of the FET single-pole double-throw switch.During the testing of the 1 dB compression point, the output of the Agilent E8257D is connected directly to the P1 port of the circuit described in this paper.The open end of this circuit (P2 or P3) is then connected directly to the Agilent E4448A spectrum analyzer.The power supply's voltage switching sequence is determined by the switching end.When P2 is turned on, the voltage switching sequence consists of VG1, VM1, VG2, and VM2.When P3 is enabled, it follows the sequence of VG2, VM2, VG1, and VM1.After that, the signal generator is configured to generate output signals for testing.For the third-order cut-off point test, two Agilent E8257D instruments are used as the output sources.To combine the power from these sources, a power divider is required between the two instruments.The combined signal is then connected to the P1 terminal of the circuit, and the received signal is tested at the output terminal of the circuit (P2 or P3).
To combine the power from these sources, a power divider is required between the two instruments.The combined signal is then connected to the P1 terminal of the circuit, and the received signal is tested at the output terminal of the circuit (P2 or P3).The test results for a diode single-pole double-throw switch are outlined as follows.Upon opening the P1 to P2 channels, the VA voltage measures 1.5 V while the VB voltage measures −2 V. Upon opening the P1 to P3 channel, the VA and VB voltages measure −2 V and 1.5 V, respectively.During the test, a current of 65 mA is observed to flow through the pad with a positive voltage, however no current flows through the pad with a negative voltage.The combined power consumption of the circuits in both operational modes is 97.5 milliwa s.Upon opening the P1 to P2 path, the switching circuit parameters outlined in this paper are examined and the findings are presented in Figure 11.Subsequently, Figure 11a displays the chart of the return loss results, Figure 11b illustrates the diagram of the test results for the insertion loss and isolation, and Figure 11c showcases the test result of the 1 dB compression point at the operating frequency of 20 GHz.In the obtained measurement result, the value has reached the maximum frequency that the measuring instrument can output, but it has not yet reached the point where the power is compressed by 1 dB.Therefore, we can only conclude that the value is greater than 15 dBm. Figure 11d represents the diagram illustrating the measurement result of the third-order intercept point.The circuit's working frequency throughout the test is 20 GHz, with a channel spacing of 5 MHz.The third-order cut-off point, computed using the heterodyne method, is 28 dBm.The test results for a diode single-pole double-throw switch are outlined as follows.Upon opening the P1 to P2 channels, the VA voltage measures 1.5 V while the VB voltage measures −2 V. Upon opening the P1 to P3 channel, the VA and VB voltages measure −2 V and 1.5 V, respectively.During the test, a current of 65 mA is observed to flow through the pad with a positive voltage, however no current flows through the pad with a negative voltage.The combined power consumption of the circuits in both operational modes is 97.5 milliwatts.Upon opening the P1 to P2 path, the switching circuit parameters outlined in this paper are examined and the findings are presented in Figure 11.Subsequently, Figure 11a displays the chart of the return loss results, Figure 11b illustrates the diagram of the test results for the insertion loss and isolation, and Figure 11c showcases the test result of the 1 dB compression point at the operating frequency of 20 GHz.In the obtained measurement result, the value has reached the maximum frequency that the measuring instrument can output, but it has not yet reached the point where the power is compressed by 1 dB.Therefore, we can only conclude that the value is greater than 15 dBm. Figure 11d represents the diagram illustrating the measurement result of the third-order intercept point.The circuit's working frequency throughout the test is 20 GHz, with a channel spacing of 5 MHz.The third-order cut-off point, computed using the heterodyne method, is 28 dBm.
When the P1 to P3 path is activated, the switching circuit described in this paper undergoes testing for various parameters.The test results are presented in Figure 12, with Figure 12a representing the chart for the return loss results, Figure 12b depicting the diagram for the test results of the insertion loss and isolation, and Figure 12c illustrating the comparison between the test results of the 1 dB compression point and the simulation results at the operating frequency of 23 GHz.In the obtained results, the value of the measured quantity reaches the maximum frequency that the measuring instrument can output, but it does not yet reach the point where the power is compressed by 1 dB.Therefore, it can only be concluded that the value is greater than 15 dBm. Figure 12d shows the diagram representing the measured results of the third-order intercept point.The circuit's working frequency throughout the test is 23 GHz, with a channel interval of 5 MHz.The third-order cut-off point, computed using the heterodyne method, is 39.5 dBm.
The test results for a transistor single-pole double-throw switch are outlined as follows.When the P1 to P2 channels are activated, the voltages of VG1, VM1, VG2, and VM2 are measured to be −2.1 V, 0 V, −2.1 V, and −0.9 V accordingly.Meanwhile, the chip's current is only a few nA, and its power consumption is almost negligible.When the P1 to P3 channel is activated, the voltages of VG1, VM1, VG2, and VM2 are 0 V, −3 V, −0.9 V, and −2.1 V, respectively.Simultaneously, the chip's overall current is merely a few nA, and the entire power consumption is nearly negligible.Upon opening the P1 to P2 path, the parameters of the switching circuit outlined in this study are examined and the findings are displayed in Figure 13. Figure 13a  When the P1 to P3 path is activated, the switching circuit described in this p undergoes testing for various parameters.The test results are presented in Figure 12, Figure 12a representing the chart for the return loss results, Figure 12b depicting th gram for the test results of the insertion loss and isolation, and Figure 12c illustratin comparison between the test results of the 1 dB compression point and the simul results at the operating frequency of 23 GHz.In the obtained results, the value of the m ured quantity reaches the maximum frequency that the measuring instrument can ou but it does not yet reach the point where the power is compressed by 1 dB.Therefo can only be concluded that the value is greater than 15 dBm. Figure 12d shows the gram representing the measured results of the third-order intercept point.The cir working frequency throughout the test is 23 GHz, with a channel interval of 5 MHz third-order cut-off point, computed using the heterodyne method, is 39.5 dBm.The test results for a transistor single-pole double-throw switch are outlined as follows.When P1 to P2 channels are activated, the voltages of VG1, VM1, VG2, and VM2 are measured to be −2.1 V, 0 V, −2.1 V, and −0.9 V accordingly.Meanwhile, the chip's current is only a few nA, and its power consumption is almost negligible.When the P1 to P3 channel is activated, the voltages of VG1, VM1, VG2, and VM2 are 0 V, −3 V, −0.9 V, and −2.1 V, respectively.Simultaneously, the chip's overall current is merely a few nA, and the Upon opening the P1 to P3 path, the parameters of the switching circuit outlined in this work are examined and the findings are displayed in Figure 14. Figure 14a  Upon opening the P1 to P3 path, the parameters of the switching circuit outlined in this work are examined and the findings are displayed in Figure 14. Figure 14a  Upon opening the P1 to P3 path, the parameters of the switching circuit outlined in this work are examined and the findings are displayed in Figure 14.To conduct a thorough performance comparison between the two K-band single-pole double-throw switches and the other literature sources, the relevant characteristics have been compiled in Table 1.The optimal coefficient figure-of-merit (FOM) is expressed as follows: Return Loss refers to the loss of power in a signal that is reflected back from a device or system.Insertion Loss, on the other hand, refers to the loss of power that occurs when a signal is inserted into a device or system.Lastly, Area refers to the size or dimensions of a chip.
When compared to a diode switching circuit, this circuit has a smaller chip area and a greater optimization coefficient.Transistor circuits exhibit reduced insertion losses and increased signal isolation.The input return loss of the two is comparable, and the figure of merit (FOM) value is higher than that reported in other research.To conduct a thorough performance comparison between the two K-band single-pole double-throw switches and the other literature sources, the relevant characteristics have been compiled in Table 1.The optimal coefficient figure-of-merit (FOM) is expressed as follows: FOM = Return Loss Insertion Loss × Area (5) Return Loss refers to the loss of power in a signal that is reflected back from a device or system.Insertion Loss, on the other hand, refers to the loss of power that occurs when a signal is inserted into a device or system.Lastly, Area refers to the size or dimensions of a chip.
When compared to a diode switching circuit, this circuit has a smaller chip area and a greater optimization coefficient.Transistor circuits exhibit reduced insertion losses and increased signal isolation.The input return loss of the two is comparable, and the figure of merit (FOM) value is higher than that reported in other research.

Figure 1 .
Figure 1.Schematic of the diode SPDT switch.

Figure 1 .
Figure 1.Schematic of the diode SPDT switch.

Figure 2 .
Figure 2. Schematic of the FET SPDT switch.

Figure 2 .
Figure 2. Schematic of the FET SPDT switch.

Figure 3 .
Figure 3. Simulated parameters when P1 to P2 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 3 .
Figure 3. Simulated parameters when P1 to P2 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 3 .
Figure 3. Simulated parameters when P1 to P2 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 4 .
Figure 4. Simulated parameters when P1 to P3 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 4 .
Figure 4. Simulated parameters when P1 to P3 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 4 .
Figure 4. Simulated parameters when P1 to P3 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 5 .
Figure 5. Simulated parameters when P1 to P2 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 5 .
Figure 5. Simulated parameters when P1 to P2 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 7 .
Figure 7. Photograph of the K-band diode SPDT Switch.

Figure 8 .
Figure 8. Photograph of the K-band FET SPDT Switch.

Figure 6 .
Figure 6.Simulated parameters when P1 to P3 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 6 .
Figure 6.Simulated parameters when P1 to P3 is open.(a) Simulated return loss results.(b) Simulated insertion loss and isolation results.(c) Simulated third-order intercept point results.

Figure 7 .
Figure 7. Photograph of the K-band diode SPDT Switch.

Figure 8 .
Figure 8. Photograph of the K-band FET SPDT Switch.

Figure 7 .
Figure 7. Photograph of the K-band diode SPDT Switch.

Figure 8 .
Figure 8. Photograph of the K-band FET SPDT Switch.

Figure 8 .
Figure 8. Photograph of the K-band FET SPDT Switch.

Figure 9
Figure 9 depicts the utilization of the S-parameter test platform for this particular single-pole double-throw switch.In the diagram, DUT refers to the circuit chip that has

Figure 10
Figure10displays the test platform used for assessing linearity.The linearity test involves two parameters, namely the 1 dB compression point and the input third-order intercept point.Due to the double-ended nature of the linearity test, a 50Ω terminal resistor is employed as a virtual resistor at the closed port.The Agilent E8257D (Santa Clara, CA, USA) is a device that generates signals.Initially, the functionality of the diode singlepole double-throw switch is assessed.During the testing of the 1 dB compression point, the output of the Agilent E8257D is connected directly to the P1 port of the circuit described in this paper.The open end of this circuit, either P1 or P2, is then connected directly to the Agilent E4448A (Santa Clara, CA, USA) spectrum analyzer.The voltage opening sequence of the power supply is dictated by the opening end.If the P2 end is opened, the sequence is VA followed by VB.If the P3 terminal is opened, the sequence is VB followed by VA.After that, the signal generator is configured to generate output signals for testing.Next, we evaluated the functionality of the FET single-pole double-throw switch.During the testing of the 1 dB compression point, the output of the Agilent E8257D is connected directly to the P1 port of the circuit described in this paper.The open end of this circuit (P2 or P3) is then connected directly to the Agilent E4448A spectrum analyzer.The power supply's voltage switching sequence is determined by the switching end.When P2 is turned on, the voltage switching sequence consists of VG1, VM1, VG2, and VM2.When P3 is enabled, it follows the sequence of VG2, VM2, VG1, and VM1.After that, the signal generator is configured to generate output signals for testing.For the thirdorder cut-off point test, two Agilent E8257D instruments are used as the output sources.

Figure 11 .
Figure 13c displays the test result diagram for the 1 dB compression point at the operating frequency of 20 GHz, with a measured value of 6 dBm; and Figure 13d shows the measured result diagram for the third-order intercept point.The circuit operates at a frequency of 20 GHz during the test.The channel interval is 5 MHz, and the third-order cut-off point is obtained as 19 dBm using the heterodyne method.Crystals 2024, 14, x FOR PEER REVIEW 1

Figure 11 .Figure 12 .
Figure 11.Measured parameters when P1 to P2 is open.(a) Measured return loss results.(b) Measured insertion loss and isolation results.(c) Measured 1 dB compression point results.(d) Measured thirdorder intercept point results.Crystals 2024, 14, x FOR PEER REVIEW 12 of 17

Figure 12 .
Figure 12.Measured parameters when P1 to P3 is open.(a) Measured return loss results.(b) Measured insertion loss and isolation results.(c) Measured 1 dB compression point results.(d) Measured third-order intercept point results.

Figure 13 .
Figure 13.Measured parameters when P1 to P2 is open.(a) Measured return loss results.(b) Measured insertion loss and isolation results.(c) Measured 1 dB compression point results.(d) Measured thirdorder intercept point results.

Figure 13 .
Figure 13.Measured parameters when P1 to P2 is open.(a) Measured return loss results.(b) Measured insertion loss and isolation results.(c) Measured 1 dB compression point results.(d) Measured third-order intercept point results.

Figure 14 .
Figure 14.Measured parameters when P1 to P3 is open.(a) Measured return loss results.(b) Measured insertion loss and isolation results.(c) Measured 1 dB compression point results.(d) Measured thirdorder intercept point results.

Table 1 .
Comparison of the proposed switches.

Table 1 .
Comparison of the proposed switches.