PLC Program Translation for Verification Purposes

Authors

  • Dániel Darvas
    Affiliation

    Department of Measurement and Information Systems, Faculty of Electrical Engineering and Informatics, Budapest University of Technology and Economics, Hungary; European Organization for Nuclear Research (CERN), Geneva, Switzerland

  • István Majzik
    Affiliation

    Department of Measurement and Information Systems, Faculty of Electrical Engineering and Informatics, Budapest University of Technology and Economics, Hungary

  • Enrique Blanco Viñuela
    Affiliation

    European Organization for Nuclear Research (CERN), Geneva, Switzerland

https://doi.org/10.3311/PPee.9743

Abstract

Programmable logic controllers are typically programmed in one of the five languages defined in the IEC 61131 standard. While the ability to choose the appropriate language for each program unit may be an advantage for the developers, it poses a serious challenge to verification methods. In this paper we analyse and compare these languages to show that the ST programming language can efficiently and conveniently represent all PLC languages for formal verification purposes. Furthermore, we provide a translation method from IL to ST programming languages (for the Siemens implementation), together with a sketch of proof for its correctness. This allows the usage of the ST-based PLCverif model checking method for safety PLC programs.

Keywords:

PLC, programming languages, formal verification, semantics

Published Online

2017-05-23

How to Cite

Darvas, D., Majzik, I., Blanco Viñuela, E. “PLC Program Translation for Verification Purposes”, Periodica Polytechnica Electrical Engineering and Computer Science, 61(2), pp. 151–165, 2017. https://doi.org/10.3311/PPee.9743

Issue

Vol. 61 No. 2 (2017)

Section

Articles