Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Abstract


A. Introduction
Integrated circuit designs are becoming more and more complicated these days.Very large-scale integrated (VLSI) is widely used in the design of electrical components containing millions of transistors, such as memory chips and microprocessors.A process known as VLSI is used to pack millions of CMOS transistors onto a single chip in order to produce a microelectronic circuit.Three key factors are speed, area, and power consumption in a VLSI design.The basic and most commonly used arithmetic function is the majority speed-limiting component of many VLSI systems; hence, increasing its speed and performance is essential.Two binary digits added together are the main function of a full-adder cell.In systems that have arithmetic logic units (ALUs), full adders are helpful.Full adders are useful in a wide range of digital electronics and circuits.The adders can be used to perform multiplication.The arithmetic and logical functions of digital systems depend on full adders.To construct integrated circuits, a variety of technologies are available, such as bipolar integrated technology, NMOS, and CMOS [1].MGDI and CMOS technologies are used in this work.Considerations such as transistor sizing, layout optimization, power consumption, signal propagation delay, and overall circuit performance are necessary in the design of complete adders that are CMOS-and MGDI-based.The logic style that is most commonly used is standard CMOS.The main instrument used to create integrated circuits is CMOS technology.One advantage of CMOS circuits is their simple design.The entire circuit is also integrated into the chip because of its high level of integration [2][3].GDI was presented as a potentially effective method for achieving high performance, low chip size, and less design complexity.The GDI technique's drawback is that it cannot provide the full output swing of a desired output state.Most logic operations can be carried out with the fewest transistor ranks by using the GDI approach.In comparison to the CMOS technique, the GDI technique is better suited for configuring high-speed circuit designs with fewer discrete components [4].Related works are also described below.Kamlesh Kukreti, Prashant Kumar, Shivangi Barthwal, Amit Juyal, and Alankrita Joshi created performance analysis of full adder based on Domino logic technique.One-bit full adder circuit was optimized using CMOS based logic and domino-based logic on Cadence Virtuoso based on 0.18um technology having the supply voltage of 3V.According to estimates, the one-bit full-adder circuit based on Domino logic required 28.57% less space and introduced 47.36% less delay than the one-bit fulladder circuit based on CMOS logic [5].Arjun Sehrawat, Vandana Khanna, Kushal Jindal designed a comparative study of CMOS logic and modified GDI technique for basic logic gates and code convertor.Using 90 nm technology, they discovered that modified GDI technique comes out to be a good substitute for existing CMOS technology that can be used in high performance and more complex digital circuits and designs [6].Merrin Mary Solomon, Neeraj Gupta, Rashmi Gupta developed a high speed adder using GDI technique.They estimated that full adder designs in terms of area, delay and power dissipation.In addition, this design will have an improved speed and also the efficiency of the system is more compared to all the conventional techniques [7].
In this study, a full-adder is designed and examined using conventional CMOS and MGDI methods.The full-adder circuit was first constructed using a NAND and XOR CMOS and MGDI.Adder circuits were built and analyzed using CMOS and MGDI technology at 90 nm.The propagation delay has been calculated for 90 nm technology using Cadence Virtuoso simulation.Following that, the timing waveform, power consumption, and propagation delay time of the entire design are examined.For better comprehension, the performance analysis table and graph are finally shown.
There are five sections in this paper.A general introduction to full-adder IC design is given in Section A. The modeling of the full-adder architecture and theory is covered in Section B. The CMOS and MGDI schematic is implemented in Section C. The simulation results and analysis of the system are described in Section D, while the conclusion is provided in Section E.

B. Modeling of the Full-Adder Design
CMOS and MGDI are technologies used in the fabrication of integrated circuits.It is among the most widely used technologies for constructing digital logic circuits and microprocessors.The full-adder is built with the XOR and NAND logic circuits.The modeling of the full-adder provided by the use of Quartus II software.

Full-Adder
A basic full-adder has two outputs: Sum and Cout (carry out), and three inputs A, B, and Cin (carry in).Binary numbers include sum and Cout, as indicated in Table 1.The boolean equations associated with the fundamental logic diagram for a complete full adder are shown below.Logic gates XOR and NAND are fundamental building blocks that are integrated to make a circuit that can add two binary values with a carry-in input in order to design a full adder [8].The logic diagram of fulladder using XOR and NAND gate is depicted in Figure 1 using Quartus II software.

CMOS Technology
CMOS technology is a popular semiconductor technology utilized in the creation of digital integrated circuits.Particularly often used options for creating digital circuits is CMOS technology, which has various advantages over alternative technologies.The fact that CMOS circuitry operates more quickly, consumes less power, and is less susceptible to noise and process variations than other types of circuitry is just one of its numerous benefits.Figure 2 illustrates how a static CMOS gate is connected to logic "0" by an NMOS pull-down network (PDN) and logic "1" by a PMOS pull-up network (PUN).The networks are configured such that one is ON and the other is OFF for a specific input pattern [9][10].

Modified Gate Diffusion Input
In digital circuit design, gate diffusion input (GDI) is a method for effectively implementing logic operations utilizing CMOS technology.Compared to conventional CMOS implementations, GDI logic gates allow the development of complicated logic circuits with a lower transistor count.Because of this, they are incredibly effective and versatile for intricate logic systems.An improved version of the GDI technique, modified gate diffusion input (MGDI), is a high-speed and area-efficient design technique.In contrast to the basic GDI cell, where the substrate connections of NMOS and PMOS are connected to the sources of the corresponding gates, the MGDI technique connects the substrates of NMOS and PMOS to ground and VDD, respectively, and connects the gate terminal, the source of PMOS, and the source of NMOS to the input signals, as shown in Figure 3. G, P, and N are the three inputs that make up the cells in Figure 3, where G is the gate terminal and P and N are the source terminals for PMOS and NMOS.The basic GDI cell's source terminals are connected to the PMOS and NMOS substrates, while the MGDI cell's substrates are connected to ground and VDD, respectively.To obtain the intended output, connect the PMOS and NMOS drain terminals [11][12].

C. Creation of Full Adder Design
The schematic for a full-adder utilizing XOR and NAND CMOS-based and MGDI-based architectures is shown in Figures 4 and 5.The CMOS method was used in this design to build the XOR and NAND schematics (6 PMOS and 6 NMOS for XOR and 2 PMOS and 2 NMOS for NAND, respectively).PDN and PUN are connected by a basic structure.Additionally, the MGDI approach was used to produce the XOR and NAND schematics in design (2 PMOS and 2 NMOS for XOR and 2 PMOS and 2 NMOS for NAND, respectively).Using Cadence Virtuoso Tool's 90 nm GPDK technology, all of these schematics were created.A CMOS-based full-adder schematic using 36 transistors (18 PMOS and 18 NMOS) is shown in Figure 6. Figure 7 shows an MGDI-based full-adder schematic made with 20 transistors (10 PMOS and 10 NMOS).Transistor size is expressed as a width/length (W/L) ratio.The W/L ratios of the NMOS and PMOS transistors used in all simulations are 120/100 for NMOS and 120/100 for PMOS.The Cadence Virtuoso, which operates on 90 nm GPDK technology, was used to generate this schematic.

D. Result and Discussion
In this section, performance analyses of full adder designs are discussed.To validate the logic operations, schematic designs are simulated.When there are an odd number of high states in the input, the output "Sum" is high; otherwise, it is low.Similarly, when two or more input states are high, output "Cout" is high.Figures 8 and 9 displays the schematic output timing waveform.After the precise result was obtained, the power analysis waveform simulation results are shown in Figures 10 and 11 below, respectively.The waveform is also simulated with 90 nm technology at 1.8 V supply voltage, and 200 ns stop times, respectively.For all levels, the threshold voltage has been set at 0.9 volts.This voltage marks the point at which power and current start to increase as the supply voltage rises.Operating temperatures have been specified for all designs at 27°C.  2. For high-speed circuit design, it includes the total number of transistors, area efficiency, and delay time.The design and simulations were done with the Cadence Virtuoso.In Figure 14, the full-adder comparison analyses are shown graphically.

E. Conclusion
The main focus of this research work was to use CMOS and MGDI techniques to create a full adder with high-speed performance.The design of a CMOS and MGDI full-adder based on 90 nm GPDK technology at 1.8 V in Cadence Virtuoso Tool has involved a schematic analysis and comparison of surface area, transistor count, and delay.According to the simulation results, the MGDI design technique produces very accurate results with fewer transistors and less delay than the CMOS design.In addition, as compared to CMOS logic, the MGDI technology results found a 79.6172% reduction in delay and a 51.1343% reduction in chip size.So, the MGDI technique is a superior replacement for current CMOS technology in high-performance and sophisticated digital circuits and designs.

F. Acknowledgment
The author wanted to show appreciation to Dr. Tin Tin Hla, Professor and Head, Department of Electronic Engineering, Mandalay Technological University, for her help, encouragement, and kindness in writing this research.

1 Figure 1 .
Figure 1.Logic diagram of full-adder using XOR and NAND gate

Table 2 .
Performance Evaluation of Full Adder Figure 14.Full-Adder Comparative Graph