FPGA Implementation of Mean – Max Membership based Defuzzifier Unit

,


1.INTRODUCTION
The modern concept of fuzzy sets was introduced by Lotfi Zadeh [1][2] in his work "Fuzzy Sets" which described the mathematics of fuzzy set theory nearly three decades ago.Although a relatively new theory, fuzzy logic has been used in many engineering applications because being considered as a simplistic solution available for the specific problems.Fuzzy systems have high potential to understand the systems that are devoid of analytic formulations: complex systems [3][4].
Fuzzification, defuzzification and inference are three important segments of a fuzzy system.However, the fuzzy results generated cannot be used as such to the real time applications, hence it is necessary to convert the fuzzy quantities to crisp for further processing.This can be achieved by using defuzzification process.The defuzzification has the capability to reduce a fuzzy quantity to a crisp single-valued quantity.Defuzzification can also be called as "rounding off" method.Defuzzification reduces the collection of membership function values in to a single sealer quantity [5][6][7][8][9].The various fuzzy systems are realized by different researcher for different applications.The original digital realization of fuzzy inference processor was performed by Toga and Watanabe [10][11].H. Peyravi9+ et al. [12] have proposed reconfigurable inference engine for the analog fuzzy logic controller, based on Mamdani inference technique.J.M. Jou et al. [13], R. d 'Amore [14] and N. E.
Evmorfopoulong et al. [15] have proposed different architecture for the fuzzy inference processor.A significant improvement is reducing power and reducing redundancy has been obtained in these structures.The inference engine performance is an important issue which needs to be addressed.Many researchers have done a work on the defuzzification fuzzy processors.Roberto d"Amore et al [12] has developed a two input one output bit scalable architecture for fuzzy processors.
In this work, we propose a VLSI architecture of a defuzzifier.The defuzzifier is based on (MMM), the simplest and generally used.The proposed architecture is modeled in very high speed hardware description language (VHDL) and implemented in Vertex-4 field programmable gate array (FPGA).In this work, two models have been designed to test the functionality of the proposed fuzzy processor.The defuzzified value has been obtained manually using the MMM technique initially, then the proposed architecture has computed the defuzzified values.

2.DEFUZZIFICATION PROCESS
The fuzzy data obtained from the fuzzification process is not suitable for the real time applications and have to be converted into crisp form.This process is known as defuzzification and it reduces the collection of membership function values into a single quantity.The different defuzzification methods used in literature are max-membership principle, centroid method, weighted average method, mean-max membership, centre of sums, center of largest area, first of maxima or last of maxima.These methods have their own applications, advantages and disadvantages [1][2][3][4]

Y MMM = (1)
Where a and b are the first and last maximum point in the x-axis of defuzzifier respectively.
In this work, we have used a model to study and realize the defuzzification architecture as shown in Figure 2. In this model two rules are being fired and Mamdani implication has been used for inference.We have used aggression of rules, as the overall consequent is being obtained from the two individual consequent in each set.In each set, the minimum of two antecedent membership values is propagated to the consequent as "AND" connective is used between the two antecedents in the rule.The propagated membership value from operations on the antecedents truncates the membership function for the consequent for that rule.The truncated membership functions from each rule are aggregated according to the following equation used for conjunctive system of rules [3].Where uy(y) minimum of (uy 1 , uy 2 , … uy r ) are the principle of fuzzification Each rule comprises of two antecedents (A1, B1 and A2, B2) and one consequent (C1, C2) an is represented as:

3.CALCULATION OF DEFUZZIFIED VALUES
The defuzzified or crisp value for MODEL 1 can be calculated first manually and then using the proposed architecture.It is important that the two values must match; otherwise the proposed architecture is not well designed.In this study, (MMM) is being used to calculate the defuzzified value.
. The researchers have developed various architectures of defuzzifiers depending on what application the fuzzy processor or the fuzzy controller is being designed for.Figure (1) shows the block diagram of a defuzzifier circuit.Volume 10, Issue 3, September 2015 , p.p(79-91) ISSN 1992 -0849 Web Site: www.kujss.comEmail: kirkukjoursci@yahoo.com, kirkukjoursci@gmail.com 82 C1X1, C2X1, C1X2 and C2X2 are the fuzzy inputs to the defuzzifier, which comprises of elements and their associated membership functions.

Figure ( 3 )
again shows the defuzzification for the MODEL 1 as given by Figure 2. The application of equation (1) to Figure 3 will generate the defuzzified value of model 1.The defuzzified value obtained out of MMM defuzzifier.