Automatic Generation of Network Function Accelerators Using Component-Based Synthesis

Authors

  • Sai Teja Nagapuri  New Jersey Institute of Technology, Newark, New Jersey, USA
  • Rajasree Tella  New Jersey Institute of Technology, Newark, New Jersey, USA
  • Meghana Reddy Guntireddygari  New Jersey Institute of Technology, Newark, New Jersey, USA

DOI:

https://doi.org//10.32628/CSEIT2390655

Keywords:

Synapse, Network Function, Component-Based Synthesis, Tofino-Based Switch.

Abstract

The document discusses the development of a compiler called SyNAPSE, which aims to address the challenge of programming for multiple hardware targets in networked systems. It focuses on optimising the performance, efficiency, and resource consumption of networked systems by dividing packet processing across multiple hardware platforms. The key problem it is solving is the difficulty in developing high-performance network functions for multiple platforms, each with its own programming language and hardware features. SyNAPSE aims to provide a solution that allows for 'write once, run anywhere' code that is portable across different platforms and automatically provisioned on the hardware best- suited for the task. It explores a large search space of different mappings of functionality to hardware, allowing for optimization based on programmer- specified objectives such as minimising memory consumption or maximising network throughput.

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Published

2023-12-30

Issue

Section

Research Articles

How to Cite

[1]
Sai Teja Nagapuri, Rajasree Tella, Meghana Reddy Guntireddygari, " Automatic Generation of Network Function Accelerators Using Component-Based Synthesis, IInternational Journal of Scientific Research in Computer Science, Engineering and Information Technology(IJSRCSEIT), ISSN : 2456-3307, Volume 9, Issue 6, pp.297-302, November-December-2023. Available at doi : https://doi.org/10.32628/CSEIT2390655