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Since the publication of this paper, the authors noticed that the affiliation information for Francesco Bertolini, Giovanna Motta, Federica Melle, Valentina Tabanelli and Angelica Calleri was not complete. The correct affiliation is shown below: Division of Haematopathology, IEO European Institute of Oncology IRCCS, Milan, Italy Giovanna Motta, Federica Melle, Valentina Tabanelli, Angelica Calleri and Stefano A. Pileri. Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons. org/licenses/by/4.0/.


TMC2010 Functional Description General Information
The TMC2010 consists of four functional sections: Input registers, an asynchronous multiplier array, an adder, and output registers.The input registers store the two 16-bit numbers which are to be multiplied, and the control lines which control the input numerical format !two's complement or unsigned magnit11rlel.output rounding, accumulation, and subtraction.The round control is used when a single-word output is desired.Each number is independently stored, simplifying multiplication by a constant.The output registers can be preloaded with a constant to provide the sum of

Power
The TMC2010 operates from a single +5 Volt supply.All power and ground lines must be connected.

Name Function vDD
Pos~ive Supply Voltage

Data Inputs
The TMC2010 has two 16-bit two's complement or unsigned magnitude data inputs, labeled X and Y.The Most Significant Bits IMSBsl, denoted X15 and Y15, carry the sign information for the two's complement notation.The remaining bits are denoted X14 through Xo and Y14 through Yo !with Xo and Yo the least Significant Bitsl.Data present at the X and Y inputs

Controls
The TMC2010 has eight control lines.TSX, TSM, and TSL are three-state enable lines for the XTP, the MSP, and the LSP respectively.The output driver is in the high-impedance state when TSX, TSM, or TSL is HIGH, and enabled when the appropriate control is LOW.
PRELoad !PRELI is an active-HIGH control which has several effects when active (see Table 11.First, all output buffers are forced into the high-impedance state.Second, when any or all of TSX, TSM, and TSL are also HIGH, external data present at the output pins will be preloaded into the corresponding section of the output register on the rising edge of CLK P.
Normal data setup and hold times apply both to the logical AND of PREL and the relevant three-state control ITSX, TSM, TSU, and to the data being preloaded.These setup and hold times are with respect to the rising edge of CLK P.
RouNO IRNO) controls the addition of a 1 to the MSB of the LSP for rounding.When RNO is HIGH, a 1 is added to the MSB of the LSP for rounding the product in the MSP and XTP lif appropriate) rather than truncating it.
Two's Complement ITC) controls how the device interprets data on the X and Y inputs.TC HIGH makes both inputs two's complement inputs, while TC LOW makes both inputs magnitude only inputs.1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.functional operation under any of these conditions is NOT implied.2. Applied voltage must be current limited to specified range.3. forcing voltage must be• limited to specified range.4. Current is specified as conventional current flowing into the device.
2. PREL H1 inhibits any change of output register for those outputs in which the three-state control 1s IOW.

Multiplication by a Constant
Multiplication by a constant requires that the constant be loaded into the desired input register, and that the register not be loaded again until a new constant is desired.The multiply

Selection of Numeric Format
Essentially, the difference between integer, mixed, and fractional notation in system design is only conceptual.For example, the TMC2010 does not differentiate between this operation: and this operation: The difference lies only in constant scale factors lin this case, a factor of 8 in the multiplier and multiplicand and a factor of 64 in the product).However, these scale factors do have cycle then consists of loading new data and strobing the output register.
implications for hardware design.Because common good design practice assigns a fixed value to any given line land input and output signals often share the same line), the scale factors determine the connection of the output pins of any multiplier in a system.As a result, only two choices are normally made: integer and fractional notation.If integer notation is used, the Least Significant Bits of the multiplier, multiplicand, and product all have the same value.If fractional notation is used, the Most Significant Bits of the multiplier, multiplicand, and product all have the same value.These formats are illustrated in detail in Figures 1 through 4. The TMC2010 is a high-speed 16 x 16 bit parallel multiplier-accumulator which operates at a 160 nanosecond cycie time imore than 6MHz multiply-accumulate ratei.The input data may be specified as two's complement or unsigned magnitude, yielding a full-precision 32-bit product.Products may be accumulated to a 35-bit result.
Individually clocked input and output registers are provided to maximize system throughput and simplify bus interfacing.These registers are positive-edge -triggered 0-type flip-flops.The result is divided into a 3-bit eXTended Product IXTPI, a 16-bit Most Significant Product IMSPI, and a 16-bit Least Significant Product ILSPl.Individual three-state output ports are provided for the XTP and the MSP; the LSP is multiplexed with the Y input.The output register can be preloaded directly via the output ports.
Built with TRW's state-of-the-art 2-micron CMOS process, the TMC2010 is pin and function compatible with the industry standard TDC1010 and operates with the same speed at one-sixth or less power dissipation, depending on the multiply-accumulate rate.

Functional Block Diagram
x,.

TMC2009 Application Notes
Multiplication By A Constant Multiplication by a constant requires that the constant be loaded into the desired input register, and that the register not be loaded again until a new constant is desired.The multiply

Selection Of Numeric Format
Essentially, the difference between integer, mixed, and fractional notation in system design is only conceptual.For example, the TMC2009 does not differentiate between this operation: and this operation: 16/BI x 12/BI = 12/64 The difference lies only in constant scale factors !in this case, a factor of 8 in the multiplier and multiplicand and a factor of 64 in the product).However, these scale factors do have

Ordering Information
Product TemperatlH'e Range Number

TMC2009JJC
STD -TA = 0°C to 70°C TMC2009JJG STD -TA -0°c to 70°C TMC2009JJV 1 EXT -Tc = -55°C to 125°C TMC2009C1V 1 EXT -Tc --55°C to 125°C   The TMC2110 is a high-speed 16 x 16 bit parallel multiplier-accumulator which operates at a 100 nanosecond cycle time !10MHz multiply-accumulate rate!.The input data may be specified as two's-complement or unsigned magnitude, yielding a full-precision 32-bit product.Products may be accumulated to a 35-bit result.
Individually clocked input and output registers are provided to maximize system throughput and simplify bus interfacing.These registers are positive-edge-triggered 0-type flip-flops.The result is divided into a 3-bit eXTended Product IXTPI, a 16-bit Most Significant Product IMSPI, and a 16-bit Least Significant Product ILSPI.Individual three-state output ports are provided for the XTP and the MSP; the LSP is multiplexed with the Y input.The output register can be preloaded directly via the output ports.
Built with TRW's state-of-the-art 1-micron OMICRON-C ™ CMOS process, the TMC2110 is pin and function compatible with the industry standard TDC1010, yet operates at more than 50% greater speed.

Value J3 Package Cl, LI Package TTL
The asynchronous multiplier array is a network of AND gates and adders, which has been designed to handle two's complement or unsigned magnitude numbers.The output registers hold the product as two 16-bit words and one 3-bit word: the Most Significant Product IMSPJ, the Least Significant Product !lSPJ, and the eXTended Product IXTPI.Three -state output drivers permit the TM C2010 to be used on a bus, or allow the outputs to be multiplexed over the same 16-bit output lines.The least Significant Product llSPJ is multiplexed with the Y input.
Xo X Data LSB LSI Products Division TRW Electronic Components Group products plus a constant.TRW Electronic Components Group TMC2010 Data Outputs (Cont.I Clocks The TMC2010 has three clock lines, one for each of the input registers and one for the product register.Data present at the inputs of these registers is loaded into the registers at the rising edge of the appropriate clock.The RouND IRNDI, Two's Complement ITCI, ACCumulate IACCJ, and SUBtract !SUBJ inputs are registered, with all four bits clocked in at the rising LSI Products Division TRW Electronic Components Group edge of the logical OR of both CLK X and CLK Y. Special II attention to the clock signals is required if normally HIGH clock signals are used.Problems with the loading of these four control signals can be avoided by the use of normally LOW clocks.

Fractional Two's Complement Notation
When ACCumulate IACCl is HIGH, the content of the output register is added to or subtracted from the next product generated, and their sum is stored back into the output registers at the next rising edge of CLK P. When ACC is LOW, multiplication without accumulation is performed, and the next product generated is stored into the output registers directly.This operation is used for the first term in a summation to avoid a separate "clear" operation.The SUBtract ISUBI control is used in conjunction with the ACC control.When both the ACC and SUB controls are HIGH, the content of the output register is subtracted from the next product generated and the difference is stored back into the output register.Note that the previous output is subtracted from the product, not the product from the previous output.The RND, TC, ACC, and SUB inputs are registered, with all four bits clocked in at the rising edge of the logical OR of both CLK X and CLK Y. Special attention to the clock signals is required if normally HIGH clock signals are used.Problems with the loading of these four control signals can be avoided by the use of normally LOW clocks.

Table 1
Because common good design practice assigns a fixed value to any given line land input and output signals often share the same line), the scale factors determine the connection of the output pins of any multiplier in a system.As a result, only two choices are normally made: integer and fractional notation.If integer notation is used, the Least Significant Bits of the multiplier, multiplicand, and product all have the same value.If fractional notation is used, the Most Significant Bits of the multiplier, multiplicand, and product all have.thesamevalue.These formats are illustrated in detail in Figures1 through 4.
TRW reserv"' ilw riylll 10 change products and specifications without notice.This information does not convey any license under patent rights of TRW Inc. or others.TRW LSI Products Inc.