Fast and Fault-Tolerant Model Predictive Control of MMCs Under Selective Harmonic Elimination

Modular multilevel converters (MMC) are an attractive choice for various applications, including mediumand high-voltage drives. The large number of semiconductor-based submodules (SM) in an MMC makes it vulnerable to SM switch failures. This paper proposes a fault-tolerant (FT) selective harmonic elimination method to enable seamless operation of an MMC during such failures. The effects of switch failure on phase voltage waveforms are studied first. Then, a method is proposed to design the FT SHE-PWM waveform to preserve its harmonic performance. A model predictive controller (MPC) is also proposed to increase the capacitor voltages during an SM failure to maintain the fundamental component of the faulty phase voltage and balance the line voltages. The advantages of the proposed method are verified through offline and realtime simulation studies on a three-phase nine-level MMC in PSCAD/EMTDC software and RTDS.


I. INTRODUCTION
Modular multilevel converters (MMC) have become a suitable choice for applications such as HVDC, FACTS, and medium-and high-voltage drives [1]. Advantages of MMCs include voltage scalability, total modularity, and use of a single DC-link. An MMC consists of hundreds of identical semiconductor submodules (SM) connected in series in each phase. SMs consist of insulated-gate bipolar transistors (IGBT). IGBTs are highly fragile, and since an MMC has many IGBTs, they are the most likely elements to fail [2]. There are two types of IGBT failures: short-circuit and opencircuit. The existing gate-drive circuits provide protection for short-circuit failures. However, open-circuit failures can remain undetected for a long time and cause overvoltage and overcurrent problems. Once detected, the SMs with faulty IGBTs are bypassed using a fast bidirectional switch [3]. This causes the voltage of the faulty phase to reduce and the line voltages to become unbalanced, degrading the power quality of the converter [4]. Reliability is a key factor in MMC applications as mentioned above, and the control system of the MMC should enable its seamless operation during SM failures.
Various methods are introduced in the literature to enable fault-tolerant (FT) operation of MMCs [4]- [12]. These meth-This work was supported in part by the National Science Foundation (NSF) under awards ECCS-1953198 and EECS-1953213, in part by Manitoba Hydro International, and in part by the Commonwealth Cyber Initiative (CCI), an investment by the Commonwealth of Virginia in the advancement of cyber R&D, innovation, and workforce development.
A. Mohammadhassani  ods can be categorized into two groups: hardware-based methods and software-based methods. Hardware-based methods incorporate redundant SMs in each phase, inserted in place of bypassed faulty SMs. However, most of these methods utilize redundant SMs with uncharged capacitors (cold SMs) [9]. Inserting cold SMs into the circuit causes transients and distortions in the output voltage. In addition, cold SMs reduce the semiconductor utilization factor of an MMC. Some redundancy-based methods use pre-charged (hot) SMs [10], [11]. Hot SMs are inserted into circuit even during the normal operation of MMCs. However, this results in increased switching and conduction losses. On the other hand, transient response of the output voltage is better and semiconductor utilization factor is higher. Despite their advantages, both redundancy-based methods have two drawbacks in common [12]: First, utilizing redundant SMs increases the cost and size of the converter. Second, FT operation of MMCs is achieved only when the number of redundant SMs is higher than the number of faulty SMs.
In contrast, software-based methods modify the modulation technique of an MMC to add FT capabilities to its operation. These methods are less common. References [6], [7] study modifying modulation techniques for FT operation of multicell converters. However, they do not maintain the harmonic performance. The merits of modifying space vector modulation (SVM) for FT operation of MMCs are explored in [8]. However, SVM design becomes very complicated when the number of voltage levels increases beyond three. In addition, this method does not use any circulating current controllers during FT mode, which adversely affects the harmonic performance of SVM. Reference [4] modifies the phase-shifted carrier modulation technique (PSC) to enable FT operation in MMCs. However, this method still uses redundant SMs.
A widely known modulation scheme is the selective harmonic elimination pulse-width modulation (SHE-PWM). In SHE-PWM, the switching angles are explicitly calculated to achieve the desired harmonic performance. This technique is commonly used in cascaded H-bridge inverters (CHB) [13], [14]; however, it is not widely employed in MMCs yet. This is because MMCs are commonly used in high-voltage applications, where the number of voltage levels is very high. For instance, an MMC requires 200-400 SMs per arm to reach ±400 kV (DC) in an HVDC system [15]. Therefore, the number of switching angles is also very high. This significantly complicates SHE-PWM; thus, other modulation techniques such as the nearest level modulation (NLM) are used for such applications. Simultaneously, MMCs are beginning to gain favor in applications such as medium-voltage microgrids [16], [17], where the number of SMs is 5-20 per arm. Thus, the advantages of SHE-PWM can be explored for MMCs in these applications [18], and FT SHE-PWM methods can be designed to increase the reliability of MMC operation [19]. On the other hand, the unequal and sometimes large difference between the switching angles in SHE-PWM can cause large ripples in the circulating current in previously proposed circulating current controllers [20]- [22]. This may cause the circulating current controller to become unstable or create large disturbances in the output voltage. A method is proposed in [18] to limit the circulating current ripple by applying redundant switching states and using two upper and lower limits. However, this method has a slow response. Moreover, choosing the limits is an empirical process, which can become difficult under different MMC ratings. Therefore, a circulating current controller should also be designed to address the aforementioned challenges.
This paper introduces an FT SHE-MPC strategy for MMCs. A procedure is proposed to properly design the FT SHE-PWM waveforms to preserve the harmonic performance of the faulty phase voltage and its fundamental component. This procedure is designed by building upon the (2N + 1)-level SHE-PWM proposed in [18]. An MPC-based controller is proposed to stabilize the operation of the MMC while implementing SHE-PWM during normal and FT operation. MPC is an effective strategy for multi-objective and nonlinear models [23], [24]. The proposed controller increases the capacitor voltages during FT operation to complete the transition into FT operation and maintain the fundamental component of the faulty phase voltage. To verify the performance of the proposed FT SHE-PWM scheme, a detailed model of an MMC with 4 SMs in each arm is modeled in PSCAD/EMTDC software. In addition, real-time results are acquired using RTDS to confirm the results obtained using PSCAD/EMTDC.
The specific contributions of this paper are • FT SHE-PWM waveform design procedure.
• Design of MPC-based circulating current controller for normal and FT operation.
The rest of this paper is organized as follows. Section II discusses the mathematical modeling of the MMC. Section III discusses the proposed waveform design procedure for FT SHE-PWM. Section IV presents the proposed MPC strategy. Section V discusses performance evaluation. Section VI discusses the real-time evaluation of the proposed method. Finally, conclusions are presented in Section VII. Fig. 1 shows the generic topology of a three-phase threewire MMC with N SMs in each phase arm. Half-bridge SMs (HBSM) are considered in this paper as they are the most common choice [1]. Each HBSM is also equipped with a bidirectional switch to bypass it during OC SM faults. The circulating current i diff,i and the output current are found as

II. BASICS OF OPERATION
where i u,i and i l,i are the upper and lower arm currents, as shown in Fig. 1. The arm voltages are where v u,i and v l,i are the upper and lower arm output voltages, n i u,j and n i l,j are the upper arm and lower arm capacitor insertion indices, and v i cu,j and v i cl,j are the upper and lower arm capacitor voltages. The balanced steady-state value of the capacitor voltages V c is where V Σ cu,i and V Σ cl,i are the sum of HBSM capacitor voltages in the upper and lower arms, respectively. Therefore, (2) is rewritten as where N u,i and N l,i are the upper and lower arm insertion indices. The line-to-neutral voltage V o,i is defined as

The complete dynamic model of the MMC is found as
where L arm is the arm inductance, R arm is the arm resistance, and C SM is the HBSM capacitance.

III. PROPOSED WAVEFORM DESIGN PROCEDURE FOR FAULT-TOLERANT (2N + 1)-LEVEL SHE-PWM
A. Overview of the (2N + 1)-Level SHE-PWM Fig. 2(a) shows the general (2N + 1)-level phase output voltage waveform V o,i of an MMC with SHE-PWM. The waveform has quarter-wave symmetry. There are k switching angles in one quarter wave, which corresponds to k degrees of freedom. Due to quarter-wave symmetry, the Fourier series expansion of V o,i has only odd sine coefficients: where ω o is the fundamental frequency. The general (2N + 1)-level SHE-PWM problem is defined in (8), which is solved offline to obtain switching angles for normal operation. This formulation can be solved using different methods, e.g., using Groebner bases and symmetrical polynomials [25] and virtual angles [18], which are verified on commercially available software packages such as Maple18, Mathematica, and MATLAB. The first equation corresponds to the fundamental component, and the remaining k−1 equations correspond to the low-order harmonics to be eliminated. Since a three-phase system is studied, triplen harmonics are canceled in line voltages and are not considered in this formulation.
where 0 ≤ m a ≤ 1, and l is the highest harmonic to be eliminated. To address this issue, the number of switching angles in the corrupted V o,i waveform is increased so that the same number of harmonic components are eliminated as in the prefailure case and its fundamental component is preserved.

B. Proposed FT SHE-PWM
The waveforms need to be designed for each value of M . Hence, the more waveforms designed, the more fault-tolerant the converter becomes. However, this also increases the complexity of the controller and requires a larger memory.
As an example, consider the FT SHE-PWM waveform design procedure for a nine-level MMC with N = 4 and M = 1. The V o,i waveform for normal operation of this MMC has 15 switching angles in each quarter-wave. Therefore, 14 low-order harmonics can be eliminated while the fundamental component is controlled at its setpoint. When M = 1, the faulty HBSM and another HBSM in the opposite arm are bypassed. Hence, the faulty phase can no longer generate ±2V c voltage levels (highest levels). As shown in Fig. 2(b), the number of switching angles in one quarter-wave is reduced to 11, which degrades its harmonic performance. To design the FT V o,i waveform as discussed, additional switching angles  are required to be added to the waveform. These switching angles can be arbitrarily placed in the waveform shown in Fig. 2(b) as long as its quarter-wave symmetry is maintained. The difference between the number of switching angles in the waveform shown in Figs  during FT operation to preserve the fundamental component of the faulty output voltage and balance the line voltages. Fig. 4 shows the proposed controller. If M = 0, the controller operates in the normal mode. Otherwise, FT operation is activated. The proposed controller receives the reference SHE-PWM waveform V * o,i and the sampled values of i diff,i , V Σ cu,i , and V Σ cl,i to predict their next sampled values using forward Euler's method. This is done through a discrete form of (6) with a sampling period of where N u,i and N l,i are defined as Equation (11) defines a limited set. The optimum N u,i and N l,i that minimize the cost function defined in (12) are chosen and fed to the balancing block. This block determines which HBSMs to insert or bypass according to their V c values and arm current directions. Using the method proposed in [18], the switching frequency of the proposed method is set to that by the SHE-PWM block. However, MPC controls i diff,i by determining N u,i and N l,i . Therefore, it adds extra switchings to properly control the MMC.
where σ is vector containing the weight factors, X is the state vector, X * is the reference state vector, and · 2 is the Euclidean norm. The weighting factors are determined using the per-unit conversion method in [26] to set i diff,i as the main control objective while setting the relative importance of V Σ cu,i and V Σ cl,i . In contrast to the SHE-MPC strategy in [22], the proposed MPC method does not treat the SHE-PWM waveform as an input to the MPC cost function. Instead, it predicts the state variables for each voltage level in the reference SHE-PWM waveform and chooses the optimum N u,i and N l,i to tighten control on the output voltage and ensure fast and stable control of circulating currents. To maintain energy balance between  the DC and AC sides and balance the energy through phase arms, the method proposed in [27], also shown in Fig. 5, is used to generate i * diff based on the instantaneous information of the MMC, including the instantaneous values of sum of capacitor voltages and the output current.
If an HBSM fails, the proposed controller increases the V c values by the amount defined in (13) to complete the transition to FT operation. To maintain V Σ cu,i and V Σ cl,i at V dc after M HBSM failures, V c should be increased to V dc /(N − M ) requiring larger capacitors. However, as N increases, the increase in capacitor voltages ∆V c during HBSM failures decreases: Even though this method requires overdesign, it is less costly than conventional redundancy-based methods, which add extra HBSMs [8].

V. NON-REAL-TIME EVALUATION
A detailed-model of a three-phase nine-level MMC with N = 4 is created in PSCAD/EMTDC software for non-realtime simulation. Table I summarizes the simulation parameters. The capacitance is calculated using the method in [28] to achieve a 5% voltage ripple. The switching angles are calculated using exchange market algorithm [13] to eliminate harmonics 5 to 43.

A. Steady-State Performance
This section evaluates the steady-state performance of the proposed method during normal operation. Fig. 6(a) shows the capacitor voltages of phase a. The proposed method success- fully controls the capacitor voltages at 2.72 kV with a ripple of 4.89%. Fig. 6(b) shows i diff,a ; it correctly follows its reference with a maximum of 106.1 A. Fig. 6(c) shows the output currents. The proposed method generates balanced three-phase output currents with a peak magnitude of 335.3 A. Fig. 6(d) shows the output voltages. The proposed method generates balanced three-phase output voltages with a peak magnitude of 4 kV. Fig. 6(e) shows the harmonic spectrum of the output voltages: the peak value of the fundamental component is 4 kV, and the low-order harmonics are eliminated.

B. Response to Change in m a
This section evaluates the response of the proposed method to a step change in m a during normal operation. Fig. 7(a) shows the capacitor voltages of phase a. At t = 50 ms, m a increases in a step from 0.8 to 1. After a small transient with an overshoot to 2.87 kV, the capacitor voltages stabilize at 2.72 kV with a ripple of 5.03%. The settling time of capacitor voltages is 50 ms, which is almost half of that for the method proposed in [18]. Fig. 7(b) shows i diff,a . At t = 50 ms, m a increases in a step from 0.8 to 1. i diff,a successfully follows its new reference, increasing its maximum to 156.3 A. The settling time for the circulating current is 20 ms, which is almost one-fifth of that for the method proposed in [18]. Fig. 7(c) shows the output currents. The proposed method successfully generates balanced three-phase output currents and increases their peak magnitude to 413.8 A.   Fig. 7(e) shows the harmonic spectrum of the output voltages. The peak value of the fundamental component is increased to 5 kV while eliminating the low-order harmonics.

C. Response to HBSM Failures
This case study evaluates the performance of the proposed method under HBSM failures. Fig. 8(a) shows the capacitor voltages of phase a. At t = 50 ms, SM u1a and SM l1a are bypassed and FT operation is established. The proposed method stabilizes the remaining capacitor voltages at 3.62 kV with a ripple of 3.85% at t = 126.43 ms. Fig. 8(b) shows i diff,a ; it stabilizes with a maximum of 99.8 A at t = 126.43 ms and an overshoot to 248.6 A. The settling time of capacitor voltages and circulating current is 76.43 ms, which is significantly faster than the method proposed in [5] which takes 428.8 ms to establish FT operation. Fig. 8(c) shows the output currents. The proposed method generates balanced three-phase output currents and keeps their peak magnitude constant. However, the output currents become slightly more distorted. Fig. 8(d) shows the output voltages. The proposed method generates balanced three-phase output voltages with a modified waveform for V o,a . Fig. 8(e) shows the harmonic spectrum of V o,a during FT operation; the low-order harmonics are still eliminated and the peak value of the fundamental component is preserved. However, some of the triplen harmonics are increased compared to normal operation.

VI. REAL-TIME EVALUATION
This section evaluates the performance of the proposed method in real-time to validate the results of Section V. The MMC system is modeled on an RTDS NovaCor chassis with one core. It is modeled in the substep environment using the CHAINV5 model. This model uses a surrogate circuit to model each HBSM. The surrogate circuit consists of an upward diode, a capacitor, and a discharge resistor in parallel. In an electromagnetic transient simulation, HBSM capacitor branches are modeled with a resistance and a Thevenin history voltage source (V hc ). Alternating calculations of the HBSM capacitor voltage and V hc occur during each time step. In addition, the MMC model in RTDS includes DC-link resistances, but not the parallel bypass switches. Instead, the bottom switch of the faulty HBSM is turned on to bypass that HBSM.

A. Steady-State Performance
This section evaluates the steady-state performance of the proposed method in real time. Fig. 9(a) shows the real-time steady-state results for capacitor voltages of phase a during normal operation. The proposed method successfully stabilizes the capacitor voltages at 2.72 kV with a ripple of 4.87%. Therefore, real-time and non-real-time capacitor voltage results are similar. Fig. 9(b) shows the real-time steady-state re- sults for i diff,a during normal operation. It follows its reference and has a maximum of 108.6 A. Real-time and non-real-time results for i diff,a are similar. Fig. 9(c) shows the output currents. The proposed method generates balanced three-phase output currents with a peak magnitude of 333.2 A. Therefore, realtime and non-real-time results are similar. Fig. 9(d) shows V o,i . The proposed method generates balanced three-phase output voltages with a peak magnitude of 4 kV, similar to non-realtime results. Fig. 9(d) shows the harmonic spectrum of V o,i . The peak value of the fundamental component is 4 kV, and the low-order harmonics are eliminated, similar to non-real-time results.

B. Response to HBSM Failures
This section evaluates the performance of the proposed method under HBSM failures in real time. At t = 50 ms, SM u1a and SM l1a are bypassed and FT operation is established. Fig. 10(a) shows the capacitor voltages of phase a. The proposed method stabilizes the remaining capacitor voltages at 3.62 kV with a ripple of 3.81% at t = 126.43 ms, similar to their non-real-time response. Fig. 10(b) shows i diff,a ; it stabilizes with a maximum of 103.4 A at t = 126.43 ms and an overshoot to 243.8 A, similar to the non-real-time results. Fig. 10(c) shows the output currents. The proposed method generates balanced three-phase output currents and keeps their peak magnitude constant. However,the output currents become slightly more distorted. Fig. 10(d) shows the real-time results for V o,i during FT operation. The proposed method generates balanced three-phase output voltages with a peak magnitude of 5 kV during FT operation and changes the waveform of V o,a . Fig. 10(e) shows the harmonic spectrum for real-time V o,a during FT operation. The low-order harmonics are eliminated, and the fundamental component is preserved. However, some of the triplen harmonics are increased compared with normal operation. Therefore, the harmonic performance of real-time and non-real-time V o,a are similar.

VII. CONCLUSIONS
This paper proposes an FT SHE-PWM control method for MMCs. An MPC strategy is proposed to control the capacitor voltages and circulating currents. When an HBSM fails, the corresponding FT SHE-PWM waveform is constructed and sent to the MPC. Afterwards, the MPC applies the optimum insertion indices to properly control the MMC and generate the designed waveform at its output terminals. The proposed method is evaluated on a three-phase nine-level MMC in PSCAD/EMTDC and RTDS. Non-real-time simulation results demonstrate that the proposed method successfully controls the capacitor voltages and circulating currents while generating the correct SHE-PWM waveform the output terminals of the MMC during normal and FT operations. Real-time simulation results are provided to validate the non-real-time simulation results.