Abstract
Sequential reactive systems include programs and devices that work with two streams of data and convert input streams of data into output streams. Such information processing systems include controllers, device drivers, computer interpreters. The results of operation of such computing systems are infinite sequences of pairs of events of the request-response type, and, therefore, finite transducers are most often used as formal models for them. The behavior of transducers is represented by binary relations on infinite sequences, and so, traditional applied temporal logics (like HML, LTL, CTL, mu-calculus) are poorly suited as specification languages, since omega-languages, not binary relations on omega-words are used for interpretation of their formulas. To provide temporal logics with the ability to define properties of transformations that characterize the behavior of reactive systems, we introduced new extensions of these logics, which have two distinctive features: (1) temporal operators are parameterized, and languages in the input alphabet of transducers are used as parameters; (2) languages in the output alphabet of transducers are used as basic predicates. Previously, we studied the expressive power of new extensions Reg-LTL and Reg-CTL of the well-known temporal logics of linear and branching time LTL and CTL, in which it was allowed to use only regular languages for parameterization of temporal operators and basic predicates. We discovered that such a parameterization increases the expressive capabilities of temporal logic, but preserves the decidability of the model checking problem. For the logics mentioned above, we have developed algorithms for the verification of finite transducers. At the next stage of our research on the new extensions of temporal logic designed for the specification and verification of sequential reactive systems, we studied the verification problem for these systems using the temporal logic Reg-CTL*, which is an extension of the generalized computational tree logics CTL*. In this paper we present an algorithm for checking the satisfiability of Reg-CTL* formulas on models of finite state transducers and show that this problem belongs to the complexity class ExpSpace.
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REFERENCES
Alur, R. and Cerny, P., Streaming transducers for algorithmic verification of single-pass list-processing programs, Proceedings of the 38th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2011, pp. 599–610.
Hu, Q. and D’Antoni, L., Automatic program inversion using symbolic transducers, Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2017, pp. 376–389.
Veanes, M., Hooimeijer, P., Livshits, B., Molnar, D., and Bjorner, N., Symbolic finite state transducers: Algorithms and applications, Proceedings of the 39th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2012, pp. 137–150.
Gnatenko, A.R. and Zakharov, V.A., On the expressive power of some extensions of linear temporal logic, Autom. Control Comput. Sci., 2019, vol. 53, no. 7, pp. 663–675.
Zakharov, D.G., Kozlova, V.A., and Kozlova, D., On the model checking of sequential reactive systems, Proceedings of the 25th International Workshop on Concurrency, Specification and Programming, Rostock, Germany, 2016, vol. 1698, pp. 233–244.
Gnatenko, A.R. and Zakharov, V.A., On the model checking of finite state transducers over semigroups, Proc. ISP RAS, 2018, vol. 30, no. 3, pp. 303–324.
Clarke, E.M., Jr., Grumberg, O., Kroening, D., Peled, D., and Veith, H., Model Checking, MIT Press, 2018.
Gnatenko, A.R., On the complexity of model checking problem for finite state transducers over free semigroups, Proceedings of the Student Session of European Summer School on Logic, Language and Information, Riga, 2019.
Hopcro, J. and Ullman, J., Introduction to Automata Theory, Languages, and Computation, Addison-Wesley, 1979.
Gabbay, D., Pnueli, A., Shelah, S., and Stavi, J., On the temporal analysis of fairness, Proceedings of the 7th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 1980, pp. 163–173.
Manna, Z. and Wolper, P., Synthesis of communicating processes from temporal logic specifications, Workshop on Logic of Programs, Springer, 1981, vol. 131, pp. 253–281.
Wolper, P., Temporal logic can be more expressive, Inf. Control, 1983, vol. 56, nos. 1–2, pp. 72–99.
Kupferman, O., Piterman, N., and Vardi, M.Y., Extended temporal logic revisited, Proceedings of 12-th International Conference on Concurrency Theory, Springer, 2001, pp. 519–535.
Vardi, M.Y. and Wolper, P., Yet another process logic, in Lecture Notes in Computer Science, Springer, 1983, vol. 14, pp. 501–512.
Vardi, M.Y., A temporal fixpoint calculus, Proceedings of the 15-th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 1988, pp. 250–259.
Henriksen, J.G. and Thiagarajan, P.S., Dynamic linear time temporal logic, Ann. Pure Appl. Logic, 1999, vol. 96, nos. 1–3, pp. 187–207.
Leucker, M. and Sanchez, C., Regular linear temporal logic, Proceedings of the 4-th International Colloquium on Theoretical Aspects of Computing, Springer, 2007, pp. 291–305.
Mateescu, R., Monteiro, P.T., Dumas, E., and De Jong, H., CTRL: Extension of CTL with regular expressions and fairness operators to verify genetic regulatory networks, Theor. Comput. Sci., 2011, vol. 412, no. 26, pp. 2854–2883.
Gerth, R., Peled, D., Vardi, M.Y., and Wolper, P., Simple on-the-fly automatic verification of linear temporal logic, International Conference on Protocol Specification, Testing and Verification, Springer, 1995, pp. 3–18.
Vardi, M.Y. and Wolper, P., An automata-theoretic approach to automatic program verification, Proceedings of the First Symposium on Logic in Computer Science, IEEE Comput. Soc., 1986, pp. 322–331.
Savitch, W.J., Relationships between nondeterministic and deterministic tape complexities, J. Comput. Syst. Sci., 1970, vol. 4, no. 2, pp. 177–192.
Kozen, D., Lower bounds for natural proof systems, Proceedings of the 18-th Symp. on the Foundations of Computer Science, IEEE, 1977, pp. 254–266.
Mader, A., A classification of PLC models and applications, in Discrete Event Systems, Springer, 2000, vol. 569, pp. 239–246.
Ovatman, T., Aral, A., Polat, D., and Unver, A.O., An overview of model checking practices on verification of PLC software, Software Syst. Model., 2016, vol. 15, no. 4, pp. 937–960.
Garanina, N., Anureev, I., Zyubin, V., Rozov, A., Liakh, T., and Gorlatch, S., Reasoning about programmable logic controllers, Syst. Inf., 2020, vol. 17, pp. 33–42.
Kuzmin, E.V., Ryabukhin, D.A., and Sokolov, V.A., On the expressiveness of the approach to constructing PLC-programs by LTL-specification, Autom. Control Comput. Sci., 2016, vol. 50, no. 7, pp. 510–519.
Ljungkrantz, O., Akesson, K., Fabian, M., and Yuan, C., A formal specification language for PLC-based control logic, Proceedings of the 8th IEEE International Conference on Industrial Informatics, IEEE, 2010, pp. 1067–1072.
Ljungkrantz, O., Akesson, K., Fabian, M., and Ebrahimi, A.H., An empirical study of control logic specifications for programmable logic controllers, Empirical Software Eng., 2014, vol. 19, no. 3, pp. 655–677.
ACKNOWLEDGMENTS
The authors are grateful to the anonymous referee for the valuable comments that helped to improve this paper.
Funding
The reported study was funded by Russian Foundation for Basic Research, project no. 18-01-00854.
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Gnatenko, A.R., Zakharov, V.A. On the Model Checking Problem for Some Extension of CTL*. Aut. Control Comp. Sci. 55, 776–785 (2021). https://doi.org/10.3103/S0146411621070051
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DOI: https://doi.org/10.3103/S0146411621070051