RSA ENCRYPTION USING VLSI ARCHITECTURE FOR HIGH SPEED APPLICATIONS

: The major concern for the governments and private network communication is the security of systems against eavesdropping and illegal access. To overcome such illegal access the security of modern computer systems uses public-ciphers key namely Rivest, Shamir and Adleman (RSA). The RSA provides both authentication and secrecy of communication. In conventional encryption method the cryptography using RSA provides good secrecy and reduces area but generates more delay due to time taken by the multiplication part. To overcome such a problem, a 32-bit RSA using modulo (2 n +1) multiplication based VLSI architecture is presented in this study. This method offers less delay with high performance which can be used in any communication network field. The proposed method is implemented using Xilinx 12.4 ISE and simulated in MODELSIM 6.3c.


I. INTRODUCTION
The main objective of the cryptographer is to make the crypto process easy and execute fast by advanced implementation techniques.RSA encryption and decryption by vedic mathematics is described in [1].To enhance the efficiency of RSA architecture, straight division algorithm of vedic mathematics is developed.Three methods of multiplication modulo operations using (n+1)*(n+1)-bit array multiplier, modulo p carry-save addition, and modulo (p-1) carry save addition is described in [2].They are implemented in pipelined realizations that produce a very high throughput.
A 16 bit RSA cipher for encryption and decryption using greatest common divider algorithm is described in [3].It improves the security of the transmitted data or information.The realization of the RSA cryptographic algorithm based on the digit method and montgomery multiplier is described in [4].It increases the speed of RSA encryption and decryption technique.Montgomery multiplication based on the residue number system is described in [5] to avoid timing attack and fault induction attack.The structure of the constituent modules of RSA is described in [6] based on the cellular automata.
An efficient Very Large Scale Integration (VLSI) structure based on the polymorphic cipher is described in [7] by considering unconditionally encipher procedure.VLSI structure for PRESENT block cipher algorithms is described in [8] for the key length of 128-bit and 80-bit.Various stages of the pipelining architecture of 128-bit Advanced Encryption Standard (AES) are described in [9] to increase the throughput.
Different architecture of the mix column is described in [10] to realize the AES encryption algorithm using Altera Quartus tool II.An enhanced mix column using asynchronous AES architecture with less transistor count is described in [11].A comparative study of various standard multipliers is discussed in [12].All multipliers are implemented in VLSI and their performances are also analyzed.
VLSI implementation of combinational and pipelined circuits for addition and multiplication modulo are discussed in [13].A study of various approaches for hardware implementation of AES is discussed in [14].It includes pipelining, sub-pipelining and loop unrolling.Also, it discusses the resource sharing issues between the encryption and decryption of AES algorithm.The revocable identity based encryption in cloud to secure the data is discussed in [15].
In this study, VLSI architecture based RSA cipher for high performance secret communication is presented.The paper is organized as follows.Section 2 explains the RSA encryption using modulo 2 n +1 multiplication and section 3 describes the simulation and result analysis.The final section 4 describes the conclusion of the work.

II. METHODS AND MATERIALS
The flowchart of proposed RSA encryption with modulo multiplication is shown in Fig. 1.The input data is given to the key distribution, key generation and message modules.The size of message is 32-bit data and the RSA encryption is obtained from modulo multiplication.

III. RESULTS AND DISCUSSION
The 32-bit RSA encryption using modulo (2 n +1) multiplication based VLSI architecture is simulated using Xilinx 12.3 ISE (Family-Virtex 4, Package-FF668, Speed:-12 and Devices-XC4VLX15/XCVLX25) design tool.The simulation waveform for the proposed 2 n +1 multiplication for RSA encryption is depicted in Fig. 4. Also, the simulation wave form for the RSA encryption is shown in Fig. 5.

Fig. 5 Simulation waveform of the RSA Encryption
Let us consider, the public keys are 7663 and 2347 and the private keys are 7663 and 67.Based on these keys, the original message 3452 is sent as 2978 which is the encrypted value of 3452.Thus, RSA guarantees the safe transmission of original message.After simulating the code, the delay is computed and given in the design summary of the tool.Figure 6 shows the performance analysis of the RSA encryption in terms of delay.

Fig. 6 Performance analysis of the RSA encryption
From the chart analysis, it is observed that the delay taken for the conventional method is 12.888ns whereas it is 11.388ns for the proposed system.Thus, the proposed RSA encryption method offers less delay with high performance than the conventional method.

IV. CONCLUSION
In this study, 32-bit RSA encryption using modulo 2 n +1 multiplication is presented using Xilinx 12.4 ISE tool.This RSA encryption offers high security and trusted one throughout the cryptography method.When compare to the conventional method the proposed method offers 11.58% reduction in delay with high performance as well as good secrecy in the communication without any degradation in the system performance.This method is used in net-banking systems for secure data transform.In future, the proposed system should be tested to overcome the mobility problem over group communication which enhances the overall parameters like less complexity design and good storage capacity.

Figure 2 Fig. 2 Fig. 3
Figure2depicts the architecture of RSA cryptosystem.The RSA configuration module consists of two registers to store the key as well as the message text.The intermediate results are stored temporarily in the core unit of RSA architecture and the control unit controls the movement of data between the units of RSA architecture.Also, the modulo operations [13] are performed in core unit.It consists of four main components such as one intermediate register with 512-bit, multiplexer, control unit and arithmetic logic unit with modulo 2 n +1 multiplication which is shown in Fig.3.More information on modulo 2 n +1 multiplication operation can be found in[13].