Authors:
M. Jasmin,S. Philomina,DOI NO:
https://doi.org/10.26782/jmcms.spl.2019.08.00053Keywords:
DVFS,MPSoC,SoC,NoC,Abstract
In VLSI due to recent advancements , there is a need for integration of multiple processors into a single chip. System on chip (Soc) and MPSoc consist of many processors on a single dye. In Soc power dissipation is the most critical factor, which has to be given more importance.Hence power optimization techniques have been proposed.To have an effective analysis on Power optimization ,surveys on various power optimization techniques have been presented. Power dissipation that occurs in digital circuits is mainly due to the logic elements, clocks, memories and other components. To minimize the power dissipation various techniques are analysed to achieve an effective integration of all types of SOCs with increased bandwidth and frequencies Network on chip (NoC) has been later evolved .But NoC consumes more power due to high operating frequencies.So there is a need to reduce power during compilation to increase the performance of the system. Power optimization during run time compilation is alsoexplained.In NOC power is mainly utilized during the data communication between various processing elements. Hence power utilization due to the communication links in the digital circuits is discussed. The methodologies to implement dynamic voltage and frequency scaling (DVFS) in digital design have been discussed. This paper mainly focuses on Various power optimization techniques for reducing the power utilization in network .Refference:
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