A Novel Intermediate Bus Converter Topology for Cutting Edge Data Center Applications

: As new technologies emerge data centers and servers have established themselves as one of the largest and fastest growing consumers of power. While switched capacitor converter topologies have some very attractive features, namely low reliance on magnetic components and high efficiency, several critical factors have prevented their adoption in high current data center applications. The family of converters proposed are novel intermediate bus converter that demonstrates the highest performance yet achieved for 48 V to 12 V conversion with up to 2.5 kW/in 3 power density, higher than 99% peak efficiency, and 97.2% full load efficiency for 12 V/70 A output. The reduction of voltage stress across the MOSFETs as well as extremely low reliance on magnetics are the key driving factors behind this high efficiency and power density, and are achieved without a sensitive resonant design or the usage of complex control technique.

components, have made DC-DC converters with a lower reliance on magnetics a particularly attractive option where high power density and efficiency are required.Switched capacitor converters can, in theory, eliminate these large magnetic components.Additionally, switched capacitor converters operate optimally at fixed integer conversion ratios (such as 4:1 stepdown for 48 V to 12 V conversion).In an IBA where regulation is not required for the bus converter, this makes switched capacitor converters an extremely attractive option.As shown in Fig. 1 [1] , which presents a comparison of several 48 V to 12 V converter designs, in applications where regulation is not required, unregulated converters can provide an extremely large advantage in terms of both efficiency and power density when compared with regulated converter options.
However, conventional switched capacitor converter topologies have several practical limitations that can prevent their wide adoption for high current/power level applications.The zero inductorvoltage (ZIV) converter is a converter that maintains the key advantages offered by switched capacitor converters, namely extremely low reliance on magnetic components, without any of the drawbacks traditionally associated with switched capacitor converters operating at high current levels.The ZIV converter has achieved the highest power density and efficiency yet demonstrated in literature for an unregulated, 48 V to 12 V intermediate bus converter.As shown in Fig. 1, the two phase 12-switch ZIV converter achieves 2.5 kW/in 3 power density for 48 V to 12 V conversion at 70 A load current with a full load efficiency of 97.2%.This paper is organized as follows.Section 2 will present an overview of existing switched capacitor converters for IBA.Section 3 will present the ZIV converter family.Section 4 will present simulation results and analysis related to the ZIV converters.Section 5 will present the experimental results, and Section 6 will conclude the paper.

Overview of switched capacitor topologies for intermediate bus applications
In conventional switched capacitor converter (SCC) topologies it generally not possible to regulate the output voltage without introducing significant loss.The optimal operating point will typically occur at an integer-ratio step-down as determined by the circuit topology.While this may preclude their use in certain applications in the intermediate bus architecture it is possible for the intermediate bus converter to operate as a so-called DC-transformer (DCX), and output voltage regulation is not required.Switched capacitor converters have therefore become widely researched for these DCX applications in datacenters.Additionally, in many conventional DC-DC converter topologies the magnetic components are the largest components and are lossy.Switched capacitor converters aim to remove, or at least significantly reduce, the need for any magnetic components in the converter to achieve much higher power densities, and efficiencies than conventional topologies [16] .
In conventional switched capacitor converter topologies, however, there is a fundamental issue with a true magnetics-less SCC, namely the charge redistribution loss.This charge redistribution loss occurs when a low impedance switch is closed between two paralleled capacitors and results in a current spike, as shown in Fig. 2, as well as energy loss associated with charge redistribution.To reduce this loss and limit the current spike, larger capacitors or higher switching frequencies are required than would otherwise be desired, reducing both the power density and efficiency advantages offered by SCC topologies.by parallel connection of mis-matched flying capacitors [17] In order to address the charge redistribution problem, SCCs with added inductive elements, sometimes referred to as hybrid SCC topologies, have been proposed.Many such topologies have been derived, utilizing the principle that adding an inductive element between the two paralleled capacitors will eliminate the charge redistribution current spike and associated loss [18] .
However, many of these designs are not suitable for high volume applications such as data centers for several critical reasons.First, immunity to component non-idealities is crucial.Ceramic capacitors and off-the-shelf inductors typically have fairly large component tolerances (>10%), along with the DC-voltage derating and effects of temperature on ceramic capacitors, it is impossible to guarantee that precisely tuned resonant circuits relying on these components can be mass produced.Scalability to different power levels is also critical.In order to achieve this, it should be possible to parallel the intermediate bus converters with reasonably good current sharing performance.Scalability of control is also a concern; utilizing techniques that require additional sensing can cause issues with paralleling or scaling to differing power levels.

Zero inductor-voltage converter family
The technical approach used in this paper is different from the above-mentioned SCC converter with inductor as a current limit component.The converter topology proposed in this paper is a PWM switching converter that can (1) include an inductor, (2) operate at PWM mode, and (3) make zero voltage across the inductor.In this ZIV topology the voltage across the inductor is independent of the input and output voltages.The inductor voltage is the ripple voltage of the input capacitor, output capacitor and flying capacitor.The capacitors in this topology are always connected in series, never in parallel.The voltage blocking of the flying capacitors also reduces the voltage stress of the MOSFETs.Since it is derived from a PWM converter, the operation of the converter is not sensitive to the capacitor or inductor value tolerance.As a result, the design of this converter is greatly simplified, and extremely good efficiency and power density can be achieved as will be shown in Section 5.

Proposed 7-switch zero inductor-voltage converter
The ZIV converter utilizes 7 MOSFETs and 2 flying capacitors in the topology shown in Fig. 3 [19] .The PWM gate drive signals are shown in Fig. 4. From this, it can be observed that the converter has 3 operating states, labelled A, B and C. The equivalent circuit for each operating state is shown in Fig. 5.In operating state A, MOSFETs M1, M3 and M6 are on.In this state the flying capacitors are being charged.In operating state B, MOSFETs M1 and M3 are turned off, M2 and M4 are turned on, and M6 remains on.The first flying capacitor, C f1 is now being discharged, while C f2 continues to charge.In operating state C, all the first stage MOSFETs (M1-M4) are now turned off.MOSFET M6 is turned off, and MOSFETs M5 and M7 are turned on.C f1 is now disconnected and does not carry any current during this operating state, while C f2 is discharged for the remainder of the switching period.From these figures the flying capacitors are never placed in parallel, and the inductor is always in the current path.This means that there is no current spike of the capacitors; soft-charging is an inherent feature of the topology and does not depend on any particular component tolerances, or additional inductors added to the current carrying branches.The key drawback of the 7-switch ZIV topology is that the first-stage MOSFETs (M1-M4) operate with only 25% duty cycle.It is desirable to operate MOSFET pairs with 50% duty cycle to achieve full utilization of the switching devices.

Proposed 12-switch ZIV converter
In order to address the issue of the MOSFET utilization, the 12-switch ZIV converter topology shown in Fig. 6 [20] .This converter utilizes two paralleled second-stages but requires only one input-stage.This results in significant component and size savings compared with a two-phase 7-switch ZIV converter, while also offering greatly improved efficiency and power density when compared with a single-phase 7-switch ZIV converter.The operation of this topology, and the realization of the component reduction, is best understood by examining two single-phase ZIV converters operating in parallel with a 180-degree phase shift.Note that for each phase, the first stage switches M1-M4 will be off for 50% of the total converter cycle during State C (from 0.5T s to T s , 1.5T s to 2T s , etc) as shown in Fig. 4. Fig. 7 shows the PWM gate drive diagram for the 12-switch ZIV converter.

Steady state operation
Note that the following derivation will be presented for the 7-switch ZIV converter.The analysis for the 12-switch ZIV converter is identical, with the understanding that States C and D (Fig. 7) are exactly mirrored to states A and B.
In order to understand the 4:1 step down ratio provided by this converter topology the inductor voltage can be analyzed in the steady state where As seen from the gate signal diagram, Fig. 4, State A is active for 25% of one switching cycle, State B is active for 25% of one switching cycle, and State C is active for the remaining 50% of the switching cycle.Thus the average inductor voltage over one switching cycle can be expressed as Note that the capacitor charge balance must also be maintained for steady state operation.This means that the average voltage of C f1 Substituting Eqs. ( 1), ( 2) and (3) into Eq.( 4) with the equivalencies noted in Eqs. ( 5) and (6) gives Under steady state operation the average inductor voltage across one switching cycle must be zero, and utilizing the equivalencies given in Eqs. ( 5) and ( 6) the capacitor voltage terms cancel out as shown in Eq. ( 7) leaving Thus, the ZIV converter family as presented provides a fixed 4:1 stepdown ratio under steady-state operation.

ZIV operation
As mentioned in Section 1 the ability to reduce the reliance on large magnetic components is the critical advantage allowing SCC topologies to achieve high power density and efficiency.While the ZIV converter is not an SCC topology, and thus avoids the critical drawbacks such as charge redistribution, it does maintain the advantage of very low reliance on magnetic components.This can be understood by examining the voltage at V sw2 in Fig. 3.
The first flying capacitor will have a nominal DC value of 0.5 V in , and the second flying capacitor will have a DC value of 0.25 V in nominally.These capacitor voltages can be expressed as a nominal DC value, summed with a ripple voltage.
For all of the above states, the voltage at V sw2 is equal to 0.25 V in plus the capacitor ripple voltage.The inductor is connected between V sw2 and the output voltage, which is also shown to be equal to 0.25 V in .Thus, the only voltage seen by the inductor will be due to the capacitor voltage ripple.This means the inductor voltage is independent of the input and output voltage level.Therefore, a very small inductor can be used to achieve acceptable inductor ripple.The low inductor voltage stress means that very small inductors, as small as 100 nH, can be utilized even with switching frequencies below 100 kHz.

Analysis and computer simulation 4.1 Loss analysis
Loss analysis is conducted for the 7-switch ZIV converter.Tab. 1 shows the components used in the 7-switch ZIV converter design.The conduction losses for the MOSFET, inductors and capacitors are estimated straightforwardly by Eq. ( 14).Note that the inductor loss, for the ZIV converter, is entirely winding loss as any core loss will be negligible.

Tab. 1 7-switch ZIV converter loss analysis components
The switching loss for the MOSFETs is estimated according to Eq. ( 15) where t on is the turn-on time of the MOSFET, and t off is the turn-off time of the MOSFET.

 
1 2 The deadtime (MOSFET body diode) loss is estimated according to Eq. ( 16) where t dt-r is the rising edge dead time and t dt-f is the falling edge deadtime and V sd is the reverse diode voltage of the MOSFET.

 
-dt sd dt r dt f sw The gate drive loss is estimated according to Eq. (17).
The loss analysis was performed for an input voltage of 48 V, and a load current of 25 A with a switching frequency of 60 kHz and the results are shown in Fig. 8.Note that under this load condition the conduction loss makes up over 80% of the total converter loss, despite being a hard-switched topology that does not rely on a resonant design.

Inductor voltage analysis
Using the same components outlined in Tab. 1 in a computer simulation the inductor voltage was analyzed to verify the "zero inductor-voltage" operation of the converter.The results of the simulation for 25 A load and 60 kHz switching frequency are shown in Fig. 9. From this simulation it is confirmed that the inductor sees only the capacitor ripple voltages, resulting in a very low overall reliance on magnetic components.

Current sharing analysis
As mentioned in Section 2, scalability to differing power levels is a crucial consideration for intermediate bus converter topologies and this is commonly achieved through the paralleling of multiple phases of converters.In the case of the ZIV converter, the current sharing can be achieved passively through the output voltage "droop" characteristic inherent to the ZIV converter.
In the ideal case, with lossless switches, the ZIV converter would be expected to output a voltage equal to exactly one-quarter of the input voltage.In practice the converter output will be slightly lower than the expected value of 0.25 V in .This is caused by the conduction related voltage drop across the components of the converter, such as the MOSFETs, inductors, flying capacitors and PCB traces.As this voltage drop will be linearly proportional to the load current the output voltage of the ZIV converter can be modelled by the following equation If two ZIV converters are connected in parallel, then the current carried by each phase will be determined according to the output voltage characteristic of each phase.If R out1 and R out2 are the lump equivalent resistance for each phase of the ZIV converter then the current sharing is given by 2 1  12 Fig. 9 demonstrates a case where the resistance value of phase 2 (comprised primarily of the MOSFET R ds(on) and capacitor ESR) is 10% higher than the lump resistance of phase 1.Note that in Fig. 9 the output current is give as the per-phase value, therefore 35 A per phase current would represent a total full load current of 70 A. For a 50 A total load with 10% resistance increase in one phase relative to the other, the output voltage will be approximately 11.73 V for 48 V input.The current will share according to the equations The modelled output voltage characteristic is derived from the components in Section 5, Tab. 3 and shown in Fig. 10.Using these components, the output voltage for the ZIV converter design would be 11.73 V at 50 A load current.The first phase would carry 26.2A of the load.The second phase would carry 23.8A of the load.As demonstrated here, the droop output voltage characteristic cannot guarantee perfect current sharing.Manufacturing tolerances and component-tocomponent variation will result in some current sharing mismatch in a multi-phase ZIV converter design.However, as this analysis shows, the passive current sharing will offer reasonably good performance.This means scalability to differing power levels can be achieved without added control complexity.In addition, the phase which carries higher current will become hotter and therefore, the R ds of the MOSFET for that phase will be increased, which will further improve the current sharing between the phases.

Experimental results
Experimental results are presented for a 7-switch ZIV converter design, and a two-phase 12-switch ZIV converter design.The 7-switch ZIV converter represents a proof of concept design, and demonstrates the very high efficiency of the ZIV converter, while the two-phase 12-switch ZIV converter design is optimized to achieve extremely high power density, while also demonstrating that the ZIV converter can be easily scaled to higher power levels through paralleling.

7-switch ZIV converter prototype
A prototype was constructed using the components outlined in Tab. 2. The experimental results presented in this section were gathered with an input voltage of 48 V, a switching frequency of 60 kHz, and a nominal load current of 25 A. Fig. 11 shows a photograph of the top side of the converter prototype, with the key components labelled.The driver circuitry, as well as additional capacitors are located on the back of the prototype.The prototype has a width of 0.9 in, length of 1.3 in and a height of 0.45 in giving an overall power density for 12 V 35 A output of 800 W/in 3 .Fig. 11 7-switch ZIV converter prototype top-side photograph Fig. 12 shows the converter input voltage, the voltage of the two flying capacitors and the output voltage.For the 48 V input voltage the flying capacitor charges to 0.5V in or 24 V, the second flying capacitor charges 0.25V in or 12 V, and the output voltage is also 1/4V in or 12 V.Fig. 13 shows the inductor current (top) and inductor voltage (bottom) waveforms.The shapes of the inductor current and voltage waveforms closely match the results expected from the simulation.The practical ZIV converter requires deadtime between switching transitions to prevent shoot-through.This can be seen in Fig. 13, as the inductor sees a negative voltage during this deadtime.However, the deadtime in the circuit is extremely short, at around 10 ns.Therefore the impact of this deadtime on the overall inductor current ripple is almost negligible.The start-up waveform for the converter prototype is shown in Fig. 14, with the input voltage, C f1 and C f2 voltages presented.It should be noted that no active capacitor balancing or control circuitry is added to the circuit, therefore, this procedure also validates that the capacitors will naturally balance near their expected value based on the duty cycle of the MOSFETs, as the capacitors naturally correct for the "imbalance" created when the input voltage is stepped, and quickly settle to their nominal values of 0.5V in and 0.25V in respectively.This also means no additional control complexity is required to balance the capacitors in the ZIV converter.15 shows the measured prototype efficiency (including gate-drive loss) using Reidon RSN series (0.1% error) current shunts as well as a Keithley 2 700 digital multimeter.A small USB desk fan is used to cool the prototype.With a more powerful fan, or additional heat sinking, a higher load current could have been achieved as the inductor saturation current is 49 A. In order to validate the theoretical current sharing analysis two phases of the ZIV converter design were operated in parallel.The ripple voltages of each flying capacitor were measured to approximate the current carried by each phase.The flying capacitor ripples for Phase 1 is shown in Fig. 16, and Phase 2 is shown in Fig. 17.As shown by these figures the current is shared approximately equally, with no additional active control.An experiment was conducted using 20 V input (5 V output) where the load current was stepped from 1 A to 20 A, and back down to 1 A. The V out dynamic response to this load transient is presented in Figs.18 and 19.The current slew rate was 10 A/µs (the maximum possible for the testing equipment).

Two-phase 12-switch ZIV converter prototype
This experimental results section focuses on a two-phase design of the 12-switch ZIV converter.While the 7-switch design was intended to verify the functionality of the topology, the two-phase 12-switch ZIV design allows for significant power density improvements to be made.Fig. 20 shows a photo of the power stage (top) and driver circuitry (bottom) for one phase of the converter.The dimensions for one phase of the converter design are 1 in×0.75in×0.226 in (25.4 mm×19.1 mm×5.7 mm).Tab. 3 shows the components selected for the experimental prototype.For the driver circuitry the LTC4440-5 gate driver is used in a conventional cascaded bootstrap configuration.As there are only 3 high-side switches, and silicon MOSFETs are used, not wide-bandgap devices that are highly sensitive to gate drive voltage, the diode voltage drop in this configuration does not negatively impact the circuit performance.The tallest component in the prototype is the inductor at 0.126 in (3.2 mm).On the bottom side of the board, the tallest component is the drivers with a height of 0.04 in (1 mm).Note that on the bottom side of the board 0805 size capacitors (also with a height of 1 mm) are selected.This way the overall height of the converter is minimized, allowing for higher power density to be achieved.Including the board thickness of 0.06 in this gives the overall height of 0.226 in, or 5.74 mm.The MOSFETs selected have a footprint of 3 mm ×3 mm.The inductor voltage will be the difference between V sw21 and the output voltage.This voltage difference will be a summation of the capacitor ripple voltages, dependent on the circuit state.What should be noted, however, is that the voltage is very small compared to the input or output voltages, allowing for a very small inductor to be used.
For 48 V input the output voltage characteristic of the ZIV converter is presented for the full load operating range in Fig. 22.As expected, based on the analysis, the output voltage decreases linearly in proportion to the load current.The efficiency measurements for the ZIV converter for both 48 V and 60 V input are presented in Fig. 23 as measured using a Keithley 2 700 multimeter and Reidon RSN series current shunts The maximum output current of the prototype is 70 A. For 48 V input, and 12 V output, the measured full load efficiency is 97.2% including the gate drive loss.The peak efficiency for 48 V input is 99.1%.As compared with Ref. [18] which achieves 12 V/60 A efficiency of 97.2%, the ZIV converter prototype achieves a 12 V 60 A efficiency of 97.8%.For 48 V input, the maximum converter output is 12 V/70 A. The power density of the converter for this output condition is Fig. 23 Measured efficiency for two-phase experimental prototype including gate drive loss then 2 500 W/in 3 .This matches the highest power density yet demonstrated in literature by Ref. [18], while achieving higher overall efficiency.
It should be noted that the maximum load current of 70 A is selected based on thermal considerations.If more powerful cooling is utilized this converter design can output higher current.The saturation current of the selected inductors is 22 A, meaning this two-phase design could theoretically output up to 88 A (just over 1 kW output power) with sufficient cooling.

Conclusions
Switched capacitor converters offer significant benefits over many conventional PWM based topologies including reduction in MOSFET voltage stress, and the ability to remove bulky and lossy magnetic components.However, the sensitivity of many SCC topologies to manufacturing tolerances and challenges scaling to differing power levels (through techniques such as paralleling multiple phases) have limited their adoption.
In the ZIV converter topology the critical advantages are maintained, namely reduction in MOSFET voltage stress and ability to use very small magnetic components, without many of the critical drawbacks.The ZIV converter is naturally soft-charged, therefore there is no loss due to charge redistribution and no need to introduce additional inductive elements or complex control to address this.As a conduction loss dominated converter the ZIV converter can be easily paralleled, allowing for scalability to differing power levels.The ZIV converter does not rely on a resonant design, and therefore is not sensitive to component manufacturing tolerances.
The two-phase 12-switch ZIV converter prototype presented in this paper achieves a power density of 2 500 W/in 3 , with a peak efficiency above 99% and a full load 12 V/70 A efficiency of 97.2%.In terms of power density, this matches the highest yet demonstrated for 48 V to 12 V conversion by the cascaded resonant converter while achieving higher efficiency.
The reason for this efficiency improvement can be seen by examining the relative current and voltage stresses for the components in the 12-switch ZIV converter as compared with the cascaded resonant converter.Both converter topologies require 2 inductors per phase, however, in the 12-switch ZIV converter both of these inductors carry 1/2I out as their RMS current.In the cascaded resonant converter, one inductor will carry 1/2I out and one inductor will carry the full load current.The ZIV converter requires 12 switches per phase instead of 8, however, all 12 switches in the ZIV converter carry 1/2I out when switched on.In the cascaded resonant converter only 8 switches are required, but while 4 of these switches will carry 1/2I out , 4 of the switches will carry the full load current.Similarly, the current stress of the second stage flying capacitor in the cascaded resonant converter will be equal to the full load current, while in the 12-switch ZIV converter both second stage flying capacitors C f21 and C f22 carry only 1/2I out .This means that the overall conduction loss, the dominant source of loss in the converter, is reduced.While the cascaded resonant converter eliminates switching loss due to the resonant operation, the conduction loss dominates the overall loss and therefore the reduced current stress of the ZIV converter allows for higher efficiency to be achieved without needing a resonant based design.

Fig. 1
Fig. 1 Comparison of converter topologies for 48 V to 12 V conversion

Fig. 5
Fig. 5 Equivalent circuits in operating states A, B and C

Fig. 7
Fig. 7 12-switch ZIV converter topology PWM gate drive diagram V LA is the inductor voltage in State A, V LB is the inductor voltage in State B, V LC is the inductor voltage in State C, V Cf 1-A and V Cf 2-A are the two flying capacitor voltages in State A, V Cf1-B and V Cf2-B are the two flying capacitor voltages in State B, and V Cf 2-C is the second flying capacitor voltage in State C.

Fig. 9
Fig. 9 Simulated capacitor voltage ripple and inductor voltages 25 A load 60 kHz switching frequency

Fig. 14
Fig. 14 Input voltage, C f1 and C f2 start-up voltage waveforms Fig.15shows the measured prototype efficiency (including gate-drive loss) using Reidon RSN series (0.1% error) current shunts as well as a Keithley 2 700 digital multimeter.A small USB desk fan is used to cool the prototype.With a more powerful fan, or additional heat sinking, a higher load current could have been achieved as the inductor saturation current is 49 A.

Fig. 20
Fig. 20 Top view (left) and bottom view (right) for one phase of two-phase experimental prototype (1 in×0.75 in×0.226in)

Fig. 21
Fig. 21 Experimental prototype waveforms for 48 V input 50 A load

Fig. 22
Fig. 22 Measured prototype output voltage characteristic in State A must be equal to the average voltage of C f1 for State B, as C f1 is charged for 25% of the switching cycle in State A, discharged for 25% of the switching cycle in State B, and is disconnected in State C For C f2 the average voltage of C f2 across both States A and B must be equal to the average voltage of C f2 across State C.This is because C f2 is charged for 25% of the switching cycle in State A, continues to be charged for an additional 25% of switching cycle in State B, and then is discharged for the remaining 50% of the switching cycle in State C