A Novel 5-level Flying Capacitor Bridgeless PFC Converter Based on Cost-effective Low-voltage eGaN FETs *

: In this study, a type of multilevel flying capacitor bridgeless PFC converter is proposed that permits the use of economical and efficient 100 V GaN transistors. Compared with the popular two-level totem-pole bridgeless PFC converters achieved using the much more expensive 650 V GaN devices, this new design has several distinct advantages: lower component costs, lower d v/ d t , lower power losses, and reduced concerns about device reliability. A 1.6 kW, 5-level PFC converter prototype is designed and fabricated with an efficiency of 99.18% and a power factor of 0.99, which are experimentally demonstrated. The operation principle, design considerations, control strategy and experimental results are discussed.


Introduction1
Power factor correction (PFC) converters are widely used in modern power supplies for computers, data centers, and telecommunication equipment to suppress harmonics and improve power quality [1] .
Among various types of PFC topologies, the totem-pole bridgeless PFC (TPBPFC) topology reduces the number of conduction switch components from 3 to 2 compared with the boost PFC topology, thereby significantly reducing the conduction voltage drop and conduction losses. However, the TPBPFC, which uses Si SJ MOSFETs with the inherent reverse recovery of the body diode, cannot operate in the continuous conduction mode (CCM) at a relatively high frequency [2] . Operating the TPBPFC in the discrete conduction mode (DCM) to minimize the adverse impact of the body diode is an effective solution in theory. However, issues such as higher current stress on each switch and higher harmonics in the input current may arise in the DCM operation of a Manuscript received May 23, 2020; revised July 29, 2020; accepted August 18, 2020. Date of publication September 30, 2020; date of current version August 31, 2020. * Corresponding Author, E-mail: yingeng@hnu.edu.cn * Supported by the National Natural Science Foundation of China (51977068). Digital Object Identifier: 10.23919/CJEE.2020.000019 TPBPFC. Moreover, due to the switching frequency of the silicon-based PFC converters, which is limited to below 100 kHz, it is difficult to obtain small magnetic components and achieve a high power density. In recent years, hybrid switches (HyS) based on Si IGBT and SiC MOSFET have been studied [3] . However, the mainstream 400 V PFC design generally adopts a CCM-operated boost topology using 600 V Si SJ and could provide an efficiency of 99% even in a hard-switching design [4][5][6] . Although the turn-on loss of the GaN FETs is much lower than that of the Si SJ MOSFETs, this still accounts for a vital portion of the total GaN TPBPFC power losses, which restricts the switching frequency and the power density of GaN TPBPFCs [7][8] . To achieve a higher power density, a 5-level flying capacitor bridgeless totem-pole PFC (5L-TPBPFC) converter topology, which achieves a higher switching frequency, is proposed in this study.
The new 5L-TPBPFC allows the use of 100 V GaN transistors and it is both economical and efficient while significantly reducing the switching loss, harmonics, and dv/dt. Moreover, the current price of 650 V GaN transistors is 5 to 8 times that of silicon transistors, while the cost of low-voltage (40 V/60 V/100 V/200 V) eGaN FETs is close to that of silicon [9] . The combination of eGaN FETs and flying capacitor technology in bridgeless PFCs also provides the following advantages：① A decrease of the inductor volume. As the level number is increased, the overall frequency of the converter can be greatly increased. Correspondingly, in high-level FC DC-DC converters, the inductor volume can be greatly reduced [10] . ② Improved reliability. The increased number of switches in multilevel converters results in redundant switching states and fault tolerance [11][12] . A reliability analysis of multilevel inverters in Ref. [13] claims that the system availability can be improved compared to 2-level systems, although a higher number of devices is required. ③ Improved EMI. As far as the influence of switching actions is concerned, a faster switching speed will generate higher EMI noise levels in the high frequency range [14] . However, in high-level FCMCs built with low-voltage GaN FETs, the voltage stress on a switch is small, the switching frequency is lower, and the EMI issue can be greatly improved. Therefore, the development of PFC converters using low-cost, low-voltage GaN FETs is highly attractive. This study provides a comprehensive introduction to the operation principles, design considerations, control strategy, and experimental results of a 1.6 kW PFC design based on this concept.
The rest of the paper is organized as follows.
Section 2 presents an introduction of the proposed 5L-TPBPFC topology, along with its advantages compared to conventional topologies. Section 3 reveals the control strategy for the proposed 5L-TPBPFC. In section 4, a 1.6 kW hardware prototype is presented along with experimental results to validate our design concept. Finally, the conclusions are provided in section 5.

Multilevel flying capacitor TPBPFC topologies
This section compares the proposed 5L-TPBPFC converter and the popular 2L-TPBPFC converter. The specific operation and superior qualities of the 5L-TPBPFC are illustrated.
The schematic topology of the popular TPBFC based on 650 V GaN FETs is shown in Fig. 1a, while   The converter is required to be adaptive to a general line voltage of 90 V to 265 V automatically in a bridgeless PFC, as well as to provide a quasi-regulated DC output-voltage V o . The switching node voltage V sw and input voltage V in for the popular 2L-TPBPFC are both exhibited in Fig. 2a. As shown in Fig. 2b, the pulse width modulator with the duty cycle is calculated to obtain the control signal S. If S = 0, V sw = 0 V, and if S = 1, V sw = V DC . In the 5L-TPBPFC, the voltages of the flying capacitors C 1 -C 3 must be maintained at 3V o /4, 2V o /4, and V o /4, respectively, such that the electrical stresses on each switch are balanced. Therefore, the voltage drop on each switch is V o /4. Fig. 2c exhibits five different voltage classes in which pulse width modulation (PWM) can be utilized. Consequently, the voltage pulses that are experienced by the inductor are four times less than those of the conventional boost converter. The current loop of the proposed 5L-TPBPFC is the same as that of the 2L-TPBPFC. Switches S 1a to S 4b in the 2L-TPBPFC topology can be controlled by using the phase-shifted carrier pulse width modulation (PSCPWM) signal in the linear modulation area. In the 5L-TPBPFC topology, however, switches S 1 to S 4 are controlled by the PWM signal with a duty ratio, as exhibited in Fig. 2d. Note that the phase-shifted angle from the adjacent PWM signal is 90°. In this way, the system can naturally reach equilibrium.
In addition, the 5L-TPBPFC topology can considerably reduce the volume of the main inductor. For a popular 2L-TPBPFC, the value L 2L of the main inductor is determined by the specified maximum ripple of inductor current ΔI where V L is the voltage drop of inductor and T L is the charging time. From Eq. (1), the maximum product of V L and T L is required to attain a maximum ΔI. Suppose that V m represents the peak of the line voltage, I m indicates the peak of the input current, T represents the switching period, V o represents the output voltage, P o represents the output power, and %Ripple represents the rate of the ripple. The value of L 2L can then be expressed as where A represents the coefficient for normalization. With an N-level topology, the voltage ripple experienced by the inductor is reduced by N-1 times and the frequency experienced by the inductor is increased by N-1 times. Therefore, L NL can be expressed as  Fig. 3 shows that the main inductor L NL is determined by the maximum equivalent duty ratio D m , the coefficient for normalization A, and the circuit level number N, as in 2L-, 3L-, 5L-, and 7L-TPBPFCs. In N-level TPBPFCs, the maximum of L NL always appears in the first interval of Eq. (4), which starts from 0. Therefore, it can be expressed as It is known that the multilevel topologies can significantly reduce L NL . Furthermore, the volume of the magnetic components can be reduced while the power density of the system can be significantly increased.
The area product theory [22] can be used to estimate the volume of an inductor. Moreover, the inductor core volume V can be expressed as a function of a constant K and the area product A p 0.75 4 0.75 2 (10 ) where B m is the flux density, J is the current density, K u is the window utilization factor, and W is the energy stored in an inductance. W can be expressed as The inductor core volume V can be estimated by considering the required energy of an inductor, as expressed by Eq. (7). L is the value of the inductance. Furthermore, Eq. (7) can also be expressed for an N-level TPBPFC and 2L-TPBPFC as 2 2 2 By considering L 2L as a reference, the required inductor core volume of an N-level TPBPFC may be expressed as follows 0.75 Therefore, the required inductor core volume in an N-level TPBPFC can be reduced compared to the 2L-TPBPFC. Fig. 4 shows the reduction of the inductor core volumes in the 3L-, 5L-, and 7L-TPBPFCs, which are approximately 65%, 87.5%, and 93.2%, respectively, with respect to the 2L-TPBPFC. The comparison of the inductor volumes between the 2-level and 5-level topologies is shown in Fig. 5. It is obvious that the volume of inductance is significantly reduced as the number of levels is increased. Therefore, the inductance and core volume of the boost inductor are reduced when a multilevel TPBPFC with a higher number of levels is considered compared to the 2L-TPBPFC. Consequently, the size and weight of the converter is reduced.

Control strategy
The 5L-TPBPFC enables improved power density and efficiency, while its distinct characteristics may change the parameters of the PFC. In this section, we will analyze the control performance of the PFC while considering the influence of parameter variations.
The control block diagram of 5L-TPBPFC is shown in Fig. 6. The system specifications are listed in Tab. 2. It is known that the control scheme consists of two control loops that are based on the average current control. The outer loop manages the load voltage by regulating the value of the current reference, while the inner loop is designed to control the inductor current i L to follow the current reference. The PFC can realize a close-to-unity power factor and steady load voltage with these two control loops. The small signal transfer function from the duty ratio to the inductor current can be calculated as [23] 2 2 2 2 where V in is the input voltage, V o is the load voltage, R, C and L are the resistance, inductance and capacity in the circuit, respectively. Moreover, d top and d bottom are the duty ratios of the top and bottom switches, respectively.
Eq. (10) is calculated using the system specifications listed in Tab. 3 and shown in Fig. 7a. Due to the digital controller, there is a phase lag, which is shown as G iLd;z in Fig. 7a. Therefore, we will discuss a discrete model G iLd;z . A type-II compensator represented as G c;z is adopted in the current loop to improve the feedback loop. The loop gain after compensating is shown in Fig. 7b.
As shown in Fig. 7b, for G iLd;z , a pair of resonant poles (f r ) appear near 1 kHz. For a traditional PFC with a boost topology, the main inductor L is usually large (e.g., mH), resulting in a worst case f r below 50 Hz. Therefore, the gain at the line frequency is not affected. However, for the PFC presented in this study, the main inductor is greatly reduced. Therefore, the worst resonant pole frequency f r in this case may appear above 50 Hz, leading a significant reduction of the loop gain at the line frequency. Additionally, i L may undergo a significant phase shift and distortion with respect to V in . To overcome these issues, a type-II compensator is adopted in the inner loop. In this way, the compensated loop gain remains flat on the left side of f r and the loop gain at the line frequency is above 50 dB. Therefore, the input current may better follow the reference value. Moreover, the disturbance from the input voltage can be effectively rejected with such a high gain [24] .

Experimental results
To verify our design experimentally, a 5L-TPBPFC prototype was built, as shown in Fig. 8. The system specifications are listed in Tab. 3. The controller is based on an Artix-7 100T AX7102. To analyze the operation characteristics of the 5L-TPBPFC topology, the converter is operated under two kinds of inputs, i.e., 220 Vrms, 50 Hz, and 110 Vrms, at 50 Hz conditions. Fig. 8 Hardware circuit of the 5L-TPBPFC converter Fig. 9 shows the experimental waveforms of system states: V in (input voltage), V o (output voltage), i L (input current), and V sw (switching node voltage) under various input AC voltages. As shown in Fig. 9, the output DC voltage is boosted to 400 V and the switching node voltage V sw shows a staircase waveform with 100 V increments and a weak imbalance. Under an input of 220 Vrms and 50 Hz, the V sw transitions through 5 levels from 0 V to 400 V and follows the trajectory of the rectified input voltage V in . Under an input of 110 Vrms and 50 Hz, only 3 levels are available because the peak value of V in is less than that of the third level. Note that in the different half cycles of V in , the power devices in the top or bottom bridge arms alternately operate as the main switch. The switches in the top and bottom bridge arms are therefore complementary. Thus, when V in is in the positive half cycle, V sw is in the negative half cycle. Therefore, a voltage jump occurs when V sw crosses zero. kW, which is 98.04%. Fig. 11 shows the PF curve and the input current's THD curve of the 5L-TPBPFC topology under input voltages of 100 V and 220 V, respectively. It can be seen in Fig. 11a that the PF of the converter under a full-load operation is always above 0.99 under the two different voltages. In Fig. 11b, it can be seen that the THD of the converter under a full-load operation is always under 5% under the two different voltages. Furthermore, the minimum values of the THD are 3.2% and 2.5% under 220 and 110 V, respectively. The 5L-TPBPFC design concept is therefore verified by the collected prototype data.