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Rapid exploration of cost-performance tradeoffs using dominance effect during design of hardware accelerators

Sedaghat Reza (Ryerson University, Electrical and Computer Engineering, Toronto, Canada)
Sengupta Anirban (Computer Science and Engineering, Indian Institute of Technology, Indore, India)

Modern Very Large Scale Integration (VLSI) designs require a tradeoff between cost efficiency and performance (circuit speed). Furthermore, the Design Space Exploration (DSE) of the cost-performance tradeoffs for the multi objective VLSI designs should also be fast and efficient in nature. This paper presents a novel accelerated DSE approach for the exploration of cost-performance tradeoffs of modular multi (trio parametric. viz. cost, execution time and power consumption) objective VLSI hardware accelerators using hierarchical criterion analysis. The selection of the final design point is made after the tradeoffs are explored using the proposed approach. Results of the proposed approach when applied to various benchmarks yielded significant acceleration in the exploration process compared to current existing approaches with multi parametric objective.

Keywords: hardware accelerator, rapid, exploration, performance, cost