Electrical Сharacterization of Ge-FinFET Transistor Based on Nanoscale Channel Dimensions

Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors’ dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate and a successor to conventional planar devices in nanoscale technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest of researchers in both academia and industry. However, aggressively scaling down of channel dimensions, will degrade the overall performance due to detrimental short channel effects. In this paper, we investigate the impact of downscaling of nano-channel dimensions of Germanium Fin Feld Effect Transistor (Ge-FinFET) on electrical characteristics of the transistor, namely; ION/IOFF ratio, Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to conduct a simulation study to achieve optimal channel dimensions by considering channel length (L), width (W), and oxide thickness (TOX) individually. In addition, the effects of simultaneous consideration of all dimensions by exploiting a scaling factor, K was evaluated. According to the obtained simulation results, the best performance of Ge-FinFET was achieved at a minimal scaling factor, K  0.25 with 5 nm channel length, 2.5 nm width, and 0.625 nm oxide thickness.


INTRODUCTION
Fin Field Effect Transistor (FinFET) has shown a great potential in scalability and manufacturability as a promising candidate in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies [1,2]. The structure of FinFET provides superior electrical control over the channel conduction, thus, it has attracted widespread interest from researchers in both academia and industry [3]. However, tremendous downscaling of channel dimensions, mainly the channel length, will degrade the overall performance due to detrimental short channel effects (SCEs) such as to leakages, energy consumption, electrostatics, in addition to other fabrication issues [4][5][6].
The applications of Nanoelectronic have benefited enormously from the great advancement in the emerging Nano-technology industry [7,8]. The name of Fin-FET technology comes from the fact that the structure of FET looks like a set of fins when viewed [9]. Such type of gate structure provides an improved electrical control over the channel conduction and it helps in reducing leakage current levels and overcoming some other issues related to short-channel such as electrostatic limits and source-to-drain tunneling [10]. These issues represent constraints in the design and fabrication of transistors beyond Nano-Dimensional channel length in conventional MOSFET [11,12].
More new FET structures are being explored on a large scale. One of these structures was the FinFET, which has attracted a widespread of researchers in both academia and industry of semiconductors [13], thanks to the vertical fin that determines the source channel discharge. It will be appreciated that the FinFETs can be used with (25 nm) gate length as they have the ability to provide high current immunity and high immunity to SCEs [6]. FinFET was born as a result of the continuous increase in integration levels. Control over the reduced channel length of FinFET is more complicated and more important. This is because the conduction occurs thus in two parallel channels that are in vertical planes the conduction remaining parallel to the substrate surface between drain and source area. The drain current is flowing on both sides of the fin is a way to increase the discharge source for the same area in the channel region. Thus, efforts and attentions to finding a solution for this issues are highly increased.
In this paper, we simulate and analyze the effects of reducing channel dimensions [length (L), width (W), and oxide thickness (TOX)] of Germanium Fin Feld Effect Transistor (Ge-FinFET) on its performance in terms of FOUR (4) electrical characteristics, namely, (i) ION/IOFF ratio, (ii) Subthreshold Swing (SS), (iii) Threshold voltage (VT), and (iv) Drain-induced barrier lowering (DIBL). Moreover, we propose a scaling factor K to downscale all dimensions (L, W, and TOX) as once and detect the best performance based on the selected scaling factor. According to simulation results, we have designed the best nanoscale channel dimensions of Ge-FinFET based on the highest ION/IOFF ratio and the best SS characteristics.

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The remaining part of this paper is structured as follows. Section II introduces the experimental methods adopted for this research. Section III contains the simulation results and discussions. Finally, the conclusions are presented in Section IV.

MuGFET Simulator
The well-known MuGFET which is developed and designed by Purdue University (USA) is utilized to develop the simulation model of this study. There are two modes of simulation in MuGFET either PADRE or PROPHET. The PADRE is a device-oriented simulator for 2D or 3D devices with arbitrary geometry, whereas the PROPHET is a partial differential equation profiler for one, two or three dimensions. These simulation tools can generate different characteristics of FETs transistors to understand the underlying physics behavior of FETs. It can also provide self-consistent solutions to poison and drift-diffusion equations.

Simulation Model
MuGFET is utilized to investigate the characteristics of the Ge-FinFET transistor by varying dimensions of channel. Electrical characteristics based on the I-V relation under various conditions and based on different parameters are studied and evaluated. The effects of variable channel dimensions, namely; channel length, width and oxide thickness in addition to scaling factor of the Ge-FinFET transistor, are determined. In particular, the Id-Vg characteristics of Ge-FinFET at the temperature of 300 K are simulated and analyzed. The setting of simulation parameters in this study are listed in Table 1.
In order to evaluate electrical characteristics of Ge-FinFET based on channel's dimensions, FOUR (4) simulation scenarios were designed for different simulation parameters. The first scenario focused on impact of varying channel length only, while keeping other dimensions (W and TOX) constant. The second scenario investigated electrical characteristics based on various channel widths, while both length and oxide thickness of channel were unchanged. In the third scenario, only oxide thickness was changed and other dimensions were kept constant. The last scenario was designed for simultaneous consideration of all dimensions, L, W, and TOX by changing scaling factor K to decrease all dimensions and evaluate transistor performance for each value of K.

Downscaling Channel Length Scenario
In this scenario, the impact of scaling down of channel length L on the characteristics of Ge FinFET has been studied. The channel length L was changed between 10 and 40 nm, whereas W and TOX were kept constant at default values of MuGFET which are 5 nm and 2.5 nm, respectively. The simulation of transfer characteristics (drain current Id -gate voltage Vg) has been conducted with different channel lengths L.
Based on the obtained results, the ION/IOFF ratio proportionally increases with channel length at both voltages, VDD  5 V and 0.5 V. As illustrated in Table 2, the maximum value of the ION/IOFF ratio is more than 10 4 at L  40 nm. For L range from 10 to 30 nm, the highest ION/IOFF ratio is for VDD  0.5 V, while for 30 to 40 nm L range the highest ION/IOFF ratio occurs for VDD  5 V. The relation between SS characteristic and channel lengths is also investigated. Results show that the SS is improved as the channel length increased and reached to 65 mV/dec the nearest value to the ideal SS at L  40 nm. Similarly, the threshold voltage (VT) gains some increment with increasing the channel length, where VT  0.43 V at the maximum L of 40 nm and VT  0.20 V at the minimum L of 10 nm. Conversely, drain-induced barrier lowering (DIBL) of the Ge-FinFET reduces with increasing channel length and reaches to 4.8 mV/V at L  40 nm. According to the obtained characteristics in this scenario, the best performance in terms of all performance metrics can be achieved in case with 40 nm channel length. Therefore, it is obvious that with considering channel length only, we cannot go far in downscaling channel dimensions due to the degradation of transistor performance, especially in short length channel.

Downscaling Channel Width Scenario
The impact of scaling down channel width W on the considered performance metrics of Ge-FinFET has been evaluated in this scenario. The value of W was decreased from 20 nm to 5 nm, while L and TOX were fixed to 40 nm and 2.5 nm, respectively. Unlike the previous scenario, the downscaling of channel width improved the performance of transistor in terms of all characteristics. The best performance was achieved with the smallest channel width, W  5 nm where the ION/IOFF ratio is more than 10 5 and SS  62 mV/dec according to the results in Table 3.
The improvement in Ge-FinFET with shrinking channel width is also obvious in terms of threshold voltage and DIBL. The VT is inversely proportional to channel width, where VT  0.435 V at the minimum channel width of 5 nm and VT  0.24 V at the maximum channel width of 20 nm. Meanwhile, the DIBL is proportional to channel width and it attains the minimum and best value of 4.9 mV/V when W  20 nm.

Downscaling Channel Oxide Thickness Scenario
The behaviour of Ge-FinFET in terms of most electrical characteristics with scaling down channel oxide thickness is consistent with previous scenario of channel width variation. As the oxide thickness of channel decreased, characteristics were enhanced, even though the improvement is less comparing with the widthbased scenario. For the simulation scenario carried out in this phase, the channel oxide thickness TOX has been changed (1.5, 2.5, 5 and 7 nm), while both channel length and width were kept constant at 40 and 10 nm, respectively. The obtained results prove the variation of ION/IOFF ratio with the channel oxide thickness. The best ION/IOFF ratio was greater than 10 4 and was obtained with VDD  5 V at minimum TOX  1.5 nm and then decreased to 10 2 at TOX  7 nm. Almost similar results were obtained for 0.5 V voltage which represents the nearest voltage to OFF state voltage (0 V). We noticed from the results that for a channel oxide thickness TOX  1.5 nm the Ge-FinFET has shown better SS characteristics with the best SS value of 67 mV/dec compared to other TOX values. Conversely, the farthest value from ideal SS (59.5 mV/dec) occurred at TOX  7 nm, where SS is 229 mV/dec. Furthermore, an improvement in terms of both VT and DIBL characteristics of Ge-FinFET was achieved by decreasing channel oxide thickness. While the voltage threshold increased linearly with decreasing TOX, the DIBL was not consistent and its value fluctuating with different oxide thickness. The best and highest threshold voltage was VT  0.35 V at the smallest channel oxide thickness of 1.5 nm. Similarly, DIBL achieved the smallest value of 19 mV/V at the minimal TOX.

Scaling Factor of Channel Dimensions
According to the aforementioned scenarios, the best performance in terms of the considered electrical characteristics was achieved at channel length L  40 nm, channel width W  5 nm, and channel oxide thickness TOX  1.5 nm. Thus, Ge-FinFET has not achieved a proper performance with a shrinking channel length where it attains better performance at the longest channel case. In order to scaling down all channel dimensions as once, we have applied a scaling factor K on all dimensions including length, width and thickness. Following we study the electrical characteristics based on scaling factor, the reference value of K is defined as "1" with its highest channel dimensions. Then, all dimensions are scaling down to reach to new physical limits for the channel of Ge-FinFET. All corresponding dimensions to the defend scaling factors are shown in Table 3.     Fig. 2 shows the worst SS characteristic value (100 mV/dec) that is obtained at K  1. In contrast, the nearest value to the ideal SS is 68.9 mV/dec was acquired at K  0.25. It can be notice that with increasing K, the SS value increases significantly. Likewise, the impact of changing Scaling Factor (K) on VT and DIBL is illustrated in Fig. 3, where the highest value of VT  0.64 V is obtained at K  0.25, compared to the lowest value VT  0.33 V at K  1. On the other hand, the DIBL value ranges from 356 mV/V to 111 mV/V between minimum and maximum value of K, respectively, with inconsistent behaviour in between as illustrated in Fig. 4.
According to the simulation results of this scenario, we have achieved very small physical limits for Nanochannel dimensions by applying a scaling factor K. The overall results of this study were summarized in Table 2 with highlighting on the channel dimensions for best performance in all scenarios. The best results are highlighted in different color.

CONCLUSIONS
We have demonstrated the electrical characteristics of Ge-FinFE based on various channel dimensions. Our calculation of the best performance was achieved at highest ION/IOFF ratio and the nearest SS to the ideal value in different simulation scenarios using MuGFET. We have changed dimensions individuality to study the impact of each (L, W, TOX) on the different extracted characteristics (ION/IOFF ratio at two voltages, SS, VT, and DIBL) of Ge-FinFET. In the following we have investigated the effect of scaling factor K to scaling down all dimensions to their mammal value with appropriate performance. We observed that by variation of the dimensions scaling factor, it can be possible to design new physical limits for channel dimensions with increasing the ION/IOFF ratio and enhancing SS, VT and DIBL characteristics.