Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero-Dielectric Gate (HDG)

Purpose: A TFET (Tunnel Field Effect Transistor) is a potential candidate to replace CMOS in deep-submicron region due to its lower SS (subthreshold swing, <60 mV/decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two drawbacks a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Method: To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the closed form of compact analytical current model for HDG TFET structure without using any iterative method. Result: The developed compact analytical models show a good agreement with 2-D TCAD simulator results. The model is used to study in depth about the electrical behavior of the device under various physical variation as well as bias variation. Conclusion: The proposed model can be incorporated into SPICE to describe the behavior of HDG TFET faster.


Introduction
In recent years, tunnel field effect transistor (TFET) has received attention of the researchers due to its lower subthreshold swing (<60 mV/decade) at room temperature [1][2][3][4][5][6] which makes TFET as an ideal choice to replace CMOS in design of power efficient nanoscale circuit. N-TFET devices employ band-to-band tunneling (BTBT) process to inject the carriers from valence band of source to conduction band of channel [7][8]. However, TFET suffers from two major drawbacks of lower on-current than the conventional MOSFET and larger ambipolar current [9][10]. To overcome these drawbacks, a number of alternative design techniques as well as non-planar structures have been proposed in the literature. Among these, band gap engineering [11][12], gate oxide engineering [13][14], source/drain material engineering [15][16], multi gate technique [17][18][19][20] have been proposed to enhance the on current in the TFET. Gatedrain overlap structure [21][22] was suggested in the literature to suppress the ambipolar current. Each technique has its own advantage and disadvantage. Dual metal gate TFET has been proposed to enhance the oncurrent and suppress the ambipolar current [23][24][25]. However, main concern for this technique is that one has to choose appropriate work function for auxiliary gate to overcome both drawbacks at the same time. Chandan Kumar Pandey et al [26] has proposed dielectric pocket in TFET to suppress the ambipolar conduction. In this technique, they have replaced the upper portion of drain region with high κ-DP (dielectric pocket) at the channel-drain interface which increases the minimum tunneling width and hence suppresses the ambipolar current on the cost of on-current. Junsu Yu et al [27] has reduced the ambipolar current in TFET using a stacked gate in Lshaped. The main drawback of this method is an extra processing steps.
A hetero-dielectric gate (HDG) TFET has been proposed by researchers to increase the on-current and suppress the ambipolar current in the device [28][29][30][31][32]. In this proposed structure, high-κ oxide is placed near the source to induce a local minima of conduction band edge of the tunneling junction and low-κ oxide is placed near drain to suppress the ambipolar current. The electrical characteristics of these HDG TFET devices are mostly predicted with the help of TCAD simulator [33][34]. Far fast circuit simulation and to provide in depth understanding of the working principle of the HDG TFET, it is required to develop an analytical compact models. In the literature, various analytical models were proposed [35][36][37][38][39][40] but these models are either based on iterative methods or many assumptions. However, no compact closed form of drain current analytical expression of single gate HDG TFET structure is available in the literature.
In this paper, we have developed a compact close form of analytical expression for drain current of HDG TFET structure without using any iterative method. The expression is developed using 2-D Poisson equation and parabolic approximation. For the simplification of analysis, we have ignored the source/drain depletion width due to heavy doping and quantum confinement effect due to silicon film thickness larger than 3 nm. The model's results show a good agreement with 2-D TCAD simulator results which confirms the validity of the proposed models. The proposed current model, can be incorporated into Spice for fast simulation and better understanding of the electrical behavior of single gate HDG TFET. This paper is organized as: Section 2 describes the device structure. Section 3 explains the derivation of the analytical models from the solution of 2-D Poisson equation whereas section 4 elaborates on the results. At the end, we conclude the paper in section 5.

Device Structure
The 2-D structure and coordinate system of the proposed N-type hetero-dielectric gate TFET (HDG TFET) is shown in Figure 1. The whole channel of length L is divided into two regions, namely, Region I of high-κoxide near source with length L1 and Region II of low-κ-oxide near drain of length L2. The high κ-material near the source-channel interface is placed to increase the tunneling current whereas low-κ-material near drain to suppress the ambipolar current. The channel is practically undoped (≈10 15 /cm 3 ), the p + source and n + drain is heavily doped (~10 20 /cm 3 and 5x10 18 /cm 3 respectively).
Initially, the high-κ oxide thickness tox1 and the low-κ oxide thickness tox2 are equally set as 3 nm. The gate metal work function for two regions is taken as 4.25 eV unless and until specified. In the present analysis, we have ignored the source/drain depletion region due to heavy doping and the quantum mechanical effect due to silicon film thickness of 5 nm.
To validate the developed analytical models, we used 2-D TCAD simulator results, under the assumptions of the non-local band-toband tunneling (BTBT), the band gap narrowing, Fermi-Dirac statistics, Shockley-Read-Hall (SRH) recombination and doping dependent mobility for comparison.

Analytical Models
The 2-D Poisson's equation can be used to describe the potential behavior of the proposed TFET structure across the two regions. After neglecting the fixed carrier oxide charges, 2-D Poisson's equation, governing the potential distribution ψj(x,y) in the respective region, is given as; Where, Na is the channel doping concentration, j=1, 2 represents the region I and region II, εsi is the silicon permittivity, ψj(x,y) is the 2-D electrostatic potential in the region I and II measured with respect to Fermi potential. Solution of this differential equation (1) can be obtained by assuming parabolic profile along the film thickness tsi as [40]; Where, a0, aj1, aj2 are constants and function of x-only. The value of these unknowns can be obtained by using appropriate Boundary Conditions (BCs) [40].

(a)Surface and Channel Potential
Following the same procedure, as mentioned in our earlier paper [40], differential equation (1) can be reduced to 2-D scaling equation,  is the built-in-potential at the respective interface and given as are the doping concentration of the source and drain regions, ni is the intrinsic carrier concentration. Using BCs 5(a) to 5(d) and after mathematical simplification, the value of the constants is, Substituting the value of these constants in equation (4), the analytical expression of the surface potential in the respective region can be obtained. After determining the surface potential, the channel potential is given as, 1 4 The transverse and the lateral electric field in the proposed TFET can be determined using equation (6) and relations, And thus the total electric field is Tunneling width is an important parameter to determine the tunneling current from sourceto-channel as well as ambipolar current from drain-channel in the TFET device. This parameter exhibits transition from strong dependence to weak dependence on the gate voltage. The tunneling path is defined as the lateral distance between two tunneling points 1 x and 2 x where 1 x is the initial tunneling point and 2 x is the final tunneling point. The initial tunneling point is defined as the value of x for which surface potential changes by [41]. In the present paper, the initial tunneling point is assumed to confined in region 1.
Using q and substituting the value of surface potential of region 1, the analytical expression for the initial tunneling point (after mathematical simplification) is given as; The initial tunneling point plays an important and decisive role to determine the tunneling current. The shorten 1 increases the probability of tunneling of carriers and hence results in larger tunneling current. The final tunneling point 2 is defined as the lateral distance between = 0 to a point where surface potential reaches to the value of the channel potential [41]. Using this definition and after mathematical simplification, we get tunneling point is also confined in region I due to high dielectric material in the source channel region. A similar approach can be used to determine the tunneling points in region II derive analytical expression for the ambipolar current.

(c) Tunneling current
In non-local BTBT, tunneling of charges start only when conduction band edge (CB) of source gets in line with the valence band edge (VB) of the channel region [41]. The tunneling current can be obtained by integrating Kane's band-to-band tunneling (BTBT) generation rate over the entire tunneling volume in both radial and lateral directions as [41]; Where GBTBT is the generation rate of the carriers and given as 8.6 × 10 6 V/cm.eV 3/2 , respectively. Eav is average electric field, E is the resultant field, and D is fitting parameter (its value is either 2 or 2.5 depending upon the nature of semiconductor material).
In the present paper, we have derived the analytical expression for the tunneling current in the radial direction of the channel from initial tunneling point 1 to final tunneling point 2 . It is assumed that the tunneling current is uniform across the channel width Wch and effective channel thickness tsi. Therefore, equation 9(a) reduces to

11(b)
This expression is derived without any iteration and much approximations.

Results and Discussion
We have analyzed the developed analytical models in detail to understand the electrical characteristics of the proposed device in terms of surface potential, electric field and drain current. The study is also helpful to get in-depth understanding of the gate engineered structure. The values of various parameters used in the model are; L=30 nm, L1=15-20 nm, tsi=5 nm and tox=3 nm unless and until specified. The source region and drain region are heavily doped with dopant concentration of 10 20 /cm 3 and 5x10 18 /cm 3 respectively whereas channel region is lightly doped with 5x10 15 /cm 3

dopant concentration.
To validate the developed analytical models, results were compared with 2-D TCAD simulator.   We have analyzed the effect of length L1 on the surface potential of the proposed structure. As LI decreases, conduction band becomes shallower which results in lower tunneling of carriers whereas the increase in L1 results in wider conduction band as seen from Figure 2(c). This result suggests that an optimized value of L1=15 nm is a good choice to control the tunneling and ambipolar currents in the device.     We have analyzed the lateral as well as transverse electric field of region II as shown in Figure 4(a). Both the fields increase as the dielectric constant κ-increases. From analytical results, it is observed that for κ≤ 4, fields take negative value. The negative field in drain-channel region deaccelerates the carriers and hence suppresses the ambipolar current. From this result, it is clear that SiO2 dielectric material near drain-channel region, is the natural choice to control the ambipolar current. shows the variation of lateral electric field in region I along the channel for single dielectric gate TFET and hetero dielectric gate TFET for κ=25 and κ=50. It is observed that field takes larger value near source-channel junction for κ=50 due to better control of gate over the channel. The peak of the lateral electric field near the source-channel interface is responsible for the larger tunneling probability.  We have studied the transfer characteristics of single dielectric gate TFET and hetero dielectric gate TFET as shown in Figure 5(b). Single dielectric gate TFET is studied under two cases; case 1 when gate is occupied by SiO2. Case 2 when gate is occupied by HfO2dielectric material. In case 2, we have larger on-current compared to case 1 but hetero dielectric gate TFET provides lower ambipolar current and larger ON current compare to the single dielectric TFET. To further investigate the effect of dielectric material on the drain current of the proposed structure, we have plotted the graph as shown in Figure 5(c). The analytical results show that larger on-current and lower ambipolar current is obtained when region I is occupied by larger dielectric material of strength κ=50 and region II is occupied by SiO2. The result concludes that an improved on-current and decreased SS can be obtained using gate engineering. To see the effect of work function on the drain current of the hetero dielectric gate TFET, we have studied the current for single metal TFET and two other cases namely; dual metal gate with tunnel gate having higher work function and dual metal gate with auxiliary gate having larger work function. The result is shown in Figure 5(d). Due to reduction of the tunnel gate work function compare to auxiliary gate, the band width overlap increases which results in narrow tunneling width and hence ultimately increase in on-current on the cost of increased ambipolar current. This result also suggests that the work function difference results in change in surface potential which improves the gate control over tunneling process. A narrow tunneling width gives larger tunneling probability of carriers. Therefore, we can conclude that gate dielectric engineering along with choice of metal can be employed in HDG TFEET design to enhance the tunnel current and reduce the ambipolar current. Since, the length of region I (L1) determines the tunneling barrier width in the source region, it is observed that as L1 increases the tunneling current enhances on the cost of increased ambipolar current as seen in Figure  5(e). The lower ambipolar current and acceptable on-current in the proposed structure is obtained when L1=15 nm for L=30 nm. Therefore, for the better electrical performance of the device, we have chosen the optimized value of L1=15 nm instead of L1=20 nm on the cost of slight decrease in on-current. This result also confirms the finding that as L1 decreases, BTBT becomes difficult due to shallower conduction band well whereas an increase in L1 results in less abrupt transition between on-and off-state due to wider conduction band. The silicon film thickness tsi is the critical parameter for better gate control over the channel. The lower tunneling width is achieved for lower tsi which results in higher tunneling probability and hence larger tunneling current (on current) as seen from Figure 6(a). The lower silicon film thickness also reduces the ambipolar current. Figure  6(a) shows that on-current decreases with increase in film thickness. For better oncurrent and lower off-current in the device, the optimized value of the tsi=6 nm. From our proposed analytical results, it was observed that higher gate dielectric material in source-channel region provides larger tunneling current as long as tsi<12 nm ( Figure  6(b)). This study only reflects that using gate engineering and lower film thickness, one can enhance the tunneling current and suppress the ambipolar current in TFET device. The improved on-current can result in decreased SS as well as controlled SCEs. From this observation, it is concluded that careful choice of the gate dielectric material near source and film thickness can improve the on-current and reduce SS of HDG TFET.   Therefore, the proposed structure HDG TFET can be a potential candidate for replacing convention MOSFET in deep submicron region due to larger on-current, lower SS and controlled SCEs as well as reduced ambipolar current which can be further improved by utilizing gate engineering as well as material engineering in the design.

Conclusion
A compact analytical model of drain current has been proposed for single gate HDG TFET without any iterative method. The proposed model gives close form without much approximations. The model is derived based on surface potential approach with parabolic approximation. The results of analytical models show a good agreement with 2-D ATLAS simulator results which establish the validity of the proposed model. Due to reduction of work function of tunneling region, a narrow tunneling width is achieved which enhances the on-current in device. It is also observed that a thinner silicon film result in larger drain current. The proposed structure results in lower SS and controlled SCEs due to gate engineering and material engineering combination.

Funding:
No funds, grants or other support was received

Competing interests
Authors declare that there is no competing interest

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In the present paper, there is no data or materials which are required to be disclosed or shared

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Authors are giving their consent for the publication of this research paper

Authors' contributions
Each author has same contribution

Acknowledgement
Authors are thankful to Dr Ganapathirao Maradana, NIIT University for his valuable suggestions regarding the mathematical issues.

Disclosure of potential conflicts of interest
There is no conflict of interest involved in this work

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