Performance Assessment of Dual Material Stack Gate Oxide TFET using Dielectric Pocket

This paper investigates the impact of low-K and high-K dielectric pockets on DC characteristics, analog/RF, and linearity performance of dual material stack gate oxide-tunnel ﬁeld-eﬀect transistor (DMSGO-DP-TFET). For this, a stack gate oxide with workfunction is considered to enhance the ON-state cur-rent ( I ON ), lower ambipolar current ( I amb ) and lower the subthreshold swing. For this case, the gate elec-trode is tri-segmented, named as tunnel gate ( M 1 ), con-trol gate ( M 2 ) and auxiliary gate ( M 3 ) with diﬀerent gate lengths ( L 1 , L 2 , L 3 ) and work functions ( φ 1 , φ 2 , φ 3 ), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination ( φ 1 = φ 3 < φ 2 ) outperforms as compared to other combinations. Where φ 1 on the source side is used to enhance the I ON , while φ 3 (equal to φ 1 ) is used on the drain side to minimize the I amb . To further enhance the device performance, a high-K di-electric pocket is considered at the drain junction to suppress the I amb whereas, a low-K dielectric pocket is employed at the source junction to enhance the I ON . Moreover, length of gate segments, dielectric pocket height, and thickness are optimized to achieve a bet-ter switching ratio, subthreshold swing (SS) and reduce the I amb which helps in the gain of device and design of analog/ RF circuits. The proposed device as compared to dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO 2 gate oxide shows im-Kaushal provement in I ON / I OF F ( ∼ 4.23 times), 84 % increase in transconductance ( g m ), 136 % increase in cut-oﬀ frequency ( f T ), 126 % increase in gain bandwidth prod-uct (GBP), point subthreshold swing (15.8 mV/decade) and other signiﬁcant improvements in linearity ﬁgure of merits (FOMs) making the proposed device useful for low power switching, analog/RF and linearity applications.


Introduction
MOSFETs are widely used for low-power switching, analog/RF design, and wireless communication systems. To further improve the performance and increase the packing density, MOSFET dimensions are aggressively down-scaling [1,2]. This inevitably results in some critical issues, such as high subthreshold leakage current, short channel effects (SCEs), and SS restriction of 60 mV/decade [3,4]. These challenges make conventional MOSFETs unfavorable for future low power switching and analog/RF applications.
To address the above issues, an alternate device structure based on quantum tunneling-FET (TFET) is considered one of the possible replacements of MOS-FETs for low-power switching circuits due to lower leakage current, steeper SS below 60 mV/decade and immunity to SCEs [5]- [7]. These features make TFETs more favourable for low-power, energy-efficient circuits. However, the major limitations of this device is inferior I ON and ambipolar behavior [8]. TFETs can be used in digital complementary logic circuits and high-frequency applications only if the ambipolar current of the de-vice is suppressed. Ambipolar current implies the flow of current for both positive and negative V GS [9]. This happens as the tunneling junction is transferred from source to drain side by applying V GS < 0 (in case of ntype TFET). Because of ambipolar current, SS degradation and efficiency of the device for the complimentary digital logic circuits and high-frequency applications is limited [10,11].
The ON-current of the TFETs is inferior due to inadequate band-to-band tunneling (BTBT) rate at the source junction. In TFET, high lateral electric field is required across the source junction to lower the tunneling barrier width and improve the tunneling current. As per the Wentzel-Kramers-Brillouin method, the BTBT probability depends exponentially on the width of the tunneling barrier, effective bandgap, the effective mass of charge carrier, and the energy band overlap [24].
In recent literature, researchers have made numerous efforts and proposed different methods to suppress the ambipolar current, improve the DC, analog/RF and linearity performance. Raad et al. [12] proposed a TFET based on hetero dielectric and workfunction engineer-ing (HGD-DW TFET) and reported an I ON /I OF F ra-tio of (9.8×10 11 ), g m of 0.290 mS, f T as (∼ 59.6 GH Z ). Kondekar et al. [13] proposed TFET based on electrically doping (ED-TFET) to enhance the analog and radio frequency performance and reported an I ON /I OF F ratio of (∼ 10 12 ), g m as 1.02 mS, f T of (190 GH Z ). Nigam et al. [14] proposed a charge plasma based TFET (DMCG-CPTFET) and obtained an I ON /I OF F ratio of (∼ 6 ×10 12 ), I amb as 1×10 −17 (A/µm), f T of (∼ 28 GH Z ). Ashita et al. [15] investigated a inverted-C TFET (ICTFET) with SCOPs which provides both lateral and vertical tunneling to boost the ON cur-rent. The authors have reported I ON /I OF F ratio of (4.5×10 9 ), SS of (48 mV/decade), f T of (1.19 GH Z ). Chandan et al. [16] proposed a metal strip based TFET (MS-ED-TFET) to overcome low switching ratio, SS and analog/ RF performance and acheived an I ON /I OF F of (8.92×10 8 ), SS of (8.07 mV/decade), g m of 0.007 mS, f T as (0.17 GH Z ). Shaikh et al. [17] presented a quadruplegate TFET with drain engineering (DE-QG-TFET) and acheived an I ON /I OF F ratio of (1.79 ×10 12 ), f T of (∼ 34 GH Z ), g m of 0.261 mS, GBP of (3.9 GH Z ). kumar et al. [18] proposed a stack-gate ap-proach TFET with dual material (DMDODG-TFET) to and reported an I ON / I OF F ratio of (5 ×10 11 ), SS of ( 18.5 mV/decade), f T of (∼ 8.8 GH Z ), g m of 0.09 mS. Joshi et al. [19] investigated an extended source TFET (ESDG-TFET) and reported an I ON /I OF F of (2.57×10 12 ), SS of (12.24 mV/decade), g m of 0.238 mS, f T of (37.7 GH Z ) In this work, we propose DMSGO-DP-TFET to address the ON-current, ambipolarity, and improve the analog/RF, and linearity performance. For this, the combination of (φ 3 < φ 2 ) workfunction and high-K dielectric pocket at the drain junction leads to an increased tunneling barrier width and reduced lateral electric field. As a result, ambipolar current reduces when negative V GS is applied. Similarly, (φ 1 < φ 2 ) work function and the low-K dielectric pocket at the source junction reduces the tunneling width (λ) and increases the lateral electric field, which results in an improved tunneling current.
This paper is organized as follows: Section 2 presents the structural, simulation details and process flow. Section 3 presents the structural optimization results. Section 4 describes the DC, analog/RF, and linearity performance. Lastly, Section 5 concludes the main findings of this work.
2 Device structure, parameters, simulation setup and process flow The 2D structural view of the proposed DMSGO-DP-TFET for the parameters listed in Table 1 is illus-trated in Fig. 1. The length of the stack gate (SiO 2 +HfO 2 ) is considered 50 nm with SiO 2 layer thickness of (0.8 nm) and HfO 2 oxide layer thickness of (1.2 nm) [18]. Further, the entire gate is split into three segments la-belled as tunnel gate (M 1 ), control gate (M 2 ) and aux-iliary gate (M 3 ) with lengths (L 1 , L 2 , L 3 ) and work functions (φ 1 , φ 2 , φ 3 ) respectively. In the case of single-material stack gate oxidedielectric pocket-TFET (SMSGO-  [20]. In DMSGO-TFET without dielectric pocket I ON /I OF F is noted as 2.25×10 11 . A low-K dielectric pocket is considered at the source junction to increase the I ON . Whereas, high-K dielectric pocket at the drain junction to lower the I OF F . Due to this, I ON /I OF F is noted as 2.83 ×10 12 in the proposed device using the TCAD simulations. The proposed device structure is simulated using a 2-D device simulator Atlas Silvaco V5.19.20. In our simulation, nonlocal band-to-band tunneling (BTBT) model, which uses the Wentzel-Kramers-Brillouin method, is considered to measure the tunneling probability across the junction. For this, the quantum tunneling regions are defined at source/channel interface for the consideration of tunneling of carriers in the ON-state, whereas at drain/channel interface for the consideration of ambipolar behaviour of the device. Shockley-Read-Hall model is enabled to consider minority carrier recombination effects for numerical solutions. The bandgap narrowing method (BGN) is used due to heavily doped concentrations in source and drain regions. FLDMOB mobility model is used to consider the velocity saturation effects because of the lateral electrical field. The simulation study carried out in this work uses a nonlocal BTBT model calibrated with the data reported in [8], which was previously calibrated, with the experimental data obtained from the fabricated device [21]. Fig. 2 shows the comparison of results reported in [8] and the proposed device using TCAD.
The proposed device can be fabricated using the similar method reported in [19,26]. The conceptual process flow of the proposed device is illustrated in Fig.  3(a)-(j). Firstly, a p-i-n structure can be formed using epitaxial growth process as shown in Fig. 3(a) and Fig.  3(b) shows the deposition of high-K and low-K dielectrics at the drain and source junctions. In the next step, etching is done to form the dielectric pock-ets as shown in Fig. 3(c). Then, SiO 2 can be grown on the p-i-n structure by the oxidation process as il-lustrated in Fig.  3(d). Atomic layer deposition (ALD) is used to deposit a thin HfO 2 film as illustrated in Fig. 3(e). In the nextstep, as shown in Fig. 3(f), cre-ation of the control gate can be done using masking and metallization of molybdenum (Mo) material. Moreover, auxiliary and tunnel gates can also metalized with alu-minium (Al) material using the self-aligned symmet-rical spacer method as illustrated in Fig. 3(g). Next, selective etching can be done for electrode formation as illustrated in Fig. 3(h). Similarly, the back gate formation can be done as illustrated in Fig. 3(i). Finally, Fig.  3(j) presents the metallization and patterning of source and drain contacts using Mo material as it provides the workfunction ranges from 4.36 eV to 4.95 eV 3 Results and discussion

Workfunction optimization Results
To align the band structure at the source and drain junctions and to modulate the carriers through the chan-nel, the entire gate length of DMSGO-DP-TFET is tri segmented known as tunnel gate (M 1 ), control gate (M 2 ), and auxiliary gate (M 3 ) with workfunctions φ 1 , φ 2 and φ 3 , respectively as illustrated in Fig. 1. By fixing (φ 1 and φ 3 ) and varying (φ 2 ), better switching ratio and minimum ambipolar current is observed for the combination (φ 1 = φ 3 < φ 2 ) as illustrated in Fig. 4(a) and table 2. Fig. 4(b) and Fig. 4(c) shows ON-state and the OFFstate band diagrams for the proposed DMSGO-DP-TFET by varying (φ 2 ) and fixing (φ 1 = φ 3 = 4.0 eV). From Fig. 4(c), it can be seen that tunneling width increases with an increase in (φ 2 ). This results in band overlap decrease on the source side and decreases the tunneling current. Whereas, the band overlap has been noted at the drain junction for (φ 2 > 4.4 eV) and tunneling is observed in the OFF state, also (φ 2 ) work function variation in the ON-state does not shows a significant change in the tunneling current until the workfunction (φ 2 = 4.4 eV). Also, as shown in Fig. 4(c), a decrease in band overlap is seen for (φ 2 > 4.4 eV), which results in a decrease in ON-state current (I ON )

Dielectric pocket optimization results
To further improve I ON and minimize the ambipolar current, optimized low-K and high -K dielectric pock-ets are inserted at the source and drain junctions, respectively. Fig. 5(a) shows the comparative I DS -V GS characteristics for different dielectric materials at the source and drain junctions in DMSGO-DP-TFET. Results demonstrate that combination of low-K dielectric pocket (air) at the source junction and high-K dielec-tric pocket (HfO 2 ) at the drain junction shows higher I ON and minimum ambipolar current because of tun-neling width and band alignment at the source and drain junctions. From the same figure, it can be noted that pocket thickness of 2 nm at the tunneling junction shows better tunneling current I ON and minimum ambipolar current due to the band alignments at the source and drain junctions, respectively.

Gate length optimization
In this section, the gate segments of the proposed device is optimized. In this regard, Tables III-V shows the variations in I ON , I OF F , I amb , I ON /I OF F for various combinations of L 1 , L 2 and L 3 . The optimization of L 3 at constant L 1 = 10 nm is shown in Table III. Further, the optimization of L 1 at constant L 3 = 15 nm is shown in Table IV. Table V   I amb . However, L 1 = L 3 = 10 nm shows better results in terms of I ON /I OF F and is considered as optimized gate lengths in this work.
For the optimized dielectric pockets illustrated in Fig. 1, based on (φ 1 , φ 2 , φ 3 ), various device structures can be formed as presented in Table 6. Further, a comparative analysis among these devices is done in terms of their carrier concentration, band diagrams, tunneling rate, surface potential, electric field variation, and I DS -V GS characteristics. For SMSGO-TFET, all the three workfunctions (φ 1 , φ 2 , φ 3 ) of the gate material has been considered equal (4.4 eV). Fig. 6(a) depicts the carrier concentration variation with distance for SMSGO-DP-TFET, DMSGO-DP-TFET1, DMSGO-DP-TFET2 and DMSGO-DP-TFET. From the figure, it has been noted that, due to the dielectric pocket at the source junc-tion and dual material with work-function combination (φ 1 = φ 3 < φ 2 ), higher electron concentration is ob-served for DMSGO-DP-TFET due to decrease in tun-neling width as illustrated in Fig. 6(b). Therefore, bet-ter band-to band tunneling rate is observed for DMSGO-DP-TFET as shown in Fig. 6(c). Further, large increase in surface potential and electric field is observed at the source junction for DMSGO-DP-TFET as illustrated in Fig.  6(d) and Fig. 6(e), respectively. Thus, maximum tunneling occurs at the source junction, as the BTBT rate (G BT BT ) at the tunneling junction depends on the       electric field (ε) leads to an increase in BTBT rate as per the expression [22].
Where A, B are constants which are related to the electron's effective mass and the tunnelling probability, ε is the electric field and σ is the transition constant. Further, the probability of tunneling of the carrier (T W KB ) at the tunneling barrier is analyzed by the approximation of Wentzel-Kramer-Brillouin (WKB) [23].
Where m * is the effective mass of an electron, q represents the electron charge, h represents Plank's constant, E g is the effective bandgap, λ is the width of tunneling barrier, and ∆φ represents the energy overlap where the tunneling occurs. Therefore, as shown in Fig. 6(f), a significant increase in tunneling current is observed. Fig. 6 and Table 7 show that DMSGO-DP-TFET performs better than other device structures.

DC characteristics
In this section, comparative DC characteristics of DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET has been analyzed. In this regard, the elec-tric field variation with distance for the above device structures are illustrated in Fig. 7(a). From the simulation results, a higher electric field at the source junc-tion is noted for DMSGO-DP-TFET, as a result, mini-mum tunneling barrier width is noted for DMSGO-DP-TFET as illustrated in Fig. 7(b). Further, Fig. 7(c) il-lustrates the comparative I DS -V GS characteristics vari-ation of DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET. From the figure, a sig-nificant increase in ON-state current is observed for DMSGO-DP-TFET because BTBT depends on the elec-tric field and tunneling width at the source junction [22]. current I DS rises at first as V DS increases from 0 to 0.8 V, then saturates because of velocity saturation as V DS increases beyond 0.8 V. The tunneling current does not change significantly from V DS = 0.8 V onwards, so the current remains constant. Further, noted that due to employment of dielectric pockets at the source and drain junctions, reduced V T , improved ON-state current, reduced ambipolar current, steep subthreshold slope(SS) and a higher switching ratio (2.83×10 12 ) was observed for DMSGO-DP-TFET compared with other structures as illustrated in Fig. 7 and Table 8.

Analog/RF figure of merits
This section presents performance analysis of DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO- Table 7 Performance comparison of sigle material and dual material TFET with dielectric pockets   Parameters  SMSGO-DP-TFET DMSGO-DP-TFET1 DMSGO-DP-TFET2 DMSGO-DP-TFET [25]. In this regard, Fig. 8(a) depicts the comparative plots of g m variation with V GS at V DS = 1 V. From the figure, it has been noted that in the subthreshold region g m of all the devices are very small, and it starts increasing due to increase in the ON-state current. Moreover, it starts decreasing after a particular value of V GS due to mobility degra-dation [24]. Results also show that DMSGO-DP-TFET exhibits higher g m as compared to other device struc-tures.
The next analog/RF performance parameter considered for analysis is output conductance (g DS ). A device with higher (g DS ) is preferred as it provides higher intrinsic gain. In this regard, Fig. 8(b) depicts the variation of g DS with drain voltage (V DS ). Results demonstrates higher output conductance for DMSGO-DP-TFET due to higher δI DS shown by DMSGO-DP-TFET for the similar changes in δV DS . Fig. 8(c) shows the comparative R O variation with V DS for constant V GS . From the results, lower R O is observed for DMSGO-DP-TFET as g DS is higher. The variation of C gs and C gd obtained from small-signal ac analysis at 1MHz fre-quency is illustrated in Fig. 8(d) and Fig. 8(e). From the results, it has been noted that DMCG-DP-TFET shows the minimum value of C gs , and for DMSGO-DP-TFET, a significant increase of C gd is noted above V GS = 0.85 V.
Another critical parameter for RF performance analysis of the device is cutoff frequency (f T ). It is the frequency at which the current gain becomes unity [24]. Fig.  8(f) depicts f T variation with V GS for DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET. Results demonstrates that, initially, f T in-creases with V GS due to an increase in g m , then de-creases with V GS after reaching the peak value due to an increase in C gd and decrease in g m due to mobility degradation. From the results, a higher f T is obtained for DMSGO-DP-TFET which indicates that the proposed device structure is more favourable for radio frequency applications. The f T of the device is formulated as per the expression [24].
GBP is another important parameter for the radio frequency performance analysis of the device, for a specified dc voltage gain of 10, it is calculated using the expression [24].
The GBP variations with V GS for DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET are illustrated in Fig. 9(a). Results demonstrate that, GBP initially increases as V GS increases, but it decreases for higher V GS due to the similar reasons as discussed ear-lier for f T . Also, maximum GBP is noted for DMSGO-DP-TFET compared to other device structures. The TGF parameter indicates how efficiently the current reaches a certain transconductance value. In this re-gard, Fig. 9(b) shows the comparative TGF variation with V GS . From the results, for DMSGO-DP-TFET, higher TGF is observed at lower V GS and with increase in V GS it starts decreasing as the variation in I DS is small. The TGF is obtained as follows Fig. 9(c) shows the comparative variation of TFP with V GS at V DS = 1 V. From the results, it can be noted that DMSGO-DP-TFET shows higher TFP due to high g m and f T . The TFP is obtained as follows Fig. 9(d) depicts the comparative transit time (tau) variation with V GS at V DS = 1 V. It is the time taken for carriers to move from the source to the drain [20]. The results show that as V GS increases, transit time decreases due to increased f T . Also, the minimum transit time was noted for DMSGO-DP-TFET.
The maximum oscillating frequency (f max ) is another crucial parameter for radio frequency performance analysis. It is calculated by using the equation Here, R gd represents the gate resistance. Fig. 9(e) shows the f max variation with V GS for DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET at V DS = 1.0 V. From the figure, it has been noted that DMSGO-DP-TFET shows higher value of f max due to higher value of f T .

Linearity figure of merits
This section presents the linearity and distortion FOMs, such as g m3 , VIP2, VIP3, IIP3, and IMD3 for DMCG-TFET, DMCG-DP-TFET, DMSGO-TFET and DMSGO-DP-TFET which has been explained in [25]. These are defined as follows: V IP 3 = 24 × g m1 g m3 (10) Fig. 10(a) and Fig. 10(b) shows the comparative g m3 and g m3 variations with V GS at V DS = 1.0 V. From the figure, peak values of g m3 and g m3 can be seen at lower V GS in DMSGO-DP-TFET as compared with other devices. A higher values of VIP2 and VIP3 is required for better linearity and minimal distortion. In this re-gard, Fig. 10(c) and Fig. 10(d) depicts the comparative VIP2 and VIP3 variations with V GS at V DS = 1.0 V. Simulation results demonstrate that VIP2 and VIP3 of DMSGO-DP-TFET is higher than the other struc-tures. This indicates that DMSGO-DP-TFET is more linear than other devices. The next linearity and dis-tortion performance parameter for analysis is IMD3, it originates from the non-linearity characteristics of I DS -V GS and seems to be a distorting signal in wireless systems. Devices with lower IMD3 values can have the ability to withstand higher signal distortion. In this regard, Fig. 10(e) shows the comparative IMD3 variation with V GS at V DS = 1.0 V. From the figure, IMD3 of DMCG-TFET is noted to be smallest, indicating that the DMCG-TFET intermodulation distortion performance is the best of the above devices. The next linearity performance parameter for analysis is IIP3, for better linearity of the device IIP3 value should be high. In this regard, Fig. 10(f) shows the comparative IIP3 variation with V GS at V DS = 1.0 V. Results demon-strate that IIP3 for DMSGO-DP-TFET is much higher, which indicates that DMSGO-DP-TFET is more linear as compared to other structures.

Conlusion
In this work, a DMSGO-DP-TFET with dielectric pockets at the drain and source junctions is proposed. The structural parameters like gate lengths (L 1 , L 2 , L 3 ), work functions (φ 1 , φ 2 , φ 3 ), pocket height and thick-ness are optimized to achieve better switching ratio and reduce the ambipolar current. The performance of the proposed device is analyzed using TCAD device simulator. Finally, a comparative performance analysis of the proposed device is done with other device struc-tures and noted the combination of low-K and high-K dielectric pockets at the source and drain junctions and workfunction combination (φ 1 = φ 3 < φ 2 ) on the stack gate oxide in the proposed device shows significant improvements in I ON /I OF F , SS, g m , f T , R O , transit time (τ), GBP, TGF, TFP, f max , VIP2, VIP3, IMD3 and IIP3 given in table 8. The performance of the proposed device is compared with the recent literature shown in Table 9 which shows that the proposed device useful for low power switching, high frequency and linearity applications.