Tunable Intermediate-Logic Ternary Circuits based on MoSe 2 -WSe 2 Heterojunction

Van der Waals (vdW) heterojunctions, which consist of p-type and n-type semiconductors, have provided new features for transition metal dichalcogenides (TMDs). In this work, a negative heterojunction (MoSe 2 -WSe 2 H-TR) is proposed. The MoSe 2 -WSe 2 H-TR provides desirable device characteristics for ternary circuit operation with a switching behavior of off-state / p-type turn-on / NDT region / p-type turn-on. As a result, a 100% output voltage ( V OUT ) swing inverter can be achieved in a ternary inverter, which consists of the proposed MoSe 2 -WSe 2 vdW-H-TR and a MoS 2 floating-gate transistor. Furthermore, a tunable intermediate-logic ternary circuit operation is demonstrated by controlling the threshold voltage ( V TH ) in a pull-down n-type MoS 2 floating-gate transistor. We also investigated that a light-induced operation on the MoSe 2 -WSe 2 vdW-H-TR offers control of the V OUT amplitude at the intermediate-logic state. Based on the proposed MoSe 2 -WSe 2 vdW-H-TR, this work suggests a strategy to obtain a tunable ternary circuit, thus providing a new concept of heterojunction electronics using layered TMDs.

One of the emerging electronic functions arising from the vdW-H is a new switching behavior, which includes negative differential resistance (NDR) or negative differential transconductance (NDT) characteristics. [19][20][21] This new switching characteristic does not behave monotonically, i.e., the current does not continuously increase as the applied voltage increases. There is NDT regions, where the current decreases when the applied voltage is in the middle of its range. Due to this unique switching behavior, a new circuit scheme for ternary logic has been proposed. In the complementary circuit consisting of two serially connected transistors, where one transistor is a vdW-H transistor with NDT, the charging pull-up transistor has a comparable resistance region with the discharging pull-down transistor. 22,23 As a result, the vdW-H-based circuit offers an additional output voltage (VOUT) state at which both transistors have a comparable resistance. Thus, ternary logic operation can be achieved. As the ternary circuit has an extra logic state, more efficient logic computing is potentially provided.
However, the transition from binary to ternary logic circuit results in the reduction of the circuit's noise margin. Specifically, the maximum noise margin of a ternary logic circuit is 33% of the VDD (VDD is divided by three logic states), while the maximum noise margin of a binary logic circuit is 50% of the VDD (VDD is divided by two logic states). 24 As a result, it is very important to accurately control each logic state margin circuit as the number of logic level states increases. However, previously reported vdW-H-based ternary circuits include: (1) incomplete output voltage swing [25][26][27] and (2) narrow margin for the intermediate-logic state. [28][29][30] These issues must be addressed to make the ternary circuit suitable to practical applications. Therefore, it is necessary to investigate how to implement vdW-H-based logic more systematically.
Here, we report a new combination of MoSe2-WSe2 vdW-H, providing desirable electrical properties for ternary circuit operation.

Results and Discussion
First, the MoSe2-WSe2 vdW-H was fabricated using a polydimethylsiloxane (PDMS) stamp method. 31 WSe2 was deposited on the top of MoSe2 to form a partial overlap in the middle of the channel between the source and drain electrode. As a result, the one contact electrode makes contact with the MoSe2 only, while the other contact electrode makes contact with the WSe2 only (Figure 1a Figure S1). The coexistence of MoSe2 and WSe2 is also supported by the binding energy peaks of Mo 3d, W 4f, and Se 3d in the measured X-ray photoelectron spectroscopy (XPS) spectra ( Figure S2). [35][36][37] The measured AFM shows the MoSe2-WSe2 vdW-H formation structure in the middle of the transistor channel region ( Figure S3).
We investigated the electrical characteristics of the fabricated MoSe2-WSe2 vdW-H-TR. We prepared a baseline MoSe2 and WSe2 transistors were prepared as baseline n-type and p-type devices, respectively ( Figure S4). The measured transfer characteristics of the baseline MoSe2 transistor exhibit n-type dominant ambipolar characteristics with an effective electron and effective hole mobility ( Figure 1d and Table S1). In contrast, the baseline WSe2 transistor exhibits p-type dominant ambipolar characteristics with an effective electron and effective hole mobility ( Figure 1d and Table S1). These n-type dominant and p-type dominant ambipolar characteristics are also supported by the measured output curves, which exhibit a linear current increase due to counterflow (i.e., hole current in the n-type operation and electron current in the p-type operation) ( Figure S5 Figure S10). In the VG = 40 V to −7 V range, the WSe2 p-channel begins to accumulate hole carriers, contributing to ID increase. In about the middle of the range (VG = −7 V), both MoSe2 and WSe2 accumulate hole and electron carriers, contributing to ID increase. Accordingly, the peak of ID (the highest ID value) was observed in this voltage range. In the −47 V < VG < −7 V range, ID decreases, since the MoSe2 n-channel becomes depleted by the applied negative bias VG. As the negative VG increases further, the turn-on of the MoSe2 p-channel contributes to ID increase due to the ambipolar characteristics of the MoSe2. It is worth noting that ID increases again, when further negative bias is applied (VG < −47 V). This is because the MoSe2 contributes to electron carrier accumulation due to its ambipolar charge transport properties (Figure 1d It is emphasized that the maximum NDT and voltage range values obtained in the MoSe2-WSe2 vdW-H-TR are larger than in previously reported TMDs-based heterojunction transistors (Table S2) In the NDT region, ID increases as the applied Pinc increases. This is shown in the plots of Ipeak and Ivalley, which depend on the illumination Pinc (Figure 3g and 3h). In the NDT region, an enhancement in ID under illumination was observed. The NDT results from the depletion of the MoSe2 channel (as described in Figure 1) and the photocurrent generation in the MoSe2 by the light illumination lead to an increase in ID in this region of the NDT. The peak-to-valley ratio and maximum negative gm decrease as the applied Pinc increases. This is due to the increase in ID in the NDT region by light illumination (Figure 3i and 3j). Additional measurements and their analysis of the photoresponsive WSe2, MoSe2, MoSe2-WSe2 vdW-H-TR are given in Figure S14-S16. Figure S14a and S14b shows the transfer curves of baseline

Data availability
All data during this project are included in this article and supplementary information.