CJFET Differential Pairs Constructions and Characteristics for Design of CBiCJFet Differential Amplifiers and Differential Difference Amplifiers

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage Δ 𝑉 𝐺𝑆 depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using 𝑝 + buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. 𝐺𝑆 decreases, and with increasing drain-source voltage Δ 𝑉 𝐺𝑆 at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference Δ 𝑉 𝐺𝑆 was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread Δ 𝑉 𝐺𝑆 was shown: for example, for the drain current 𝐼 𝐷 = 50 𝜇𝐴 the voltage spread Δ 𝑉 𝐺𝑆 did not exceed 10 mV. In this case the voltage spread Δ 𝑉 𝐺𝑆 practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: Δ 𝑉 𝐺𝑆 reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on Δ 𝑉 𝐺𝑆 was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

A process, developed by SPE "Pulsar" [21], allows to design analog ICs, containing JFets and HF complementary bipolar transistors. But bipolar active elements (especially p-n-p) have extremely low values of base current gain in cryogenic temperatures range. So to build low-temperature and low noise sensor interfaces and input stage of corresponding special analog ICs it is appropriate to implement only on CJFet components. This limitation causes development problem for analog ICs' functional unit base CJFet, on base of which it is possible to develop different OA, continuously operating voltage stabilizers, current and voltage comparators, active ARC etc. Todays' level of CJFet's circuitry is very low and not developed. It causes a problem of CJFet analog OM circuitry, it is more compliacated than the one for CMOS and BJ processes. Its reason is different static voltage polarity between source and gate of JFet in active mode (comparing with drain-source polarity). As a consequence the following is required firstly to design CJFet analog OM: special CJFet current mirrors (CM), which are not implemented per circuits traditional for CMOS and BJT, CJFet input differential stages, buffer amplifiers (BA) with source output, railto-rail CJFet BA, input stages of fast CJFet AM, intermediate folded cascode, static mode stabilizer circuit (reference current sources and potential offset circuit), operational amplifiers with increased gain, fast CJFet OA, micropower CJFet OA, differential difference amplifier, OTA amplifiers with controled slope etc. Conceptually we need updated concept for developing wide class of analog CJFet ICs, which practically were not developed because of dominant impact of cheap techology for CMOS and BJ and small production of low temperature microelectronic devices. However modern necessities of space instrumentation, high energy physics, medicine, quantum computing systems, high speed railway transport etc. stimulate development of this scientific direction. The above circuitry tasks are of high priority.
The methods to increase identity of JFet DP are connected with JFet rational construction and its implementation technology [21]. It is known that CBi-pCJFet process in BiCom3HV modification of Texas Instruments company [22,23] allows developing new precision operational amplifiers OPA211 and OPA827 wth JFet and BJT, which combine ultralow level of noise coefficient and low power consumtion. The said amplifiers are characterized by enabling parameters. BiCom3HV process makes possible to provide next generation of analog electronic component base, it includes all best microelectronic achievements. But OPA211 and OPA827 operate at temperatures of -40 0 С and higher according to BiCom3HV process, which is provided by bipolar transistors application. It is not enough for several tasks.
The purpose of this article is to develop and describe process and construction solutions, which provide identity improvement for CJFet DP with p-and nchannels, integrated into silicon complementary bipolar technological process of SPE "Puslar" (Moscow). -top gate development due to active base and polysilicon emitter of npn-transistor.
There are drain-gate characteristics of p-channel JFets differential pair at 5 V and 10 V of drain voltage.
A dependence of drain-source voltage nonidentity ∆ from drain current is defined for the above contruction of p-channel JFets (Fig. 3). The Fig. 3 shows that ∆ reduces when current increases, and ∆ increases at high currents, when drain-source voltage increases. A spread of voltages ∆ does not go below 80 mV in a drain current rage up to 50 A. The parameters of p-channel JFET second construction (Type 2) are the following: -development of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor, when a distance between drain/souce areas are 6.6 m; -channel development based on p-layer collector of pnp-transistor; -development of bottom gate using p+ buried layer; -top gate development due to passive base. There are drain-gate characteristics of second type p-channel JFets differential pair at 5 V and 10 V on drain. (a) There is a dependence of drain-source ∆ voltage spread on drain current for this pair of transistors. The Fig. 5 shows that the second type JFet differential pair has significantly smaller spread of voltages ∆ . For example, a voltage spread ∆ does not exceed 10 V for drain current = 50 A. In this case the voltage spread ∆ practially does not depend on drain-source voltage in contrast to differenctial pair of the first type.

n-Channel JFet Differential
Pairs made by SPE "Pulsar" and Their Basic Characteristics There is a topology of n-channel Fets differential pair on Fig. 6. It includes the following sections: S-area -source, G-area -top gate, D-area -drain. There are drain-gate charactrisitics of n-channel JFets at 5 V and 10 V on drain for differential pairs of the first and second types on Fig. 7 and 8 correspondently. Thus it is reasonable to compare these transistors at drain current of 10 A, but not at 50 A (as was done for p-channel transistors).
Dependence ∆ on drain current ( Fig. 9) for the first type n-channel transistors differential pair substantially similar to the difference of the first type p-channel JFet differential pair (Fig. 3). But there is significantly weaker influence of drain-source voltage for n-channel JFet at higher current density. ∆ for drain current = 10 mA does not exceed 30 mV. The values of voltage spread ∆ are significanly lower: from 5 to 21 mV for the second type n-channel transistors (Fig. 10). ∆ is not higher than 8 mV at = 10 A. Similar to p-channel transistors (Type 2) there is an optimum value of drain current at which there is a minimum of ∆ . When the drain current increases any further, ∆ weakly depends on drain current value similarly to all considered types of differential pairs. So it is defined, that to provide minimum values of spread ∆ for JFet differential pair, including considerting low temperature influence, it is reasonalbe to use the second type of p-n junction complementary field-effect transistors construction.

Conclusion
We have developed constructions of p-and nchannel JFets, included into silicon complementary bipolar process of SPE "Pulsar", which provide relatively high identity of drain-gate characteristics at their differential input ( ≤ 5÷10 mV) and possibility to develop CBiCFet integral circuits.