Design of a Novel Optimized Mac Unit Using Modified Fault Tolerant Vedic Multiplier

In this study, the design of optimized Multiplication and Accumulation (MAC) unit with modified Vedic multiplier is presented. To design a MAC unit, efficient multiplier is used to increase speed and to reduce area and power. Conventional MAC is designed using without fault tolerant Vedic multiplier. But it consumes more area and power. And also less delay. So MAC unit is changed to design the efficient Vedic multiplier. Conventional MAC unit with regular Vedic multiplier is not working for some of the inputs condition. To overcome this fault, novel Vedic multiplier is proposed and designed using less half adder and Full Adder. Simulation is carried out using Modelsim 6.3c. Synthesis and Implementation is carried out using Xilinx and FPGA Spartan 3.


INTRODUCTION
MAC unit is used in ALU block.As all of us know that the Computation unit is main unit of any technology (Cieplucha, 2013), which performs different arithmetic operations like as addition, subtraction and multiplication etc., also in some places it performs logical operations also like as AND, OR, INVERT, X-OR etc. which is dominant feature in the digital domain based applications (Deepak and Kailath, 2012).ALU is the execution unit which does not only perform Arithmetic operations but also logical operations.And that's why ALU is called as the heart of Microprocessor, Microcontrollers and CPUs.No technology can exist, without those operations which are performed by ALU (Shams et al., 1998).Every technology uses works upon those operations either fully or partially which are performed by ALU.
The DSP functions extensively make use of the Multiply Accumulate operation, for high performance Digital signal processing system (Itawadiya et al., 2013).A basic MAC architecture consist of a Multiplier and an accumulate adder organized as in Fig. 1.MAC unit compute the product of two numbers and adds the product to an accumulator register (Jaina et al., 2011).The output of register is fed back to one input of the adder as shown in Fig. 1 (Shanthala et al., 2009).

DESIGN OF MAC UNIT USING CONVENTIONAL VEDIC MULTIPLIER
Vedic multiplier can propose using different algorithm.In this study Urdhava-Tiryakbhyam algorithm is used to design the Vedic multiplier (Bansal et al., 2014).Urdhava-Tiryakbhyam is the common formula applicable to all cases of multiplication and also in the division of a huge number by another huge number.It means perpendicularly and diagonally (Huddar et al., 2013) (Fig. 2).
Conventional Vedic multiplier is constructed using Ripple Carry Adder (RCA).RCA consist of number of full adders and half adders.Conventional Vedic multiplier is not working properly, when the carry input has more than one number of ones.So it will be generate fault output, when the carry input consist of more number of one's (Kunchigi et al., 2012).

Proposed MAC unit using modified vedic multiplier:
In this research study, Modified Vedic multiplier is proposed to reduce the total number of half adder and full adder in order to rectify the fault, when the carry is 1.From the conventional Vedic multiplier,    9).Modified Vedic multiplier is shown in Fig. 3.It is used give the exact result, when the carry output is 1.Instead of 16 bit ripple carry adder (32 half adder), 8 half adder and one full adder is used in modified Vedic multiplier to reduce the area and delay than the conventional Vedic multiplier.So 22 half adder is reduced in the modified full adder and also when 15×11, it gives 165.This fault also rectifies using half adders (Table 1).

CONCLUSION
An efficient multiplier called modified Vedic multiplier has been proposed for MAC unit.The proposed multiplier provides low area and less delay by use of less number of full adder and half adder instead of ripple carry adder.In this study, hardware design and implementation of Field Programmable Gate Array based Multiplication and Accumulation (MAC) unit with modified Vedic multipliers is presented.The design was implemented on Xilinx Spartan 3 XC3S50 FPGA device.Comparative study of an efficient MAC unit with regular Vedic multiplier and modified Vedic multiplier was done.The Modified Vedic multiplier as compared to regular Vedic shows much more reduction in device Utilization.The proposed method offers 10% area, 10% delay and 5% power reduction than the existing architecture.Hence it is concluded that, modified Vedic multiplier based MAC unit provides an efficient method for reducing the power dissipation, delay and area.In future, the proposed MAC unit can be used in the digital FIR filter.

Table 1 :
Comparison of different MAC unit using regular and modified vedic multipliers