Modified Embedded Switched Inductor Z Source Inverter

A novel modified embedded switched inductor Z-source inverter is proposed by inserting the photovoltaic panels at various locations to improve the output voltage boosting performance. The proposed inverter have the concepts of embedded and switched inductor Z source network to have better features in terms of increased voltage boost inversion ability, continuous input current, reduced voltage stress on the switches/capacitors. Simulations are carried out by employing (120°) pulse width modulation scheme. Hardware implementation of the proposed topology of rating 150 W, 60 V is made and the results are experimentally verified. Switch device power and reliability evaluation of the proposed inverter are also calculated.


INTRODUCTION
Ever increasing energy consumption, cost of fossil fuels, soaring costs and exhaustible nature and worsening global environment have created a booming interest in renewable energy generation systems, one of which is photovoltaic.Such a system generates electricity by converting Sun's energy directly into electricity.Photovoltaic generated energy can be delivered to power system networks through grid connected inverters.Z source inverters are recent find in inverter topologies mostly used for photovoltaic applications because they have many advantages like better voltage boost and improved reliability than the other traditional voltage and current type inverters (Peng, 2003;Saravanan et al., 2011).Voltage type Z source inverters are classified based on number and location of input dc sources, Z networks and switching devices as reported in (Loh et al., 2010;Li et al., 2013).
Various Z source inverter topologies and its variants are reported in the literature focusing on renewable energy and adjustable speed drive applications (Loh et al., 2005;Saravanan et al., 2012a, b).Various Pulse Width Modulation (PWM) strategies employed in these topologies are discussed in Loh et al. (2005) and Ellabban et al. (2009).
The work reported in this study have the combined features of embedded ZSI (Loh et al., 2010) and Switched inductor Z Source Inverter (SLZSI) (Zhu et al., 2010) to provide better voltage boosting ability with smoother output voltage waveforms at reduced voltage stress on the capacitors.In addition, the proposed inverter avoids the start up inrush current that could destroy the devices and thereby inverter's reliability is improved.
A two level embedded Z source inverter (Loh et al., 2010) shown in Fig. 1, has dc sources embedded within X shaped LC impedance network.Here, even if one of the sources fails to feed power to the inverter at times of interruptions or fault conditions, continuous operation is possible by feeding power from the other source.
Switched inductor Z Source Inverter (SLZSI) (Zhu et al., 2010) shown in Fig. 2 has high voltage conversion ratios with a very short shoot through state.It consists of four inductors (L 1 , L 2 , L 3 and L 4 ), two capacitors (C 1 and C 2 ) and seven diodes (D, D 1 , D 2 , D 3 , D 4 , D 5 and D 6 ).The combinations of L 1 -L 3 -D 1 -D 3 -D 5 and L 2 -L 4 -D 2 -D 4 -D 6 act as the switched inductor cells.
Despite this increase in boost inversion, SLZSI has significant drawback namely current drawn from the source is discontinuous in nature.A decoupling capacitor bank at the front end is used to avoid the current discontinuity and protect the source.In addition, SLZSI cannot suppress the startup inrush current resulting in voltage and current spikes which can destroy the devices connected to it.
To overcome these problems, modified embedded switched inductor Z-source inverter topology is proposed in this study which has the concepts of embedded and switched inductor topologies to have better features, like: The proposed inverter topology is built by inserting dc sources into the X-shaped impedance network.Since the dc sources are connected directly to the impedance network's inductors, boosted dc current flows through the inverter smoothly.The modified inverter provides a continuous input current without adding an input passive filter and also exhibits a lower voltage stress on the capacitors with improved reliability.
The MESLZSI topology consist of four inductors and two capacitors for each cell, ( L 1 , L 2 , L 3 and L 4 ) and   (C Sci. Eng. Technol., 7(17): 3544-3552, 2014 3547 voltage sources to the main circuit.The corresponding in this state are V L1_non , , respectively.In second cell , D 10 , D 12 and D 13 ) are connected in series.are charged, whereas the transfer energy from the dc voltage sources to the main circuit.The corresponding voltages across L 5 , L 6 , L 7 and L 8 in this state are V L6_non , V L7_non and V L8_non , respectively.
In the shoot through states, the inverter side is shorted by both the upper and lower switching devices in the phase legs.
Control scheme employed: As discussed earlier, any modulation method (Loh et al., 2005(Loh et al., 2009) ) can be adopted to control the proposed MESLZSI.Figure 4

Switching device power calculation:
The Switching expressed as the product of voltage stress and current stress.The total SDP of an inverter system is defined as the aggregate of SDP of all switching devices used in the circuit (Miaosen and Alan, 2007b;Miaosen et al., 2007a).Total SDP is a measure of the total semiconductor device requirement, thus an important cost indicator of an inverter system: Total average SDP = (SDP) av = Im_avg 1 The typical values for the proposed inverter are listed as: base failure rate, ‫ג‬b = 0.00074; junction temperature factor, π T = 5.9; application factor, π A = 0.7; power rating factor, π R, = P 0.37 ; voltage stress factor, π S = 1, quality factor, π Q = 2.4, environment factor, π E = 6.0: ‫ג‬p, IGBT = 0.00074*5.9*0.7*35.08*1*0.7*6.0 = 0.45028 failure/10 6 h Using 6 IGBT's in the proposed inverter, the reliability can be calculated as: ‫ג‬p, inv = 6*0.4502failure/10 6 h = 2.70172 failure/10 6 h Mean Time to Failure (MTTF) for the system use in full life period is expressed as inverse of failure rate and, calculated as: MTTF = 1/λ = 1/2.7017failure/10^6 h = 10 6 / 2.7017 h = 37, 01, 373 h = 60.36 years Thus the reliability (estimated life) of the proposed inverter is theoretically calculated to be 60.36 years.

SIMULATION RESULTS
To verify the operation of proposed inverter, simulations are performed in MATLAB/SIMULINK environment, where the solver is chosen as variable step discrete with step of 1.0 µs with following PV system input voltages of values: V 1 , V 2 , V 3 = 12 V and V 4 = 24 V, collectively, V dc = 60 V; L 1 to L 8 = 2 mH C 1 , -C 4 = 10 µF and switching frequency, f s = 20 kHz employing 120° switching scheme with a modulation index of value one.The output ac voltage waveforms (peak value) obtained through simulation for the proposed inverter are around 100 V in all the phases A, B and C, respectively which are observed with LC filter as shown in Fig. 6 and 7 shows the switching sequence of the switches S 1 to S 6 .Table 1 provides a list of simulation parameters for the proposed inverter.Figure 11 shows the various operating units like PWM pulse generator, shoot through pulse generator, isolation opto coupler and impedance network are assembled to form the hardware of the proposed inverter.Various IC's and passive elements are used to build the proposed inverter.It has IC MCT2E for

CONCLUSION
A novel modified switched inductor ZSI is proposed for solar photo voltaic applications.Simulations are carried out by employing 120° pulse width modulation scheme.Hardware, for the proposed inverter is implemented.The simulation and hardware results agree to a great extent.The proposed inverter exhibits better performance and is most suitable for solar PV applications.

Fig. 1 :
Fig. 1: Two level embedded Z source inverter 1 , C 2 ) for first cell and (L 5 , L 6 , L 7 , L 8 ) and (C 1 , C 4 ) for second cell and seven diodes (D in , D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , D 8 , D 9 , D 10 , D 11 , D 12 , D 13 and D 14 ).The combinations of L 1 -L 3 -D 1 -D 3 -D 5 and L 2 -L 4 -D 2 -D 4 -D 6 act as the switched-inductor cells in a single cell.For the purpose of analysis, operating states of MESLZSI are simplified into shoot through and non shoot through states.In non shoot through states, the proposed inverter has six active states and two zero states in the inverter main circuit.During non shoot through state, in first cell D 1 , D 4 and D 7 are ON, whereas D 2 , D 3 , D 5 and D 6 are OFF.Inductors (L 1 -L 4 ) and (L 5 -L 8 ) are connected in series in this state.Capacitors C 1 and C 2 are charged, whereas the inductors L 1 , L 2 , L 3 and L 4 transfer energy from dc

Fig. 4 :
Fig. 4: PWM signal generating unit During the shoot through state, in first cell D 1 , D 4 and D 7 are off, whereas are ON.(L 1 , L 3 ) and (L 2 , L 4 ) are connected in parallel.Capacitors C 1 , C 2 , C 3 and C 4 are discharged, whereas inductors L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , L 7 and second cell D 8 , D 11 and D 14 are off, whereas D 12 and D 13 are on.(L 5 , L 7 ) and (L in parallel; Capacitors C 1 , C 2 , C 3 and whereas inductors L 1 , L 2 , L 3 , L 4 , L 5 energy.The circuit analysis for the proposed inverter based on the shoot through and non shoot through states are described below: In non shoot through state: depicts the pictorial representation of 120° mode of conduction of PWM generator.Here the triangular signal is carrier or switching signal of the inverter, whose switching frequency employed ranges from 10-20 kHz.The modulation generator produce sine wave signal that determines the pulse width and therefore the RMS voltage output of the inverter.For PWM signal generation, it requires both reference and carrier signals that feed into a comparator which creates output signals based on the diffe signals.Obtained PWM switching signals are shown in Fig.5.The proposed inverter consist of six switches named as S 1 , S 2 , S 3 , S 4 , S 5 , S 6 each device conduct for 120° phase shift.Sequence of firing is in the order61,  12, 23, 34, 45, 56, 61  and the gating signals are shifted from each other by 60°.Switching device power calculation: Device Power (SDP) is expressed in this state are V L5_non , , respectively.In the shoot through states, the inverter side is shorted by both the upper and lower switching devices in the phase legs.During the shoot through state, in first are off, whereas D 2 , D 3 , D 5 and D 6 ) are connected in parallel.are discharged, whereas and L 8 store energy.In are off, whereas D 9 , D 10 , L 6 , L 8 ) are connected and C 4 are discharged, 5 , L 6 , L 7 and L 8 store energy.The circuit analysis for the proposed inverter based on the shoot through and non shoot through states (i in4 = I L4 As discussed earlier, any 2005; Ellabban et al., 2009) can be adopted to control the proposed the pictorial representation mode of conduction of PWM generator.Here the triangular signal is carrier or switching signal of the inverter, whose switching frequency employed ranges 20 kHz.The modulation generator produces a sine wave signal that determines the pulse width and therefore the RMS voltage output of the inverter.For PWM signal generation, it requires both reference and carrier signals that feed into a comparator which creates output signals based on the difference between the signals.Obtained PWM switching signals are shown in Fig. 5.The proposed inverter consist of six switches each device conduct for Sequence of firing is in the order 61, and the gating signals are shifted = The average and peak currents through the device respectively Vm = The peak voltage induced on the devices The average and peak SDPs of proposed inverter can be calculated for the given typical values {P o = 150 W, M = 1, Cos ø = 1} as: (SDP) av = (2Po (2 -√3M) / (√3M -1Reliability analysis of the proposed inverter can be found out in terms of mean time to failure.IGBT Reliability (‫ג‬p) is expressed (Xue et al., 2012) as: ‫ג‬p, IGBT = ‫ג‬ b π T π A π R π S π Q π E failure/10 6 h (19)

Figure 8
Figure8shows the capacitor voltage waveforms connected to the inverter having the values as 32.66V in the capacitors V C1 and V C2 , where V C3 and V C4 have 21.93 V and 18.43 V respectively.The obtained value shows that the internal capacitors C 3 and C 4 are under reduced stress condition, which is the notable feature of this proposed topology.Figure9shows the inductor current waveforms of values I L1 = 3.245 A, I L2 = 3.252

Table 1 :
Simulation parameters of the proposed modified embedded