A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 µm CMOS Process

: Digital to (DAC) is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp) circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 µm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 µm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.


INTRODUCTION
Signal processing and storage are the key component in most modern electronic systems and in the digital domain. However, to interface with the real world, conversions between analog signals and digital signals are necessary (Akter et al., 2008a, b;Reaz et al., 2007a, b;Marufuzzaman et al., 2010;Reaz et al., 2003;Reaz et al., 2005). The advance in complementary Metal-Oxide-Semiconductor (CMOS) technologies has dramatically improved the system performance. Moreover, the requirement of a corresponding increase in data-converter performance is important. In the design of mixed-signal ASICs, it is often very expedient to have small calibration circuits, which can be used repetitively throughout the chip. Though, it is very important to make the calibration circuits as small as possible. As a result, in the layout the internal circuitry remains virtually unchanged.
Most of the electronic devices require two converters, which are Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). However, both the converters are equally important in CMOS design. DACs are often used in digital systems to provide complete interface with analog sensors and output devices for control systems such as those used in automotive engine controls (Reaz et al., 2006;Reaz and Wei, 2004;Mohd-Yasin et al., 2004;Mogaki et al., 2007). In addition, designing circuits with low voltage supplies is becoming necessary into the age of portable electronic devices. The low voltage introduces some limitations like the lack of headroom present for providing output currents from the DAC.
In this study, the analysis of op-amp circuit for 3bit DAC is presented. The design includes a weighted resistor and an op-amp circuit. The proposed design is implemented in CEDEC 0.18 µm CMOS process. The pre-simulation of DAC and post layout simulation is done with the same process under low supply voltage. Moreover, the proposed design is able to decrease the power dissipation of the overall circuit.
DAC architecture: There are several research has been done on DAC structure. Fu et al. (2011) worked on a 12-bit CMOS current steering DAC with a fully differential voltage output as shown in Fig. 1. The proposed DAC has adopted a segmented architecture in order to achieve a minimized die area and optimized performance. However, the design dissipates more power of 13.4 mW under 0.72~1.2 V as the supply voltages. Zhu et al. (2011) also describe a DAC circuit, which utilize the optimized circuit matching technique as shown in Fig. 2. During the design process, the working frequency band varies from 10 MHz to 200 MHz with a Spurious-Free Dynamic Range (SFDR) attenuating from 61dB to 40dB. Moreover, the measurement results of the differential nonlinearity and integral nonlinearity is 0.16 LSB and 0.4 LSB, respectively. The circuit also fabricated in a 0.5 µm single poly three-metal 5 V CMOS standard process. However, the whole chip occupies about 2.822 mm 2 On the other hand, Purighalla and Maundy (2011) has proposed a logarithmic DAC structure, which is shown in Fig. 3. The design presents an 84-dB dynamic range true logarithmic amplifier. Logarithmic ordering in the output is achieved as a function of control parameter X, which in turn is tuned digitally. However, the design produced power consumption as 13.2 mW with supply voltage as 1.65 V.
The DAC design as shown in Fig. 4 is proposed by Namburu et al. (2010), which includes CMOS drivers to switch the gates of a set of binary-weighted PMOS  (2002) technology. A Spurious-Free Dynamic Range (SFDR) of more than 30 dB has been measured over the complete Nyquist interval at sampling frequencies of 2 GS/s. The power consumption at a 2 GHz clock frequency for a near-Nyquist sinusoidal output signal equals only 12 mW. The block diagram of the proposed DAC is shown in Fig. 5. In addition, Palmers and Steyeart (2010) describes a 10-bit 5-5 segmented current steering DAC, which is implemented in a standard 130 nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The proposed DAC block diagram is shown in Fig. 6.
In this research, the design is employed weighted resistor and operational amplifier in order to develop as a 3-bit low power of DAC in CEDEC 0.18 µm CMOS process, which produces the lowest power consumption, compared to prior research studies.

PROPOSED METHODOLOGY
The proposed DAC design is based on conventional circuit of weighted summing amplifier as shown in Fig. 7. In this research, an op-amp is designed using the method proposed by Kumar and Kolhe (2011).
Though, the op-amp is designed for ADC design implementation, but in this research, the design method is followed to use it in DAC structure without capacitor and current with high voltage and low power consumption as shown in Fig. 8. From the schematic diagram it is shown that, M1, M2, M3 are PMOS transistors with the W/L = 1.4 µm/0.18 µm. On the other hand, M4, M5, M6, M7 and M8 are NMOS with the W/L = 0.9 µm/0.18 µm. In the schematic diagram, M4 is connected to Input Negative (INN) and M5 is The block diagram of the proposed 3-bit DAC circuit design is shown in Fig. 9. It is clear from the Fig. 9 that, the proposed design required switches, weighted resistor and op-amp circuit for the DAC. Digital inputs are driven throughout switches, resistor and op-amp to produce the output signal.

RESULTS AND DISCUSSION
27°C operating condition and CEDEC 0.18-µm CMOS process has been used to design the modified op-amp circuit. Simulations are executed to evaluate the circuit performance of the proposed op-amp. The design of DAC is simulated using ELDONET simulator of CEDEC 0.18 µm CMOS process. For simulation, a test-bench file is also required, which is shown in Fig.  10. A switch connects an input to a common ground. The supply voltage is 8 V for the test-bench schematic.  A switch connects an input either to a common voltage V or to a common ground. The inputs are weighted in a 4:2:1 relationship, so that the sequence of values 4 V0+2 V1+V2 is formed a binary-coded decimal number, which is illustrated in Table 1. The digital inputs control the switches and the amplifier provides the analog output.
The generated waveform for 3-bit weighted sum of DAC shown in Fig. 11, which is similar as the values mentioned in Table 2. When the input = 000, then VOUT = 0V and if input = 111, then the output VOUT = 7 V.
Moreover, the layout diagram of the proposed circuit is done with the CEDEC 0.18 µm CMOS   Zhu et al. (2011) 0.5 mm 8-bit 5V 117 mW - Purighalla and Maundy (2011) 0.18 µm 4-bit 1.65V 13.2 mW 1.5 mm² Namburu et al. (2010) 0.5 µm 10-bit 3V -0.067mm² Wu and Steyaert (2010) 90 nm 5-bit -12 mW 0.375 mm² Palmers and Steyeart (2010) 130 nm 10-bit 1.2/1.8V 23.6 mW 0.5 mm² process IC station tool. Figure 12 shows the layout of op amp for DAC which is successfully processed with the post layout simulation. Besides that, the analysis of the W/L ratio for both PMOS and NMOS has done in order to get better power consumption and delay, which is generated for each range. Table 2 shows the value of delay and power dissipation for different sizes of PMOS and NMOS. From the Table 2, it is obvious that the delays are remaining same for each range of W/L for both PMOS  Table 2.
A performance evaluation study among different design methods and this study on the low voltage functionality with power consumption are listed in Table 3. Based on the comparison study, it is found that the proposed design is able to produce low power consumption only 43.6 nW than the other research studies. However, it operates at high power supply voltage, which is 8 V. In addition, the designed DAC is required only 143.17 µm as the layout area, which is also less than the previous research studies. Moreover, the designed DAC is able to perform in a better way in terms of power consumption, lower supply voltage, active layout are, etc. So it is obvious from the Table 3 that, the designed DAC can be applicable to low power applications.

CONCLUSION
An improved design and a comparative study of low power op-amp circuit for 3-bit DAC presented in this research. The modified circuit has been designed by using the CEDEC 0.18-µm CMOS process. According to the performance evaluation results, it has been proven that, the circuit is capable of consuming low power 43.60 nw under supply voltage as 8 V. Furthermore, the measured results confirm that this low power op-amp is free from the power delineation caused by the temperature change. Additionally, the circuit size reduced significantly with the active area 143.17 µm.