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Abstract
In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case.
From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.
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References
- ARITH research group, Aoki Lab., Tohoku University, “Hardware algorithms for arithmetic modulesâ€
- M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall, ISBN 0-13-21450-3, pp.119-123, 1979.
- Nowick, “Conditional Sum Adders: Detailed Implementationâ€
- Da Huang and Afsaneh Nassery, “Modified booth encoding radix-4 8-bit multiplierâ€, unpublished.
- Beril Seda Çiftci, “Design and realization of a high speed 64 x 64 – bit multiplier for low power applicationsâ€, thesis, Sabanci University, 1979.
- Magnus Sjalander, “Efficient reconfigurable multipliers based on the twin- precision techniqueâ€, thesis, Charlmers University, 2006
References
ARITH research group, Aoki Lab., Tohoku University, “Hardware algorithms for arithmetic modulesâ€
M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall, ISBN 0-13-21450-3, pp.119-123, 1979.
Nowick, “Conditional Sum Adders: Detailed Implementationâ€
Da Huang and Afsaneh Nassery, “Modified booth encoding radix-4 8-bit multiplierâ€, unpublished.
Beril Seda Çiftci, “Design and realization of a high speed 64 x 64 – bit multiplier for low power applicationsâ€, thesis, Sabanci University, 1979.
Magnus Sjalander, “Efficient reconfigurable multipliers based on the twin- precision techniqueâ€, thesis, Charlmers University, 2006