FIR Filter Design using Multiple Constant Multiplication (MCM) Method with Modified Ripple Carry Adder

─ FIR filters are used in digital signal processing. These filters are used as filtering unit for fixed and reconfigurable applications. This work proposes a multiple constant multiplication (MCM) method to reduce the area delay product (ADP) of the FIR filters that are used for fixed applications. The existing work comprises ripple carry adders that are used in adder unit, which consumes more area and delay. In order to overcome the drawbacks of existing work, the proposed work is designed which is based on modified ripple carry adders that are used in adder unit. The simulation is done using VHDL in Xilinx ISE 12.1.The parameters such as area, power and delay are compared with the existing MCM method.


I. INTRODUCTION
Digital filters plays major role in DSP, due to its advance performance is one of the key reasons that DSP has become so popular. Filters are used for two process, signal separation and signal restoration. Signal separation is needed when a signal have distorted with interference, noise, or other signals. Signal restoration is used when a signal has been distorted in some way. Digital filters can be implemented in two ways, by convolution (also called finite impulse response or FIR) and by recursion (also called infinite impulse response or IIR). Filters carried out by convolution have good performance than filters used in recursion, but execute much more slowly as the multiplicand has a limited number of values. From this reason, it is attractive to carry out the multiplication by using shifts and adds. The shifts can be realized by using hardwired shifters and hence they are essentially free. Furthermore, we can reduce the area of adder by introducing common sub expression elimination CSE techniques. The CSE tackles the multiple constant multiplication (MCM) problem by minimizing the number of additions through extracting common parts among the constants represented in canonic signed digit (CSD) . There are three different kinds of common subexpressions horizontal, vertical and oblique. Due to the computational complexity and the fact that linear phase FIR filters are symmetrical, the search for redundant computations in multiplier block is normally connected to horizontal common subexpressions. This paper proposes a combination of horizontal and vertical CSE. We have presented an improved horizontal and vertical CSE which is able to reduce the number of adders.

II. COMPUTATIONAL ANALYSIS AND MATHEMATICAL FORMULATION OF BLOCK TRANSPOSE FORM FIR FILTER
The output of N length FIR filter can be computed using the relation where, y(n)-Filter output h (i)-Filter coefficient x(n)-Input The computation of (1) can be expressed by the recurrence relation The general block diagram of FIR filter is shown in figure 1 In FIR filter, the multiplication operation is performed between one common variable and many constants (the coefficients) and known as the multiple constant multiplication (MCM). The algorithms that are introduced before is to implement this MCM for an efficient FIR filter design can be categorized in two main groups: 1) graph based algorithms and 2) common sub-expression elimination (CSE) algorithms. Most of these graph based or CSE algorithms presented earlier are used to obtain efficient FIR filter architecture by running the algorithms on a particular set of coefficients for some time on a highly efficient computing platform.We discuss the derivation of MCM units for transpose form block FIR filter, and the design of proposed structure for fixed filters. For fixed-coefficient implementation, The general block diagram for MCM is given in figure 2.The proposed MCM structure is shown in figure The multiplications are required to be mapped to the MCM units for a low-complexity realization. In the following, we show that the proposed formulation for MCM-based implementation of block FIR filter makes use of the symmetry in input matrix to perform horizontal and vertical common subexpression elimination and to minimize the number of shift-add operations in the MCM blocks. To illustrate the computation for L = 4 and N = 16. The input matrix contains six-input samples {x(4k),

IV. PROPOSED MCM METHOD
The proposed MCM-based structure for FIR filters for block size L = 4 is shown in Fig. 3 for the purpose of illustration. The MCM-based structure (shown in Fig. 3) involves six MCM blocks corresponding to six input samples. Each MCM block computes the necessary product terms as shown in Table I. The subexpressions of the MCM blocks are shift computed in the adder network to obtain the inner-product output (rl,m), for 0 ≤ l ≤ L − 1 and 0 ≤ m ≤ (N/L) − 1 corresponding to the matrix product of (14). The innerproduct values are finally added in the PAU of to obtain a block of filter output. Published by :

A. Coefficient Storage Unit
The Coefficient storage Unit consists of Read Only Memory (ROM) for storing the Fixed Coefficient Constants with Counter. The Counter architecture is used for to get the value from the ROM Memory.

B. Register Unit
The Register Unit consists of adders to add the given inputs; the Block diagram of Register unit is as shown in the figure. The input which is given from the register unit is multiplied along with the coefficients inorder to get the output og the filter.The multiplication along with the addition is performed in the inner product unit which is shown in figure5 .Each inner product unit comprises of inner product cell which is shown in figure 6   Published by :